2 * LatticeMico32 helper routines.
4 * Copyright (c) 2010-2014 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "qemu/host-utils.h"
24 #include "sysemu/sysemu.h"
25 #include "hw/semihosting/semihost.h"
28 bool lm32_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
29 MMUAccessType access_type
, int mmu_idx
,
30 bool probe
, uintptr_t retaddr
)
32 LM32CPU
*cpu
= LM32_CPU(cs
);
33 CPULM32State
*env
= &cpu
->env
;
36 address
&= TARGET_PAGE_MASK
;
38 if (env
->flags
& LM32_FLAG_IGNORE_MSB
) {
39 tlb_set_page(cs
, address
, address
& 0x7fffffff, prot
, mmu_idx
,
42 tlb_set_page(cs
, address
, address
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
47 hwaddr
lm32_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
49 LM32CPU
*cpu
= LM32_CPU(cs
);
51 addr
&= TARGET_PAGE_MASK
;
52 if (cpu
->env
.flags
& LM32_FLAG_IGNORE_MSB
) {
53 return addr
& 0x7fffffff;
59 void lm32_breakpoint_insert(CPULM32State
*env
, int idx
, target_ulong address
)
61 cpu_breakpoint_insert(env_cpu(env
), address
, BP_CPU
,
62 &env
->cpu_breakpoint
[idx
]);
65 void lm32_breakpoint_remove(CPULM32State
*env
, int idx
)
67 if (!env
->cpu_breakpoint
[idx
]) {
71 cpu_breakpoint_remove_by_ref(env_cpu(env
), env
->cpu_breakpoint
[idx
]);
72 env
->cpu_breakpoint
[idx
] = NULL
;
75 void lm32_watchpoint_insert(CPULM32State
*env
, int idx
, target_ulong address
,
81 case LM32_WP_DISABLED
:
85 flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
| BP_MEM_READ
;
88 flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
| BP_MEM_WRITE
;
90 case LM32_WP_READ_WRITE
:
91 flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
| BP_MEM_ACCESS
;
96 cpu_watchpoint_insert(env_cpu(env
), address
, 1, flags
,
97 &env
->cpu_watchpoint
[idx
]);
101 void lm32_watchpoint_remove(CPULM32State
*env
, int idx
)
103 if (!env
->cpu_watchpoint
[idx
]) {
107 cpu_watchpoint_remove_by_ref(env_cpu(env
), env
->cpu_watchpoint
[idx
]);
108 env
->cpu_watchpoint
[idx
] = NULL
;
111 static bool check_watchpoints(CPULM32State
*env
)
113 LM32CPU
*cpu
= env_archcpu(env
);
116 for (i
= 0; i
< cpu
->num_watchpoints
; i
++) {
117 if (env
->cpu_watchpoint
[i
] &&
118 env
->cpu_watchpoint
[i
]->flags
& BP_WATCHPOINT_HIT
) {
125 void lm32_debug_excp_handler(CPUState
*cs
)
127 LM32CPU
*cpu
= LM32_CPU(cs
);
128 CPULM32State
*env
= &cpu
->env
;
131 if (cs
->watchpoint_hit
) {
132 if (cs
->watchpoint_hit
->flags
& BP_CPU
) {
133 cs
->watchpoint_hit
= NULL
;
134 if (check_watchpoints(env
)) {
135 raise_exception(env
, EXCP_WATCHPOINT
);
137 cpu_loop_exit_noexc(cs
);
141 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
142 if (bp
->pc
== env
->pc
) {
143 if (bp
->flags
& BP_CPU
) {
144 raise_exception(env
, EXCP_BREAKPOINT
);
152 void lm32_cpu_do_interrupt(CPUState
*cs
)
154 LM32CPU
*cpu
= LM32_CPU(cs
);
155 CPULM32State
*env
= &cpu
->env
;
157 qemu_log_mask(CPU_LOG_INT
,
158 "exception at pc=%x type=%x\n", env
->pc
, cs
->exception_index
);
160 switch (cs
->exception_index
) {
161 case EXCP_SYSTEMCALL
:
162 if (unlikely(semihosting_enabled())) {
163 /* do_semicall() returns true if call was handled. Otherwise
164 * do the normal exception handling. */
165 if (lm32_cpu_do_semihosting(cs
)) {
171 case EXCP_INSN_BUS_ERROR
:
172 case EXCP_DATA_BUS_ERROR
:
173 case EXCP_DIVIDE_BY_ZERO
:
175 /* non-debug exceptions */
176 env
->regs
[R_EA
] = env
->pc
;
177 env
->ie
|= (env
->ie
& IE_IE
) ? IE_EIE
: 0;
179 if (env
->dc
& DC_RE
) {
180 env
->pc
= env
->deba
+ (cs
->exception_index
* 32);
182 env
->pc
= env
->eba
+ (cs
->exception_index
* 32);
184 log_cpu_state_mask(CPU_LOG_INT
, cs
, 0);
186 case EXCP_BREAKPOINT
:
187 case EXCP_WATCHPOINT
:
188 /* debug exceptions */
189 env
->regs
[R_BA
] = env
->pc
;
190 env
->ie
|= (env
->ie
& IE_IE
) ? IE_BIE
: 0;
192 env
->pc
= env
->deba
+ (cs
->exception_index
* 32);
193 log_cpu_state_mask(CPU_LOG_INT
, cs
, 0);
196 cpu_abort(cs
, "unhandled exception type=%d\n",
197 cs
->exception_index
);
202 bool lm32_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
204 LM32CPU
*cpu
= LM32_CPU(cs
);
205 CPULM32State
*env
= &cpu
->env
;
207 if ((interrupt_request
& CPU_INTERRUPT_HARD
) && (env
->ie
& IE_IE
)) {
208 cs
->exception_index
= EXCP_IRQ
;
209 lm32_cpu_do_interrupt(cs
);
215 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
216 * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
217 * 0x80000000-0xffffffff is not cached and used to access IO devices. */
218 void cpu_lm32_set_phys_msb_ignore(CPULM32State
*env
, int value
)
221 env
->flags
|= LM32_FLAG_IGNORE_MSB
;
223 env
->flags
&= ~LM32_FLAG_IGNORE_MSB
;