hw/ppc/spapr_irq.c

   1 /*
   2  * QEMU PowerPC sPAPR IRQ interface
   3  *
   4  * Copyright (c) 2018, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "qemu/log.h"
  12 #include "qemu/error-report.h"
  13 #include "qapi/error.h"
  14 #include "hw/ppc/spapr.h"
  15 #include "hw/ppc/spapr_cpu_core.h"
  16 #include "hw/ppc/spapr_xive.h"
  17 #include "hw/ppc/xics.h"
  18 #include "hw/ppc/xics_spapr.h"
  19 #include "sysemu/kvm.h"
  20
  21 #include "trace.h"
  22
  23 void spapr_irq_msi_init(sPAPRMachineState *spapr, uint32_t nr_msis)
  24 {
  25     spapr->irq_map_nr = nr_msis;
  26     spapr->irq_map = bitmap_new(spapr->irq_map_nr);
  27 }
  28
  29 int spapr_irq_msi_alloc(sPAPRMachineState *spapr, uint32_t num, bool align,
  30                         Error **errp)
  31 {
  32     int irq;
  33
  34     /*
  35      * The 'align_mask' parameter of bitmap_find_next_zero_area()
  36      * should be one less than a power of 2; 0 means no
  37      * alignment. Adapt the 'align' value of the former allocator
  38      * to fit the requirements of bitmap_find_next_zero_area()
  39      */
  40     align -= 1;
  41
  42     irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
  43                                      align);
  44     if (irq == spapr->irq_map_nr) {
  45         error_setg(errp, "can't find a free %d-IRQ block", num);
  46         return -1;
  47     }
  48
  49     bitmap_set(spapr->irq_map, irq, num);
  50
  51     return irq + SPAPR_IRQ_MSI;
  52 }
  53
  54 void spapr_irq_msi_free(sPAPRMachineState *spapr, int irq, uint32_t num)
  55 {
  56     bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
  57 }
  58
  59 void spapr_irq_msi_reset(sPAPRMachineState *spapr)
  60 {
  61     bitmap_clear(spapr->irq_map, 0, spapr->irq_map_nr);
  62 }
  63
  64
  65 /*
  66  * XICS IRQ backend.
  67  */
  68
  69 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
  70                                   const char *type_ics,
  71                                   int nr_irqs, Error **errp)
  72 {
  73     Error *local_err = NULL;
  74     Object *obj;
  75
  76     obj = object_new(type_ics);
  77     object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
  78     object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
  79                                    &error_abort);
  80     object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
  81     if (local_err) {
  82         goto error;
  83     }
  84     object_property_set_bool(obj, true, "realized", &local_err);
  85     if (local_err) {
  86         goto error;
  87     }
  88
  89     return ICS_BASE(obj);
  90
  91 error:
  92     error_propagate(errp, local_err);
  93     return NULL;
  94 }
  95
  96 static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
  97 {
  98     MachineState *machine = MACHINE(spapr);
  99     int nr_irqs = spapr->irq->nr_irqs;
 100     Error *local_err = NULL;
 101
 102     if (kvm_enabled()) {
 103         if (machine_kernel_irqchip_allowed(machine) &&
 104             !xics_kvm_init(spapr, &local_err)) {
 105             spapr->icp_type = TYPE_KVM_ICP;
 106             spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs,
 107                                           &local_err);
 108         }
 109         if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
 110             error_prepend(&local_err,
 111                           "kernel_irqchip requested but unavailable: ");
 112             goto error;
 113         }
 114         error_free(local_err);
 115         local_err = NULL;
 116     }
 117
 118     if (!spapr->ics) {
 119         xics_spapr_init(spapr);
 120         spapr->icp_type = TYPE_ICP;
 121         spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs,
 122                                       &local_err);
 123     }
 124
 125 error:
 126     error_propagate(errp, local_err);
 127 }
 128
 129 #define ICS_IRQ_FREE(ics, srcno)   \
 130     (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
 131
 132 static int spapr_irq_claim_xics(sPAPRMachineState *spapr, int irq, bool lsi,
 133                                 Error **errp)
 134 {
 135     ICSState *ics = spapr->ics;
 136
 137     assert(ics);
 138
 139     if (!ics_valid_irq(ics, irq)) {
 140         error_setg(errp, "IRQ %d is invalid", irq);
 141         return -1;
 142     }
 143
 144     if (!ICS_IRQ_FREE(ics, irq - ics->offset)) {
 145         error_setg(errp, "IRQ %d is not free", irq);
 146         return -1;
 147     }
 148
 149     ics_set_irq_type(ics, irq - ics->offset, lsi);
 150     return 0;
 151 }
 152
 153 static void spapr_irq_free_xics(sPAPRMachineState *spapr, int irq, int num)
 154 {
 155     ICSState *ics = spapr->ics;
 156     uint32_t srcno = irq - ics->offset;
 157     int i;
 158
 159     if (ics_valid_irq(ics, irq)) {
 160         trace_spapr_irq_free(0, irq, num);
 161         for (i = srcno; i < srcno + num; ++i) {
 162             if (ICS_IRQ_FREE(ics, i)) {
 163                 trace_spapr_irq_free_warn(0, i);
 164             }
 165             memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
 166         }
 167     }
 168 }
 169
 170 static qemu_irq spapr_qirq_xics(sPAPRMachineState *spapr, int irq)
 171 {
 172     ICSState *ics = spapr->ics;
 173     uint32_t srcno = irq - ics->offset;
 174
 175     if (ics_valid_irq(ics, irq)) {
 176         return spapr->qirqs[srcno];
 177     }
 178
 179     return NULL;
 180 }
 181
 182 static void spapr_irq_print_info_xics(sPAPRMachineState *spapr, Monitor *mon)
 183 {
 184     CPUState *cs;
 185
 186     CPU_FOREACH(cs) {
 187         PowerPCCPU *cpu = POWERPC_CPU(cs);
 188
 189         icp_pic_print_info(spapr_cpu_state(cpu)->icp, mon);
 190     }
 191
 192     ics_pic_print_info(spapr->ics, mon);
 193 }
 194
 195 static void spapr_irq_cpu_intc_create_xics(sPAPRMachineState *spapr,
 196                                            PowerPCCPU *cpu, Error **errp)
 197 {
 198     Error *local_err = NULL;
 199     Object *obj;
 200     sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
 201
 202     obj = icp_create(OBJECT(cpu), spapr->icp_type, XICS_FABRIC(spapr),
 203                      &local_err);
 204     if (local_err) {
 205         error_propagate(errp, local_err);
 206         return;
 207     }
 208
 209     spapr_cpu->icp = ICP(obj);
 210 }
 211
 212 static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
 213 {
 214     if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
 215         CPUState *cs;
 216         CPU_FOREACH(cs) {
 217             PowerPCCPU *cpu = POWERPC_CPU(cs);
 218             icp_resend(spapr_cpu_state(cpu)->icp);
 219         }
 220     }
 221     return 0;
 222 }
 223
 224 static void spapr_irq_set_irq_xics(void *opaque, int srcno, int val)
 225 {
 226     sPAPRMachineState *spapr = opaque;
 227     MachineState *machine = MACHINE(opaque);
 228
 229     if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) {
 230         ics_kvm_set_irq(spapr->ics, srcno, val);
 231     } else {
 232         ics_simple_set_irq(spapr->ics, srcno, val);
 233     }
 234 }
 235
 236 static void spapr_irq_reset_xics(sPAPRMachineState *spapr, Error **errp)
 237 {
 238     /* TODO: create the KVM XICS device */
 239 }
 240
 241 #define SPAPR_IRQ_XICS_NR_IRQS     0x1000
 242 #define SPAPR_IRQ_XICS_NR_MSIS     \
 243     (XICS_IRQ_BASE + SPAPR_IRQ_XICS_NR_IRQS - SPAPR_IRQ_MSI)
 244
 245 sPAPRIrq spapr_irq_xics = {
 246     .nr_irqs     = SPAPR_IRQ_XICS_NR_IRQS,
 247     .nr_msis     = SPAPR_IRQ_XICS_NR_MSIS,
 248     .ov5         = SPAPR_OV5_XIVE_LEGACY,
 249
 250     .init        = spapr_irq_init_xics,
 251     .claim       = spapr_irq_claim_xics,
 252     .free        = spapr_irq_free_xics,
 253     .qirq        = spapr_qirq_xics,
 254     .print_info  = spapr_irq_print_info_xics,
 255     .dt_populate = spapr_dt_xics,
 256     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
 257     .post_load   = spapr_irq_post_load_xics,
 258     .reset       = spapr_irq_reset_xics,
 259     .set_irq     = spapr_irq_set_irq_xics,
 260 };
 261
 262 /*
 263  * XIVE IRQ backend.
 264  */
 265 static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
 266 {
 267     MachineState *machine = MACHINE(spapr);
 268     uint32_t nr_servers = spapr_max_server_number(spapr);
 269     DeviceState *dev;
 270     int i;
 271
 272     /* KVM XIVE device not yet available */
 273     if (kvm_enabled()) {
 274         if (machine_kernel_irqchip_required(machine)) {
 275             error_setg(errp, "kernel_irqchip requested. no KVM XIVE support");
 276             return;
 277         }
 278     }
 279
 280     dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
 281     qdev_prop_set_uint32(dev, "nr-irqs", spapr->irq->nr_irqs);
 282     /*
 283      * 8 XIVE END structures per CPU. One for each available priority
 284      */
 285     qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
 286     qdev_init_nofail(dev);
 287
 288     spapr->xive = SPAPR_XIVE(dev);
 289
 290     /* Enable the CPU IPIs */
 291     for (i = 0; i < nr_servers; ++i) {
 292         spapr_xive_irq_claim(spapr->xive, SPAPR_IRQ_IPI + i, false);
 293     }
 294
 295     spapr_xive_hcall_init(spapr);
 296 }
 297
 298 static int spapr_irq_claim_xive(sPAPRMachineState *spapr, int irq, bool lsi,
 299                                 Error **errp)
 300 {
 301     if (!spapr_xive_irq_claim(spapr->xive, irq, lsi)) {
 302         error_setg(errp, "IRQ %d is invalid", irq);
 303         return -1;
 304     }
 305     return 0;
 306 }
 307
 308 static void spapr_irq_free_xive(sPAPRMachineState *spapr, int irq, int num)
 309 {
 310     int i;
 311
 312     for (i = irq; i < irq + num; ++i) {
 313         spapr_xive_irq_free(spapr->xive, i);
 314     }
 315 }
 316
 317 static qemu_irq spapr_qirq_xive(sPAPRMachineState *spapr, int irq)
 318 {
 319     sPAPRXive *xive = spapr->xive;
 320
 321     if (irq >= xive->nr_irqs) {
 322         return NULL;
 323     }
 324
 325     /* The sPAPR machine/device should have claimed the IRQ before */
 326     assert(xive_eas_is_valid(&xive->eat[irq]));
 327
 328     return spapr->qirqs[irq];
 329 }
 330
 331 static void spapr_irq_print_info_xive(sPAPRMachineState *spapr,
 332                                       Monitor *mon)
 333 {
 334     CPUState *cs;
 335
 336     CPU_FOREACH(cs) {
 337         PowerPCCPU *cpu = POWERPC_CPU(cs);
 338
 339         xive_tctx_pic_print_info(spapr_cpu_state(cpu)->tctx, mon);
 340     }
 341
 342     spapr_xive_pic_print_info(spapr->xive, mon);
 343 }
 344
 345 static void spapr_irq_cpu_intc_create_xive(sPAPRMachineState *spapr,
 346                                            PowerPCCPU *cpu, Error **errp)
 347 {
 348     Error *local_err = NULL;
 349     Object *obj;
 350     sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
 351
 352     obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(spapr->xive), &local_err);
 353     if (local_err) {
 354         error_propagate(errp, local_err);
 355         return;
 356     }
 357
 358     spapr_cpu->tctx = XIVE_TCTX(obj);
 359
 360     /*
 361      * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
 362      * don't beneficiate from the reset of the XIVE IRQ backend
 363      */
 364     spapr_xive_set_tctx_os_cam(spapr_cpu->tctx);
 365 }
 366
 367 static int spapr_irq_post_load_xive(sPAPRMachineState *spapr, int version_id)
 368 {
 369     return 0;
 370 }
 371
 372 static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
 373 {
 374     CPUState *cs;
 375
 376     CPU_FOREACH(cs) {
 377         PowerPCCPU *cpu = POWERPC_CPU(cs);
 378
 379         /* (TCG) Set the OS CAM line of the thread interrupt context. */
 380         spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx);
 381     }
 382
 383     /* Activate the XIVE MMIOs */
 384     spapr_xive_mmio_set_enabled(spapr->xive, true);
 385 }
 386
 387 static void spapr_irq_set_irq_xive(void *opaque, int srcno, int val)
 388 {
 389     sPAPRMachineState *spapr = opaque;
 390
 391     xive_source_set_irq(&spapr->xive->source, srcno, val);
 392 }
 393
 394 /*
 395  * XIVE uses the full IRQ number space. Set it to 8K to be compatible
 396  * with XICS.
 397  */
 398
 399 #define SPAPR_IRQ_XIVE_NR_IRQS     0x2000
 400 #define SPAPR_IRQ_XIVE_NR_MSIS     (SPAPR_IRQ_XIVE_NR_IRQS - SPAPR_IRQ_MSI)
 401
 402 sPAPRIrq spapr_irq_xive = {
 403     .nr_irqs     = SPAPR_IRQ_XIVE_NR_IRQS,
 404     .nr_msis     = SPAPR_IRQ_XIVE_NR_MSIS,
 405     .ov5         = SPAPR_OV5_XIVE_EXPLOIT,
 406
 407     .init        = spapr_irq_init_xive,
 408     .claim       = spapr_irq_claim_xive,
 409     .free        = spapr_irq_free_xive,
 410     .qirq        = spapr_qirq_xive,
 411     .print_info  = spapr_irq_print_info_xive,
 412     .dt_populate = spapr_dt_xive,
 413     .cpu_intc_create = spapr_irq_cpu_intc_create_xive,
 414     .post_load   = spapr_irq_post_load_xive,
 415     .reset       = spapr_irq_reset_xive,
 416     .set_irq     = spapr_irq_set_irq_xive,
 417 };
 418
 419 /*
 420  * Dual XIVE and XICS IRQ backend.
 421  *
 422  * Both interrupt mode, XIVE and XICS, objects are created but the
 423  * machine starts in legacy interrupt mode (XICS). It can be changed
 424  * by the CAS negotiation process and, in that case, the new mode is
 425  * activated after an extra machine reset.
 426  */
 427
 428 /*
 429  * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
 430  * default.
 431  */
 432 static sPAPRIrq *spapr_irq_current(sPAPRMachineState *spapr)
 433 {
 434     return spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT) ?
 435         &spapr_irq_xive : &spapr_irq_xics;
 436 }
 437
 438 static void spapr_irq_init_dual(sPAPRMachineState *spapr, Error **errp)
 439 {
 440     MachineState *machine = MACHINE(spapr);
 441     Error *local_err = NULL;
 442
 443     if (kvm_enabled() && machine_kernel_irqchip_allowed(machine)) {
 444         error_setg(errp, "No KVM support for the 'dual' machine");
 445         return;
 446     }
 447
 448     spapr_irq_xics.init(spapr, &local_err);
 449     if (local_err) {
 450         error_propagate(errp, local_err);
 451         return;
 452     }
 453
 454     /*
 455      * Align the XICS and the XIVE IRQ number space under QEMU.
 456      *
 457      * However, the XICS KVM device still considers that the IRQ
 458      * numbers should start at XICS_IRQ_BASE (0x1000). Either we
 459      * should introduce a KVM device ioctl to set the offset or ignore
 460      * the lower 4K numbers when using the get/set ioctl of the XICS
 461      * KVM device. The second option seems the least intrusive.
 462      */
 463     spapr->ics->offset = 0;
 464
 465     spapr_irq_xive.init(spapr, &local_err);
 466     if (local_err) {
 467         error_propagate(errp, local_err);
 468         return;
 469     }
 470 }
 471
 472 static int spapr_irq_claim_dual(sPAPRMachineState *spapr, int irq, bool lsi,
 473                                 Error **errp)
 474 {
 475     Error *local_err = NULL;
 476     int ret;
 477
 478     ret = spapr_irq_xics.claim(spapr, irq, lsi, &local_err);
 479     if (local_err) {
 480         error_propagate(errp, local_err);
 481         return ret;
 482     }
 483
 484     ret = spapr_irq_xive.claim(spapr, irq, lsi, &local_err);
 485     if (local_err) {
 486         error_propagate(errp, local_err);
 487         return ret;
 488     }
 489
 490     return ret;
 491 }
 492
 493 static void spapr_irq_free_dual(sPAPRMachineState *spapr, int irq, int num)
 494 {
 495     spapr_irq_xics.free(spapr, irq, num);
 496     spapr_irq_xive.free(spapr, irq, num);
 497 }
 498
 499 static qemu_irq spapr_qirq_dual(sPAPRMachineState *spapr, int irq)
 500 {
 501     sPAPRXive *xive = spapr->xive;
 502     ICSState *ics = spapr->ics;
 503
 504     if (irq >= spapr->irq->nr_irqs) {
 505         return NULL;
 506     }
 507
 508     /*
 509      * The IRQ number should have been claimed under both interrupt
 510      * controllers.
 511      */
 512     assert(!ICS_IRQ_FREE(ics, irq - ics->offset));
 513     assert(xive_eas_is_valid(&xive->eat[irq]));
 514
 515     return spapr->qirqs[irq];
 516 }
 517
 518 static void spapr_irq_print_info_dual(sPAPRMachineState *spapr, Monitor *mon)
 519 {
 520     spapr_irq_current(spapr)->print_info(spapr, mon);
 521 }
 522
 523 static void spapr_irq_dt_populate_dual(sPAPRMachineState *spapr,
 524                                        uint32_t nr_servers, void *fdt,
 525                                        uint32_t phandle)
 526 {
 527     spapr_irq_current(spapr)->dt_populate(spapr, nr_servers, fdt, phandle);
 528 }
 529
 530 static void spapr_irq_cpu_intc_create_dual(sPAPRMachineState *spapr,
 531                                            PowerPCCPU *cpu, Error **errp)
 532 {
 533     Error *local_err = NULL;
 534
 535     spapr_irq_xive.cpu_intc_create(spapr, cpu, &local_err);
 536     if (local_err) {
 537         error_propagate(errp, local_err);
 538         return;
 539     }
 540
 541     spapr_irq_xics.cpu_intc_create(spapr, cpu, errp);
 542 }
 543
 544 static int spapr_irq_post_load_dual(sPAPRMachineState *spapr, int version_id)
 545 {
 546     /*
 547      * Force a reset of the XIVE backend after migration. The machine
 548      * defaults to XICS at startup.
 549      */
 550     if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {
 551         spapr_irq_xive.reset(spapr, &error_fatal);
 552     }
 553
 554     return spapr_irq_current(spapr)->post_load(spapr, version_id);
 555 }
 556
 557 static void spapr_irq_reset_dual(sPAPRMachineState *spapr, Error **errp)
 558 {
 559     /*
 560      * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
 561      * if selected.
 562      */
 563     spapr_xive_mmio_set_enabled(spapr->xive, false);
 564
 565     spapr_irq_current(spapr)->reset(spapr, errp);
 566 }
 567
 568 static void spapr_irq_set_irq_dual(void *opaque, int srcno, int val)
 569 {
 570     sPAPRMachineState *spapr = opaque;
 571
 572     spapr_irq_current(spapr)->set_irq(spapr, srcno, val);
 573 }
 574
 575 /*
 576  * Define values in sync with the XIVE and XICS backend
 577  */
 578 #define SPAPR_IRQ_DUAL_NR_IRQS     0x2000
 579 #define SPAPR_IRQ_DUAL_NR_MSIS     (SPAPR_IRQ_DUAL_NR_IRQS - SPAPR_IRQ_MSI)
 580
 581 sPAPRIrq spapr_irq_dual = {
 582     .nr_irqs     = SPAPR_IRQ_DUAL_NR_IRQS,
 583     .nr_msis     = SPAPR_IRQ_DUAL_NR_MSIS,
 584     .ov5         = SPAPR_OV5_XIVE_BOTH,
 585
 586     .init        = spapr_irq_init_dual,
 587     .claim       = spapr_irq_claim_dual,
 588     .free        = spapr_irq_free_dual,
 589     .qirq        = spapr_qirq_dual,
 590     .print_info  = spapr_irq_print_info_dual,
 591     .dt_populate = spapr_irq_dt_populate_dual,
 592     .cpu_intc_create = spapr_irq_cpu_intc_create_dual,
 593     .post_load   = spapr_irq_post_load_dual,
 594     .reset       = spapr_irq_reset_dual,
 595     .set_irq     = spapr_irq_set_irq_dual
 596 };
 597
 598 /*
 599  * sPAPR IRQ frontend routines for devices
 600  */
 601 void spapr_irq_init(sPAPRMachineState *spapr, Error **errp)
 602 {
 603     /* Initialize the MSI IRQ allocator. */
 604     if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
 605         spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
 606     }
 607
 608     spapr->irq->init(spapr, errp);
 609
 610     spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr,
 611                                       spapr->irq->nr_irqs);
 612 }
 613
 614 int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp)
 615 {
 616     return spapr->irq->claim(spapr, irq, lsi, errp);
 617 }
 618
 619 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
 620 {
 621     spapr->irq->free(spapr, irq, num);
 622 }
 623
 624 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
 625 {
 626     return spapr->irq->qirq(spapr, irq);
 627 }
 628
 629 int spapr_irq_post_load(sPAPRMachineState *spapr, int version_id)
 630 {
 631     return spapr->irq->post_load(spapr, version_id);
 632 }
 633
 634 void spapr_irq_reset(sPAPRMachineState *spapr, Error **errp)
 635 {
 636     if (spapr->irq->reset) {
 637         spapr->irq->reset(spapr, errp);
 638     }
 639 }
 640
 641 /*
 642  * XICS legacy routines - to deprecate one day
 643  */
 644
 645 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
 646 {
 647     int first, i;
 648
 649     for (first = 0; first < ics->nr_irqs; first += alignnum) {
 650         if (num > (ics->nr_irqs - first)) {
 651             return -1;
 652         }
 653         for (i = first; i < first + num; ++i) {
 654             if (!ICS_IRQ_FREE(ics, i)) {
 655                 break;
 656             }
 657         }
 658         if (i == (first + num)) {
 659             return first;
 660         }
 661     }
 662
 663     return -1;
 664 }
 665
 666 int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
 667 {
 668     ICSState *ics = spapr->ics;
 669     int first = -1;
 670
 671     assert(ics);
 672
 673     /*
 674      * MSIMesage::data is used for storing VIRQ so
 675      * it has to be aligned to num to support multiple
 676      * MSI vectors. MSI-X is not affected by this.
 677      * The hint is used for the first IRQ, the rest should
 678      * be allocated continuously.
 679      */
 680     if (align) {
 681         assert((num == 1) || (num == 2) || (num == 4) ||
 682                (num == 8) || (num == 16) || (num == 32));
 683         first = ics_find_free_block(ics, num, num);
 684     } else {
 685         first = ics_find_free_block(ics, num, 1);
 686     }
 687
 688     if (first < 0) {
 689         error_setg(errp, "can't find a free %d-IRQ block", num);
 690         return -1;
 691     }
 692
 693     return first + ics->offset;
 694 }
 695
 696 #define SPAPR_IRQ_XICS_LEGACY_NR_IRQS     0x400
 697
 698 sPAPRIrq spapr_irq_xics_legacy = {
 699     .nr_irqs     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
 700     .nr_msis     = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
 701     .ov5         = SPAPR_OV5_XIVE_LEGACY,
 702
 703     .init        = spapr_irq_init_xics,
 704     .claim       = spapr_irq_claim_xics,
 705     .free        = spapr_irq_free_xics,
 706     .qirq        = spapr_qirq_xics,
 707     .print_info  = spapr_irq_print_info_xics,
 708     .dt_populate = spapr_dt_xics,
 709     .cpu_intc_create = spapr_irq_cpu_intc_create_xics,
 710     .post_load   = spapr_irq_post_load_xics,
 711     .set_irq     = spapr_irq_set_irq_xics,
 712 };