4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "hw/qdev-properties.h"
29 #include "migration/vmstate.h"
35 /* These key value are as per MBV field in PVR0 */
69 static void mb_cpu_set_pc(CPUState
*cs
, vaddr value
)
71 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
73 cpu
->env
.sregs
[SR_PC
] = value
;
76 static bool mb_cpu_has_work(CPUState
*cs
)
78 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_NMI
);
81 #ifndef CONFIG_USER_ONLY
82 static void microblaze_cpu_set_irq(void *opaque
, int irq
, int level
)
84 MicroBlazeCPU
*cpu
= opaque
;
85 CPUState
*cs
= CPU(cpu
);
86 int type
= irq
? CPU_INTERRUPT_NMI
: CPU_INTERRUPT_HARD
;
89 cpu_interrupt(cs
, type
);
91 cpu_reset_interrupt(cs
, type
);
96 /* CPUClass::reset() */
97 static void mb_cpu_reset(CPUState
*s
)
99 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(s
);
100 MicroBlazeCPUClass
*mcc
= MICROBLAZE_CPU_GET_CLASS(cpu
);
101 CPUMBState
*env
= &cpu
->env
;
103 mcc
->parent_reset(s
);
105 memset(env
, 0, offsetof(CPUMBState
, pvr
));
106 env
->res_addr
= RES_ADDR_NONE
;
109 /* Disable stack protector. */
112 env
->sregs
[SR_PC
] = cpu
->cfg
.base_vectors
;
114 #if defined(CONFIG_USER_ONLY)
115 /* start in user mode with interrupts enabled. */
116 env
->sregs
[SR_MSR
] = MSR_EE
| MSR_IE
| MSR_VM
| MSR_UM
;
118 env
->sregs
[SR_MSR
] = 0;
121 env
->mmu
.c_mmu_tlb_access
= 3;
122 env
->mmu
.c_mmu_zones
= 16;
126 static void mb_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
128 info
->mach
= bfd_arch_microblaze
;
129 info
->print_insn
= print_insn_microblaze
;
132 static void mb_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
134 CPUState
*cs
= CPU(dev
);
135 MicroBlazeCPUClass
*mcc
= MICROBLAZE_CPU_GET_CLASS(dev
);
136 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
137 CPUMBState
*env
= &cpu
->env
;
138 uint8_t version_code
= 0;
143 env
->pvr
.regs
[0] = PVR0_USE_BARREL_MASK \
144 | PVR0_USE_DIV_MASK \
145 | PVR0_USE_HW_MUL_MASK \
146 | PVR0_USE_EXC_MASK \
147 | PVR0_USE_ICACHE_MASK \
148 | PVR0_USE_DCACHE_MASK \
150 env
->pvr
.regs
[2] = PVR2_D_OPB_MASK \
154 | PVR2_USE_MSR_INSTR \
155 | PVR2_USE_PCMP_INSTR \
156 | PVR2_USE_BARREL_MASK \
157 | PVR2_USE_DIV_MASK \
158 | PVR2_USE_HW_MUL_MASK \
159 | PVR2_USE_MUL64_MASK \
160 | PVR2_FPU_EXC_MASK \
163 for (i
= 0; mb_cpu_lookup
[i
].name
&& cpu
->cfg
.version
; i
++) {
164 if (strcmp(mb_cpu_lookup
[i
].name
, cpu
->cfg
.version
) == 0) {
165 version_code
= mb_cpu_lookup
[i
].version_id
;
171 qemu_log("Invalid MicroBlaze version number: %s\n", cpu
->cfg
.version
);
174 env
->pvr
.regs
[0] |= (cpu
->cfg
.stackprot
? PVR0_SPROT_MASK
: 0) |
175 (cpu
->cfg
.use_fpu
? PVR0_USE_FPU_MASK
: 0) |
176 (cpu
->cfg
.use_mmu
? PVR0_USE_MMU_MASK
: 0) |
177 (cpu
->cfg
.endi
? PVR0_ENDI_MASK
: 0) |
178 (version_code
<< 16) |
179 (cpu
->cfg
.pvr
== C_PVR_FULL
? PVR0_PVR_FULL_MASK
: 0);
181 env
->pvr
.regs
[2] |= (cpu
->cfg
.use_fpu
? PVR2_USE_FPU_MASK
: 0) |
182 (cpu
->cfg
.use_fpu
> 1 ? PVR2_USE_FPU2_MASK
: 0);
184 env
->pvr
.regs
[5] |= cpu
->cfg
.dcache_writeback
?
185 PVR5_DCACHE_WRITEBACK_MASK
: 0;
187 env
->pvr
.regs
[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
188 env
->pvr
.regs
[11] = PVR11_USE_MMU
| (16 << 17);
190 mcc
->parent_realize(dev
, errp
);
193 static void mb_cpu_initfn(Object
*obj
)
195 CPUState
*cs
= CPU(obj
);
196 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(obj
);
197 CPUMBState
*env
= &cpu
->env
;
198 static bool tcg_initialized
;
201 cpu_exec_init(cs
, &error_abort
);
203 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
);
205 #ifndef CONFIG_USER_ONLY
206 /* Inbound IRQ and FIR lines */
207 qdev_init_gpio_in(DEVICE(cpu
), microblaze_cpu_set_irq
, 2);
210 if (tcg_enabled() && !tcg_initialized
) {
211 tcg_initialized
= true;
216 static const VMStateDescription vmstate_mb_cpu
= {
221 static Property mb_properties
[] = {
222 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU
, cfg
.base_vectors
, 0),
223 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU
, cfg
.stackprot
,
225 /* If use-fpu > 0 - FPU is enabled
226 * If use-fpu = 2 - Floating point conversion and square root instructions
229 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU
, cfg
.use_fpu
, 2),
230 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU
, cfg
.use_mmu
, true),
231 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU
, cfg
.dcache_writeback
,
233 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU
, cfg
.endi
, false),
234 DEFINE_PROP_STRING("version", MicroBlazeCPU
, cfg
.version
),
235 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU
, cfg
.pvr
, C_PVR_FULL
),
236 DEFINE_PROP_END_OF_LIST(),
239 static void mb_cpu_class_init(ObjectClass
*oc
, void *data
)
241 DeviceClass
*dc
= DEVICE_CLASS(oc
);
242 CPUClass
*cc
= CPU_CLASS(oc
);
243 MicroBlazeCPUClass
*mcc
= MICROBLAZE_CPU_CLASS(oc
);
245 mcc
->parent_realize
= dc
->realize
;
246 dc
->realize
= mb_cpu_realizefn
;
248 mcc
->parent_reset
= cc
->reset
;
249 cc
->reset
= mb_cpu_reset
;
251 cc
->has_work
= mb_cpu_has_work
;
252 cc
->do_interrupt
= mb_cpu_do_interrupt
;
253 cc
->cpu_exec_interrupt
= mb_cpu_exec_interrupt
;
254 cc
->dump_state
= mb_cpu_dump_state
;
255 cc
->set_pc
= mb_cpu_set_pc
;
256 cc
->gdb_read_register
= mb_cpu_gdb_read_register
;
257 cc
->gdb_write_register
= mb_cpu_gdb_write_register
;
258 #ifdef CONFIG_USER_ONLY
259 cc
->handle_mmu_fault
= mb_cpu_handle_mmu_fault
;
261 cc
->do_unassigned_access
= mb_cpu_unassigned_access
;
262 cc
->get_phys_page_debug
= mb_cpu_get_phys_page_debug
;
264 dc
->vmsd
= &vmstate_mb_cpu
;
265 dc
->props
= mb_properties
;
266 cc
->gdb_num_core_regs
= 32 + 5;
268 cc
->disas_set_info
= mb_disas_set_info
;
271 * Reason: mb_cpu_initfn() calls cpu_exec_init(), which saves the
272 * object in cpus -> dangling pointer after final object_unref().
274 dc
->cannot_destroy_with_object_finalize_yet
= true;
277 static const TypeInfo mb_cpu_type_info
= {
278 .name
= TYPE_MICROBLAZE_CPU
,
280 .instance_size
= sizeof(MicroBlazeCPU
),
281 .instance_init
= mb_cpu_initfn
,
282 .class_size
= sizeof(MicroBlazeCPUClass
),
283 .class_init
= mb_cpu_class_init
,
286 static void mb_cpu_register_types(void)
288 type_register_static(&mb_cpu_type_info
);
291 type_init(mb_cpu_register_types
)