hw/vfio/platform: change interrupt/unmask fields into pointer
[qemu/ar7.git] / target-sh4 / helper.c
blobeaececd89494311fb01b9e84e4e20350fdbbad02
1 /*
2 * SH4 emulation
4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
25 #include "cpu.h"
27 #if !defined(CONFIG_USER_ONLY)
28 #include "hw/sh4/sh_intc.h"
29 #endif
31 #if defined(CONFIG_USER_ONLY)
33 void superh_cpu_do_interrupt(CPUState *cs)
35 cs->exception_index = -1;
38 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
39 int mmu_idx)
41 SuperHCPU *cpu = SUPERH_CPU(cs);
42 CPUSH4State *env = &cpu->env;
44 env->tea = address;
45 cs->exception_index = -1;
46 switch (rw) {
47 case 0:
48 cs->exception_index = 0x0a0;
49 break;
50 case 1:
51 cs->exception_index = 0x0c0;
52 break;
53 case 2:
54 cs->exception_index = 0x0a0;
55 break;
57 return 1;
60 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
62 /* For user mode, only U0 area is cacheable. */
63 return !(addr & 0x80000000);
66 #else /* !CONFIG_USER_ONLY */
68 #define MMU_OK 0
69 #define MMU_ITLB_MISS (-1)
70 #define MMU_ITLB_MULTIPLE (-2)
71 #define MMU_ITLB_VIOLATION (-3)
72 #define MMU_DTLB_MISS_READ (-4)
73 #define MMU_DTLB_MISS_WRITE (-5)
74 #define MMU_DTLB_INITIAL_WRITE (-6)
75 #define MMU_DTLB_VIOLATION_READ (-7)
76 #define MMU_DTLB_VIOLATION_WRITE (-8)
77 #define MMU_DTLB_MULTIPLE (-9)
78 #define MMU_DTLB_MISS (-10)
79 #define MMU_IADDR_ERROR (-11)
80 #define MMU_DADDR_ERROR_READ (-12)
81 #define MMU_DADDR_ERROR_WRITE (-13)
83 void superh_cpu_do_interrupt(CPUState *cs)
85 SuperHCPU *cpu = SUPERH_CPU(cs);
86 CPUSH4State *env = &cpu->env;
87 int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
88 int do_exp, irq_vector = cs->exception_index;
90 /* prioritize exceptions over interrupts */
92 do_exp = cs->exception_index != -1;
93 do_irq = do_irq && (cs->exception_index == -1);
95 if (env->sr & (1u << SR_BL)) {
96 if (do_exp && cs->exception_index != 0x1e0) {
97 cs->exception_index = 0x000; /* masked exception -> reset */
99 if (do_irq && !env->in_sleep) {
100 return; /* masked */
103 env->in_sleep = 0;
105 if (do_irq) {
106 irq_vector = sh_intc_get_pending_vector(env->intc_handle,
107 (env->sr >> 4) & 0xf);
108 if (irq_vector == -1) {
109 return; /* masked */
113 if (qemu_loglevel_mask(CPU_LOG_INT)) {
114 const char *expname;
115 switch (cs->exception_index) {
116 case 0x0e0:
117 expname = "addr_error";
118 break;
119 case 0x040:
120 expname = "tlb_miss";
121 break;
122 case 0x0a0:
123 expname = "tlb_violation";
124 break;
125 case 0x180:
126 expname = "illegal_instruction";
127 break;
128 case 0x1a0:
129 expname = "slot_illegal_instruction";
130 break;
131 case 0x800:
132 expname = "fpu_disable";
133 break;
134 case 0x820:
135 expname = "slot_fpu";
136 break;
137 case 0x100:
138 expname = "data_write";
139 break;
140 case 0x060:
141 expname = "dtlb_miss_write";
142 break;
143 case 0x0c0:
144 expname = "dtlb_violation_write";
145 break;
146 case 0x120:
147 expname = "fpu_exception";
148 break;
149 case 0x080:
150 expname = "initial_page_write";
151 break;
152 case 0x160:
153 expname = "trapa";
154 break;
155 default:
156 expname = do_irq ? "interrupt" : "???";
157 break;
159 qemu_log("exception 0x%03x [%s] raised\n",
160 irq_vector, expname);
161 log_cpu_state(cs, 0);
164 env->ssr = cpu_read_sr(env);
165 env->spc = env->pc;
166 env->sgr = env->gregs[15];
167 env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
169 if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
170 /* Branch instruction should be executed again before delay slot. */
171 env->spc -= 2;
172 /* Clear flags for exception/interrupt routine. */
173 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
175 if (env->flags & DELAY_SLOT_CLEARME)
176 env->flags = 0;
178 if (do_exp) {
179 env->expevt = cs->exception_index;
180 switch (cs->exception_index) {
181 case 0x000:
182 case 0x020:
183 case 0x140:
184 env->sr &= ~(1u << SR_FD);
185 env->sr |= 0xf << 4; /* IMASK */
186 env->pc = 0xa0000000;
187 break;
188 case 0x040:
189 case 0x060:
190 env->pc = env->vbr + 0x400;
191 break;
192 case 0x160:
193 env->spc += 2; /* special case for TRAPA */
194 /* fall through */
195 default:
196 env->pc = env->vbr + 0x100;
197 break;
199 return;
202 if (do_irq) {
203 env->intevt = irq_vector;
204 env->pc = env->vbr + 0x600;
205 return;
209 static void update_itlb_use(CPUSH4State * env, int itlbnb)
211 uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
213 switch (itlbnb) {
214 case 0:
215 and_mask = 0x1f;
216 break;
217 case 1:
218 and_mask = 0xe7;
219 or_mask = 0x80;
220 break;
221 case 2:
222 and_mask = 0xfb;
223 or_mask = 0x50;
224 break;
225 case 3:
226 or_mask = 0x2c;
227 break;
230 env->mmucr &= (and_mask << 24) | 0x00ffffff;
231 env->mmucr |= (or_mask << 24);
234 static int itlb_replacement(CPUSH4State * env)
236 SuperHCPU *cpu = sh_env_get_cpu(env);
238 if ((env->mmucr & 0xe0000000) == 0xe0000000) {
239 return 0;
241 if ((env->mmucr & 0x98000000) == 0x18000000) {
242 return 1;
244 if ((env->mmucr & 0x54000000) == 0x04000000) {
245 return 2;
247 if ((env->mmucr & 0x2c000000) == 0x00000000) {
248 return 3;
250 cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
253 /* Find the corresponding entry in the right TLB
254 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
256 static int find_tlb_entry(CPUSH4State * env, target_ulong address,
257 tlb_t * entries, uint8_t nbtlb, int use_asid)
259 int match = MMU_DTLB_MISS;
260 uint32_t start, end;
261 uint8_t asid;
262 int i;
264 asid = env->pteh & 0xff;
266 for (i = 0; i < nbtlb; i++) {
267 if (!entries[i].v)
268 continue; /* Invalid entry */
269 if (!entries[i].sh && use_asid && entries[i].asid != asid)
270 continue; /* Bad ASID */
271 start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
272 end = start + entries[i].size - 1;
273 if (address >= start && address <= end) { /* Match */
274 if (match != MMU_DTLB_MISS)
275 return MMU_DTLB_MULTIPLE; /* Multiple match */
276 match = i;
279 return match;
282 static void increment_urc(CPUSH4State * env)
284 uint8_t urb, urc;
286 /* Increment URC */
287 urb = ((env->mmucr) >> 18) & 0x3f;
288 urc = ((env->mmucr) >> 10) & 0x3f;
289 urc++;
290 if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
291 urc = 0;
292 env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
295 /* Copy and utlb entry into itlb
296 Return entry
298 static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
300 int itlb;
302 tlb_t * ientry;
303 itlb = itlb_replacement(env);
304 ientry = &env->itlb[itlb];
305 if (ientry->v) {
306 tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
308 *ientry = env->utlb[utlb];
309 update_itlb_use(env, itlb);
310 return itlb;
313 /* Find itlb entry
314 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
316 static int find_itlb_entry(CPUSH4State * env, target_ulong address,
317 int use_asid)
319 int e;
321 e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
322 if (e == MMU_DTLB_MULTIPLE) {
323 e = MMU_ITLB_MULTIPLE;
324 } else if (e == MMU_DTLB_MISS) {
325 e = MMU_ITLB_MISS;
326 } else if (e >= 0) {
327 update_itlb_use(env, e);
329 return e;
332 /* Find utlb entry
333 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
334 static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
336 /* per utlb access */
337 increment_urc(env);
339 /* Return entry */
340 return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
343 /* Match address against MMU
344 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
345 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
346 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
347 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
348 MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
350 static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
351 int *prot, target_ulong address,
352 int rw, int access_type)
354 int use_asid, n;
355 tlb_t *matching = NULL;
357 use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
359 if (rw == 2) {
360 n = find_itlb_entry(env, address, use_asid);
361 if (n >= 0) {
362 matching = &env->itlb[n];
363 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
364 n = MMU_ITLB_VIOLATION;
365 } else {
366 *prot = PAGE_EXEC;
368 } else {
369 n = find_utlb_entry(env, address, use_asid);
370 if (n >= 0) {
371 n = copy_utlb_entry_itlb(env, n);
372 matching = &env->itlb[n];
373 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
374 n = MMU_ITLB_VIOLATION;
375 } else {
376 *prot = PAGE_READ | PAGE_EXEC;
377 if ((matching->pr & 1) && matching->d) {
378 *prot |= PAGE_WRITE;
381 } else if (n == MMU_DTLB_MULTIPLE) {
382 n = MMU_ITLB_MULTIPLE;
383 } else if (n == MMU_DTLB_MISS) {
384 n = MMU_ITLB_MISS;
387 } else {
388 n = find_utlb_entry(env, address, use_asid);
389 if (n >= 0) {
390 matching = &env->utlb[n];
391 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
392 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
393 MMU_DTLB_VIOLATION_READ;
394 } else if ((rw == 1) && !(matching->pr & 1)) {
395 n = MMU_DTLB_VIOLATION_WRITE;
396 } else if ((rw == 1) && !matching->d) {
397 n = MMU_DTLB_INITIAL_WRITE;
398 } else {
399 *prot = PAGE_READ;
400 if ((matching->pr & 1) && matching->d) {
401 *prot |= PAGE_WRITE;
404 } else if (n == MMU_DTLB_MISS) {
405 n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
406 MMU_DTLB_MISS_READ;
409 if (n >= 0) {
410 n = MMU_OK;
411 *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
412 (address & (matching->size - 1));
414 return n;
417 static int get_physical_address(CPUSH4State * env, target_ulong * physical,
418 int *prot, target_ulong address,
419 int rw, int access_type)
421 /* P1, P2 and P4 areas do not use translation */
422 if ((address >= 0x80000000 && address < 0xc0000000) ||
423 address >= 0xe0000000) {
424 if (!(env->sr & (1u << SR_MD))
425 && (address < 0xe0000000 || address >= 0xe4000000)) {
426 /* Unauthorized access in user mode (only store queues are available) */
427 fprintf(stderr, "Unauthorized access\n");
428 if (rw == 0)
429 return MMU_DADDR_ERROR_READ;
430 else if (rw == 1)
431 return MMU_DADDR_ERROR_WRITE;
432 else
433 return MMU_IADDR_ERROR;
435 if (address >= 0x80000000 && address < 0xc0000000) {
436 /* Mask upper 3 bits for P1 and P2 areas */
437 *physical = address & 0x1fffffff;
438 } else {
439 *physical = address;
441 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
442 return MMU_OK;
445 /* If MMU is disabled, return the corresponding physical page */
446 if (!(env->mmucr & MMUCR_AT)) {
447 *physical = address & 0x1FFFFFFF;
448 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
449 return MMU_OK;
452 /* We need to resort to the MMU */
453 return get_mmu_address(env, physical, prot, address, rw, access_type);
456 int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
457 int mmu_idx)
459 SuperHCPU *cpu = SUPERH_CPU(cs);
460 CPUSH4State *env = &cpu->env;
461 target_ulong physical;
462 int prot, ret, access_type;
464 access_type = ACCESS_INT;
465 ret =
466 get_physical_address(env, &physical, &prot, address, rw,
467 access_type);
469 if (ret != MMU_OK) {
470 env->tea = address;
471 if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
472 env->pteh = (env->pteh & PTEH_ASID_MASK) |
473 (address & PTEH_VPN_MASK);
475 switch (ret) {
476 case MMU_ITLB_MISS:
477 case MMU_DTLB_MISS_READ:
478 cs->exception_index = 0x040;
479 break;
480 case MMU_DTLB_MULTIPLE:
481 case MMU_ITLB_MULTIPLE:
482 cs->exception_index = 0x140;
483 break;
484 case MMU_ITLB_VIOLATION:
485 cs->exception_index = 0x0a0;
486 break;
487 case MMU_DTLB_MISS_WRITE:
488 cs->exception_index = 0x060;
489 break;
490 case MMU_DTLB_INITIAL_WRITE:
491 cs->exception_index = 0x080;
492 break;
493 case MMU_DTLB_VIOLATION_READ:
494 cs->exception_index = 0x0a0;
495 break;
496 case MMU_DTLB_VIOLATION_WRITE:
497 cs->exception_index = 0x0c0;
498 break;
499 case MMU_IADDR_ERROR:
500 case MMU_DADDR_ERROR_READ:
501 cs->exception_index = 0x0e0;
502 break;
503 case MMU_DADDR_ERROR_WRITE:
504 cs->exception_index = 0x100;
505 break;
506 default:
507 cpu_abort(cs, "Unhandled MMU fault");
509 return 1;
512 address &= TARGET_PAGE_MASK;
513 physical &= TARGET_PAGE_MASK;
515 tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
516 return 0;
519 hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
521 SuperHCPU *cpu = SUPERH_CPU(cs);
522 target_ulong physical;
523 int prot;
525 get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0);
526 return physical;
529 void cpu_load_tlb(CPUSH4State * env)
531 SuperHCPU *cpu = sh_env_get_cpu(env);
532 int n = cpu_mmucr_urc(env->mmucr);
533 tlb_t * entry = &env->utlb[n];
535 if (entry->v) {
536 /* Overwriting valid entry in utlb. */
537 target_ulong address = entry->vpn << 10;
538 tlb_flush_page(CPU(cpu), address);
541 /* Take values into cpu status from registers. */
542 entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
543 entry->vpn = cpu_pteh_vpn(env->pteh);
544 entry->v = (uint8_t)cpu_ptel_v(env->ptel);
545 entry->ppn = cpu_ptel_ppn(env->ptel);
546 entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
547 switch (entry->sz) {
548 case 0: /* 00 */
549 entry->size = 1024; /* 1K */
550 break;
551 case 1: /* 01 */
552 entry->size = 1024 * 4; /* 4K */
553 break;
554 case 2: /* 10 */
555 entry->size = 1024 * 64; /* 64K */
556 break;
557 case 3: /* 11 */
558 entry->size = 1024 * 1024; /* 1M */
559 break;
560 default:
561 cpu_abort(CPU(cpu), "Unhandled load_tlb");
562 break;
564 entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
565 entry->c = (uint8_t)cpu_ptel_c(env->ptel);
566 entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
567 entry->d = (uint8_t)cpu_ptel_d(env->ptel);
568 entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
569 entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
570 entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
573 void cpu_sh4_invalidate_tlb(CPUSH4State *s)
575 int i;
577 /* UTLB */
578 for (i = 0; i < UTLB_SIZE; i++) {
579 tlb_t * entry = &s->utlb[i];
580 entry->v = 0;
582 /* ITLB */
583 for (i = 0; i < ITLB_SIZE; i++) {
584 tlb_t * entry = &s->itlb[i];
585 entry->v = 0;
588 tlb_flush(CPU(sh_env_get_cpu(s)), 1);
591 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
592 hwaddr addr)
594 int index = (addr & 0x00000300) >> 8;
595 tlb_t * entry = &s->itlb[index];
597 return (entry->vpn << 10) |
598 (entry->v << 8) |
599 (entry->asid);
602 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
603 uint32_t mem_value)
605 uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
606 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
607 uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
609 int index = (addr & 0x00000300) >> 8;
610 tlb_t * entry = &s->itlb[index];
611 if (entry->v) {
612 /* Overwriting valid entry in itlb. */
613 target_ulong address = entry->vpn << 10;
614 tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
616 entry->asid = asid;
617 entry->vpn = vpn;
618 entry->v = v;
621 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
622 hwaddr addr)
624 int array = (addr & 0x00800000) >> 23;
625 int index = (addr & 0x00000300) >> 8;
626 tlb_t * entry = &s->itlb[index];
628 if (array == 0) {
629 /* ITLB Data Array 1 */
630 return (entry->ppn << 10) |
631 (entry->v << 8) |
632 (entry->pr << 5) |
633 ((entry->sz & 1) << 6) |
634 ((entry->sz & 2) << 4) |
635 (entry->c << 3) |
636 (entry->sh << 1);
637 } else {
638 /* ITLB Data Array 2 */
639 return (entry->tc << 1) |
640 (entry->sa);
644 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
645 uint32_t mem_value)
647 int array = (addr & 0x00800000) >> 23;
648 int index = (addr & 0x00000300) >> 8;
649 tlb_t * entry = &s->itlb[index];
651 if (array == 0) {
652 /* ITLB Data Array 1 */
653 if (entry->v) {
654 /* Overwriting valid entry in utlb. */
655 target_ulong address = entry->vpn << 10;
656 tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
658 entry->ppn = (mem_value & 0x1ffffc00) >> 10;
659 entry->v = (mem_value & 0x00000100) >> 8;
660 entry->sz = (mem_value & 0x00000080) >> 6 |
661 (mem_value & 0x00000010) >> 4;
662 entry->pr = (mem_value & 0x00000040) >> 5;
663 entry->c = (mem_value & 0x00000008) >> 3;
664 entry->sh = (mem_value & 0x00000002) >> 1;
665 } else {
666 /* ITLB Data Array 2 */
667 entry->tc = (mem_value & 0x00000008) >> 3;
668 entry->sa = (mem_value & 0x00000007);
672 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
673 hwaddr addr)
675 int index = (addr & 0x00003f00) >> 8;
676 tlb_t * entry = &s->utlb[index];
678 increment_urc(s); /* per utlb access */
680 return (entry->vpn << 10) |
681 (entry->v << 8) |
682 (entry->asid);
685 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
686 uint32_t mem_value)
688 int associate = addr & 0x0000080;
689 uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
690 uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
691 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
692 uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
693 int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD));
695 if (associate) {
696 int i;
697 tlb_t * utlb_match_entry = NULL;
698 int needs_tlb_flush = 0;
700 /* search UTLB */
701 for (i = 0; i < UTLB_SIZE; i++) {
702 tlb_t * entry = &s->utlb[i];
703 if (!entry->v)
704 continue;
706 if (entry->vpn == vpn
707 && (!use_asid || entry->asid == asid || entry->sh)) {
708 if (utlb_match_entry) {
709 CPUState *cs = CPU(sh_env_get_cpu(s));
711 /* Multiple TLB Exception */
712 cs->exception_index = 0x140;
713 s->tea = addr;
714 break;
716 if (entry->v && !v)
717 needs_tlb_flush = 1;
718 entry->v = v;
719 entry->d = d;
720 utlb_match_entry = entry;
722 increment_urc(s); /* per utlb access */
725 /* search ITLB */
726 for (i = 0; i < ITLB_SIZE; i++) {
727 tlb_t * entry = &s->itlb[i];
728 if (entry->vpn == vpn
729 && (!use_asid || entry->asid == asid || entry->sh)) {
730 if (entry->v && !v)
731 needs_tlb_flush = 1;
732 if (utlb_match_entry)
733 *entry = *utlb_match_entry;
734 else
735 entry->v = v;
736 break;
740 if (needs_tlb_flush) {
741 tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
744 } else {
745 int index = (addr & 0x00003f00) >> 8;
746 tlb_t * entry = &s->utlb[index];
747 if (entry->v) {
748 CPUState *cs = CPU(sh_env_get_cpu(s));
750 /* Overwriting valid entry in utlb. */
751 target_ulong address = entry->vpn << 10;
752 tlb_flush_page(cs, address);
754 entry->asid = asid;
755 entry->vpn = vpn;
756 entry->d = d;
757 entry->v = v;
758 increment_urc(s);
762 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
763 hwaddr addr)
765 int array = (addr & 0x00800000) >> 23;
766 int index = (addr & 0x00003f00) >> 8;
767 tlb_t * entry = &s->utlb[index];
769 increment_urc(s); /* per utlb access */
771 if (array == 0) {
772 /* ITLB Data Array 1 */
773 return (entry->ppn << 10) |
774 (entry->v << 8) |
775 (entry->pr << 5) |
776 ((entry->sz & 1) << 6) |
777 ((entry->sz & 2) << 4) |
778 (entry->c << 3) |
779 (entry->d << 2) |
780 (entry->sh << 1) |
781 (entry->wt);
782 } else {
783 /* ITLB Data Array 2 */
784 return (entry->tc << 1) |
785 (entry->sa);
789 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
790 uint32_t mem_value)
792 int array = (addr & 0x00800000) >> 23;
793 int index = (addr & 0x00003f00) >> 8;
794 tlb_t * entry = &s->utlb[index];
796 increment_urc(s); /* per utlb access */
798 if (array == 0) {
799 /* UTLB Data Array 1 */
800 if (entry->v) {
801 /* Overwriting valid entry in utlb. */
802 target_ulong address = entry->vpn << 10;
803 tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
805 entry->ppn = (mem_value & 0x1ffffc00) >> 10;
806 entry->v = (mem_value & 0x00000100) >> 8;
807 entry->sz = (mem_value & 0x00000080) >> 6 |
808 (mem_value & 0x00000010) >> 4;
809 entry->pr = (mem_value & 0x00000060) >> 5;
810 entry->c = (mem_value & 0x00000008) >> 3;
811 entry->d = (mem_value & 0x00000004) >> 2;
812 entry->sh = (mem_value & 0x00000002) >> 1;
813 entry->wt = (mem_value & 0x00000001);
814 } else {
815 /* UTLB Data Array 2 */
816 entry->tc = (mem_value & 0x00000008) >> 3;
817 entry->sa = (mem_value & 0x00000007);
821 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
823 int n;
824 int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
826 /* check area */
827 if (env->sr & (1u << SR_MD)) {
828 /* For privileged mode, P2 and P4 area is not cacheable. */
829 if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
830 return 0;
831 } else {
832 /* For user mode, only U0 area is cacheable. */
833 if (0x80000000 <= addr)
834 return 0;
838 * TODO : Evaluate CCR and check if the cache is on or off.
839 * Now CCR is not in CPUSH4State, but in SH7750State.
840 * When you move the ccr into CPUSH4State, the code will be
841 * as follows.
843 #if 0
844 /* check if operand cache is enabled or not. */
845 if (!(env->ccr & 1))
846 return 0;
847 #endif
849 /* if MMU is off, no check for TLB. */
850 if (env->mmucr & MMUCR_AT)
851 return 1;
853 /* check TLB */
854 n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
855 if (n >= 0)
856 return env->itlb[n].c;
858 n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
859 if (n >= 0)
860 return env->utlb[n].c;
862 return 0;
865 #endif
867 bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
869 if (interrupt_request & CPU_INTERRUPT_HARD) {
870 superh_cpu_do_interrupt(cs);
871 return true;
873 return false;