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hw/vfio/platform: change interrupt/unmask fields into pointer
[qemu/ar7.git] / target-mips / msa_helper.c
blob5dd3da67a8408a740217b8d3222c16d20aeb9bf9
1 /*
2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2014 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22
23 /* Data format min and max values */
24 #define DF_BITS(df) (1 << ((df) + 3))
25
26 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
27 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
28
29 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
30 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
31
32 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
33 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
34
35 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
36 #define SIGNED(x, df) \
37 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
38
39 /* Element-by-element access macros */
40 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
41
42 static inline void msa_move_v(wr_t *pwd, wr_t *pws)
43 {
44 uint32_t i;
45
46 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
47 pwd->d[i] = pws->d[i];
48 }
49 }
50
51 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
52 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
53 uint32_t i8) \
54 { \
55 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
56 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
57 uint32_t i; \
58 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
59 DEST = OPERATION; \
60 } \
61 }
62
63 MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
64 MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
65 MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
66 MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
67
68 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
69 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
70 MSA_FN_IMM8(bmnzi_b, pwd->b[i],
71 BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
72
73 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
74 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
75 MSA_FN_IMM8(bmzi_b, pwd->b[i],
76 BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
77
78 #define BIT_SELECT(dest, arg1, arg2, df) \
79 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
80 MSA_FN_IMM8(bseli_b, pwd->b[i],
81 BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
82
83 #undef MSA_FN_IMM8
84
85 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
86
87 void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
88 uint32_t ws, uint32_t imm)
89 {
90 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
91 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
92 wr_t wx, *pwx = &wx;
93 uint32_t i;
94
95 switch (df) {
96 case DF_BYTE:
97 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
98 pwx->b[i] = pws->b[SHF_POS(i, imm)];
99 }
100 break;
101 case DF_HALF:
102 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
103 pwx->h[i] = pws->h[SHF_POS(i, imm)];
104 }
105 break;
106 case DF_WORD:
107 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
108 pwx->w[i] = pws->w[SHF_POS(i, imm)];
109 }
110 break;
111 default:
112 assert(0);
113 }
114 msa_move_v(pwd, pwx);
115 }
116
117 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
118 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
119 uint32_t wt) \
120 { \
121 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
122 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
123 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
124 uint32_t i; \
125 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
126 DEST = OPERATION; \
127 } \
128 }
129
130 MSA_FN_VECTOR(and_v, pwd->d[i], pws->d[i] & pwt->d[i])
131 MSA_FN_VECTOR(or_v, pwd->d[i], pws->d[i] | pwt->d[i])
132 MSA_FN_VECTOR(nor_v, pwd->d[i], ~(pws->d[i] | pwt->d[i]))
133 MSA_FN_VECTOR(xor_v, pwd->d[i], pws->d[i] ^ pwt->d[i])
134 MSA_FN_VECTOR(bmnz_v, pwd->d[i],
135 BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
136 MSA_FN_VECTOR(bmz_v, pwd->d[i],
137 BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
138 MSA_FN_VECTOR(bsel_v, pwd->d[i],
139 BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
140 #undef BIT_MOVE_IF_NOT_ZERO
141 #undef BIT_MOVE_IF_ZERO
142 #undef BIT_SELECT
143 #undef MSA_FN_VECTOR
144
145 static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
146 {
147 return arg1 + arg2;
148 }
149
150 static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
151 {
152 return arg1 - arg2;
153 }
154
155 static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
156 {
157 return arg1 == arg2 ? -1 : 0;
158 }
159
160 static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
161 {
162 return arg1 <= arg2 ? -1 : 0;
163 }
164
165 static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
166 {
167 uint64_t u_arg1 = UNSIGNED(arg1, df);
168 uint64_t u_arg2 = UNSIGNED(arg2, df);
169 return u_arg1 <= u_arg2 ? -1 : 0;
170 }
171
172 static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
173 {
174 return arg1 < arg2 ? -1 : 0;
175 }
176
177 static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
178 {
179 uint64_t u_arg1 = UNSIGNED(arg1, df);
180 uint64_t u_arg2 = UNSIGNED(arg2, df);
181 return u_arg1 < u_arg2 ? -1 : 0;
182 }
183
184 static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
185 {
186 return arg1 > arg2 ? arg1 : arg2;
187 }
188
189 static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
190 {
191 uint64_t u_arg1 = UNSIGNED(arg1, df);
192 uint64_t u_arg2 = UNSIGNED(arg2, df);
193 return u_arg1 > u_arg2 ? arg1 : arg2;
194 }
195
196 static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
197 {
198 return arg1 < arg2 ? arg1 : arg2;
199 }
200
201 static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
202 {
203 uint64_t u_arg1 = UNSIGNED(arg1, df);
204 uint64_t u_arg2 = UNSIGNED(arg2, df);
205 return u_arg1 < u_arg2 ? arg1 : arg2;
206 }
207
208 #define MSA_BINOP_IMM_DF(helper, func) \
209 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
210 uint32_t wd, uint32_t ws, int32_t u5) \
211 { \
212 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
213 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
214 uint32_t i; \
215 \
216 switch (df) { \
217 case DF_BYTE: \
218 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
219 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
220 } \
221 break; \
222 case DF_HALF: \
223 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
224 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
225 } \
226 break; \
227 case DF_WORD: \
228 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
229 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
230 } \
231 break; \
232 case DF_DOUBLE: \
233 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
234 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
235 } \
236 break; \
237 default: \
238 assert(0); \
239 } \
240 }
241
242 MSA_BINOP_IMM_DF(addvi, addv)
243 MSA_BINOP_IMM_DF(subvi, subv)
244 MSA_BINOP_IMM_DF(ceqi, ceq)
245 MSA_BINOP_IMM_DF(clei_s, cle_s)
246 MSA_BINOP_IMM_DF(clei_u, cle_u)
247 MSA_BINOP_IMM_DF(clti_s, clt_s)
248 MSA_BINOP_IMM_DF(clti_u, clt_u)
249 MSA_BINOP_IMM_DF(maxi_s, max_s)
250 MSA_BINOP_IMM_DF(maxi_u, max_u)
251 MSA_BINOP_IMM_DF(mini_s, min_s)
252 MSA_BINOP_IMM_DF(mini_u, min_u)
253 #undef MSA_BINOP_IMM_DF
254
255 void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
256 int32_t s10)
257 {
258 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
259 uint32_t i;
260
261 switch (df) {
262 case DF_BYTE:
263 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
264 pwd->b[i] = (int8_t)s10;
265 }
266 break;
267 case DF_HALF:
268 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
269 pwd->h[i] = (int16_t)s10;
270 }
271 break;
272 case DF_WORD:
273 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
274 pwd->w[i] = (int32_t)s10;
275 }
276 break;
277 case DF_DOUBLE:
278 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
279 pwd->d[i] = (int64_t)s10;
280 }
281 break;
282 default:
283 assert(0);
284 }
285 }
286
287 /* Data format bit position and unsigned values */
288 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
289
290 static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
291 {
292 int32_t b_arg2 = BIT_POSITION(arg2, df);
293 return arg1 << b_arg2;
294 }
295
296 static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
297 {
298 int32_t b_arg2 = BIT_POSITION(arg2, df);
299 return arg1 >> b_arg2;
300 }
301
302 static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
303 {
304 uint64_t u_arg1 = UNSIGNED(arg1, df);
305 int32_t b_arg2 = BIT_POSITION(arg2, df);
306 return u_arg1 >> b_arg2;
307 }
308
309 static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
310 {
311 int32_t b_arg2 = BIT_POSITION(arg2, df);
312 return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
313 }
314
315 static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
316 int64_t arg2)
317 {
318 int32_t b_arg2 = BIT_POSITION(arg2, df);
319 return UNSIGNED(arg1 | (1LL << b_arg2), df);
320 }
321
322 static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
323 {
324 int32_t b_arg2 = BIT_POSITION(arg2, df);
325 return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
326 }
327
328 static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
329 int64_t arg2)
330 {
331 uint64_t u_arg1 = UNSIGNED(arg1, df);
332 uint64_t u_dest = UNSIGNED(dest, df);
333 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
334 int32_t sh_a = DF_BITS(df) - sh_d;
335 if (sh_d == DF_BITS(df)) {
336 return u_arg1;
337 } else {
338 return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
339 UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
340 }
341 }
342
343 static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
344 int64_t arg2)
345 {
346 uint64_t u_arg1 = UNSIGNED(arg1, df);
347 uint64_t u_dest = UNSIGNED(dest, df);
348 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
349 int32_t sh_a = DF_BITS(df) - sh_d;
350 if (sh_d == DF_BITS(df)) {
351 return u_arg1;
352 } else {
353 return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
354 UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
355 }
356 }
357
358 static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
359 {
360 return arg < M_MIN_INT(m+1) ? M_MIN_INT(m+1) :
361 arg > M_MAX_INT(m+1) ? M_MAX_INT(m+1) :
362 arg;
363 }
364
365 static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
366 {
367 uint64_t u_arg = UNSIGNED(arg, df);
368 return u_arg < M_MAX_UINT(m+1) ? u_arg :
369 M_MAX_UINT(m+1);
370 }
371
372 static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
373 {
374 int32_t b_arg2 = BIT_POSITION(arg2, df);
375 if (b_arg2 == 0) {
376 return arg1;
377 } else {
378 int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
379 return (arg1 >> b_arg2) + r_bit;
380 }
381 }
382
383 static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
384 {
385 uint64_t u_arg1 = UNSIGNED(arg1, df);
386 int32_t b_arg2 = BIT_POSITION(arg2, df);
387 if (b_arg2 == 0) {
388 return u_arg1;
389 } else {
390 uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
391 return (u_arg1 >> b_arg2) + r_bit;
392 }
393 }
394
395 #define MSA_BINOP_IMMU_DF(helper, func) \
396 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
397 uint32_t ws, uint32_t u5) \
398 { \
399 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
400 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
401 uint32_t i; \
402 \
403 switch (df) { \
404 case DF_BYTE: \
405 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
406 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
407 } \
408 break; \
409 case DF_HALF: \
410 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
411 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
412 } \
413 break; \
414 case DF_WORD: \
415 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
416 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
417 } \
418 break; \
419 case DF_DOUBLE: \
420 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
421 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
422 } \
423 break; \
424 default: \
425 assert(0); \
426 } \
427 }
428
429 MSA_BINOP_IMMU_DF(slli, sll)
430 MSA_BINOP_IMMU_DF(srai, sra)
431 MSA_BINOP_IMMU_DF(srli, srl)
432 MSA_BINOP_IMMU_DF(bclri, bclr)
433 MSA_BINOP_IMMU_DF(bseti, bset)
434 MSA_BINOP_IMMU_DF(bnegi, bneg)
435 MSA_BINOP_IMMU_DF(sat_s, sat_s)
436 MSA_BINOP_IMMU_DF(sat_u, sat_u)
437 MSA_BINOP_IMMU_DF(srari, srar)
438 MSA_BINOP_IMMU_DF(srlri, srlr)
439 #undef MSA_BINOP_IMMU_DF
440
441 #define MSA_TEROP_IMMU_DF(helper, func) \
442 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
443 uint32_t wd, uint32_t ws, uint32_t u5) \
444 { \
445 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
446 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
447 uint32_t i; \
448 \
449 switch (df) { \
450 case DF_BYTE: \
451 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
452 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
453 u5); \
454 } \
455 break; \
456 case DF_HALF: \
457 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
458 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
459 u5); \
460 } \
461 break; \
462 case DF_WORD: \
463 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
464 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
465 u5); \
466 } \
467 break; \
468 case DF_DOUBLE: \
469 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
470 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
471 u5); \
472 } \
473 break; \
474 default: \
475 assert(0); \
476 } \
477 }
478
479 MSA_TEROP_IMMU_DF(binsli, binsl)
480 MSA_TEROP_IMMU_DF(binsri, binsr)
481 #undef MSA_TEROP_IMMU_DF
482
483 static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
484 {
485 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
486 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
487 return abs_arg1 > abs_arg2 ? arg1 : arg2;
488 }
489
490 static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
491 {
492 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
493 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
494 return abs_arg1 < abs_arg2 ? arg1 : arg2;
495 }
496
497 static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
498 {
499 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
500 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
501 return abs_arg1 + abs_arg2;
502 }
503
504 static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
505 {
506 uint64_t max_int = (uint64_t)DF_MAX_INT(df);
507 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
508 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
509 if (abs_arg1 > max_int || abs_arg2 > max_int) {
510 return (int64_t)max_int;
511 } else {
512 return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
513 }
514 }
515
516 static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
517 {
518 int64_t max_int = DF_MAX_INT(df);
519 int64_t min_int = DF_MIN_INT(df);
520 if (arg1 < 0) {
521 return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
522 } else {
523 return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
524 }
525 }
526
527 static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
528 {
529 uint64_t max_uint = DF_MAX_UINT(df);
530 uint64_t u_arg1 = UNSIGNED(arg1, df);
531 uint64_t u_arg2 = UNSIGNED(arg2, df);
532 return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
533 }
534
535 static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2)
536 {
537 /* signed shift */
538 return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1);
539 }
540
541 static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
542 {
543 uint64_t u_arg1 = UNSIGNED(arg1, df);
544 uint64_t u_arg2 = UNSIGNED(arg2, df);
545 /* unsigned shift */
546 return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1);
547 }
548
549 static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2)
550 {
551 /* signed shift */
552 return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1);
553 }
554
555 static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
556 {
557 uint64_t u_arg1 = UNSIGNED(arg1, df);
558 uint64_t u_arg2 = UNSIGNED(arg2, df);
559 /* unsigned shift */
560 return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1);
561 }
562
563 static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
564 {
565 int64_t max_int = DF_MAX_INT(df);
566 int64_t min_int = DF_MIN_INT(df);
567 if (arg2 > 0) {
568 return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
569 } else {
570 return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
571 }
572 }
573
574 static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
575 {
576 uint64_t u_arg1 = UNSIGNED(arg1, df);
577 uint64_t u_arg2 = UNSIGNED(arg2, df);
578 return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
579 }
580
581 static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
582 {
583 uint64_t u_arg1 = UNSIGNED(arg1, df);
584 uint64_t max_uint = DF_MAX_UINT(df);
585 if (arg2 >= 0) {
586 uint64_t u_arg2 = (uint64_t)arg2;
587 return (u_arg1 > u_arg2) ?
588 (int64_t)(u_arg1 - u_arg2) :
589 0;
590 } else {
591 uint64_t u_arg2 = (uint64_t)(-arg2);
592 return (u_arg1 < max_uint - u_arg2) ?
593 (int64_t)(u_arg1 + u_arg2) :
594 (int64_t)max_uint;
595 }
596 }
597
598 static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
599 {
600 uint64_t u_arg1 = UNSIGNED(arg1, df);
601 uint64_t u_arg2 = UNSIGNED(arg2, df);
602 int64_t max_int = DF_MAX_INT(df);
603 int64_t min_int = DF_MIN_INT(df);
604 if (u_arg1 > u_arg2) {
605 return u_arg1 - u_arg2 < (uint64_t)max_int ?
606 (int64_t)(u_arg1 - u_arg2) :
607 max_int;
608 } else {
609 return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
610 (int64_t)(u_arg1 - u_arg2) :
611 min_int;
612 }
613 }
614
615 static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
616 {
617 /* signed compare */
618 return (arg1 < arg2) ?
619 (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
620 }
621
622 static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
623 {
624 uint64_t u_arg1 = UNSIGNED(arg1, df);
625 uint64_t u_arg2 = UNSIGNED(arg2, df);
626 /* unsigned compare */
627 return (u_arg1 < u_arg2) ?
628 (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
629 }
630
631 static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
632 {
633 return arg1 * arg2;
634 }
635
636 static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
637 {
638 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
639 return DF_MIN_INT(df);
640 }
641 return arg2 ? arg1 / arg2 : 0;
642 }
643
644 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
645 {
646 uint64_t u_arg1 = UNSIGNED(arg1, df);
647 uint64_t u_arg2 = UNSIGNED(arg2, df);
648 return u_arg2 ? u_arg1 / u_arg2 : 0;
649 }
650
651 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
652 {
653 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
654 return 0;
655 }
656 return arg2 ? arg1 % arg2 : 0;
657 }
658
659 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
660 {
661 uint64_t u_arg1 = UNSIGNED(arg1, df);
662 uint64_t u_arg2 = UNSIGNED(arg2, df);
663 return u_arg2 ? u_arg1 % u_arg2 : 0;
664 }
665
666 #define SIGNED_EVEN(a, df) \
667 ((((int64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
668
669 #define UNSIGNED_EVEN(a, df) \
670 ((((uint64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
671
672 #define SIGNED_ODD(a, df) \
673 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
674
675 #define UNSIGNED_ODD(a, df) \
676 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
677
678 #define SIGNED_EXTRACT(e, o, a, df) \
679 do { \
680 e = SIGNED_EVEN(a, df); \
681 o = SIGNED_ODD(a, df); \
682 } while (0);
683
684 #define UNSIGNED_EXTRACT(e, o, a, df) \
685 do { \
686 e = UNSIGNED_EVEN(a, df); \
687 o = UNSIGNED_ODD(a, df); \
688 } while (0);
689
690 static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
691 {
692 int64_t even_arg1;
693 int64_t even_arg2;
694 int64_t odd_arg1;
695 int64_t odd_arg2;
696 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
697 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
698 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
699 }
700
701 static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
702 {
703 int64_t even_arg1;
704 int64_t even_arg2;
705 int64_t odd_arg1;
706 int64_t odd_arg2;
707 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
708 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
709 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
710 }
711
712 #define CONCATENATE_AND_SLIDE(s, k) \
713 do { \
714 for (i = 0; i < s; i++) { \
715 v[i] = pws->b[s * k + i]; \
716 v[i + s] = pwd->b[s * k + i]; \
717 } \
718 for (i = 0; i < s; i++) { \
719 pwd->b[s * k + i] = v[i + n]; \
720 } \
721 } while (0)
722
723 static inline void msa_sld_df(uint32_t df, wr_t *pwd,
724 wr_t *pws, target_ulong rt)
725 {
726 uint32_t n = rt % DF_ELEMENTS(df);
727 uint8_t v[64];
728 uint32_t i, k;
729
730 switch (df) {
731 case DF_BYTE:
732 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0);
733 break;
734 case DF_HALF:
735 for (k = 0; k < 2; k++) {
736 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k);
737 }
738 break;
739 case DF_WORD:
740 for (k = 0; k < 4; k++) {
741 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k);
742 }
743 break;
744 case DF_DOUBLE:
745 for (k = 0; k < 8; k++) {
746 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k);
747 }
748 break;
749 default:
750 assert(0);
751 }
752 }
753
754 static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
755 {
756 return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
757 }
758
759 static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
760 {
761 return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
762 }
763
764 static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
765 {
766 return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
767 }
768
769 static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
770 {
771 return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
772 }
773
774 static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
775 {
776 int64_t q_min = DF_MIN_INT(df);
777 int64_t q_max = DF_MAX_INT(df);
778
779 if (arg1 == q_min && arg2 == q_min) {
780 return q_max;
781 }
782 return (arg1 * arg2) >> (DF_BITS(df) - 1);
783 }
784
785 static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
786 {
787 int64_t q_min = DF_MIN_INT(df);
788 int64_t q_max = DF_MAX_INT(df);
789 int64_t r_bit = 1 << (DF_BITS(df) - 2);
790
791 if (arg1 == q_min && arg2 == q_min) {
792 return q_max;
793 }
794 return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1);
795 }
796
797 #define MSA_BINOP_DF(func) \
798 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
799 uint32_t wd, uint32_t ws, uint32_t wt) \
800 { \
801 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
802 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
803 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
804 uint32_t i; \
805 \
806 switch (df) { \
807 case DF_BYTE: \
808 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
809 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], pwt->b[i]); \
810 } \
811 break; \
812 case DF_HALF: \
813 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
814 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], pwt->h[i]); \
815 } \
816 break; \
817 case DF_WORD: \
818 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
819 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], pwt->w[i]); \
820 } \
821 break; \
822 case DF_DOUBLE: \
823 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
824 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], pwt->d[i]); \
825 } \
826 break; \
827 default: \
828 assert(0); \
829 } \
830 }
831
832 MSA_BINOP_DF(sll)
833 MSA_BINOP_DF(sra)
834 MSA_BINOP_DF(srl)
835 MSA_BINOP_DF(bclr)
836 MSA_BINOP_DF(bset)
837 MSA_BINOP_DF(bneg)
838 MSA_BINOP_DF(addv)
839 MSA_BINOP_DF(subv)
840 MSA_BINOP_DF(max_s)
841 MSA_BINOP_DF(max_u)
842 MSA_BINOP_DF(min_s)
843 MSA_BINOP_DF(min_u)
844 MSA_BINOP_DF(max_a)
845 MSA_BINOP_DF(min_a)
846 MSA_BINOP_DF(ceq)
847 MSA_BINOP_DF(clt_s)
848 MSA_BINOP_DF(clt_u)
849 MSA_BINOP_DF(cle_s)
850 MSA_BINOP_DF(cle_u)
851 MSA_BINOP_DF(add_a)
852 MSA_BINOP_DF(adds_a)
853 MSA_BINOP_DF(adds_s)
854 MSA_BINOP_DF(adds_u)
855 MSA_BINOP_DF(ave_s)
856 MSA_BINOP_DF(ave_u)
857 MSA_BINOP_DF(aver_s)
858 MSA_BINOP_DF(aver_u)
859 MSA_BINOP_DF(subs_s)
860 MSA_BINOP_DF(subs_u)
861 MSA_BINOP_DF(subsus_u)
862 MSA_BINOP_DF(subsuu_s)
863 MSA_BINOP_DF(asub_s)
864 MSA_BINOP_DF(asub_u)
865 MSA_BINOP_DF(mulv)
866 MSA_BINOP_DF(div_s)
867 MSA_BINOP_DF(div_u)
868 MSA_BINOP_DF(mod_s)
869 MSA_BINOP_DF(mod_u)
870 MSA_BINOP_DF(dotp_s)
871 MSA_BINOP_DF(dotp_u)
872 MSA_BINOP_DF(srar)
873 MSA_BINOP_DF(srlr)
874 MSA_BINOP_DF(hadd_s)
875 MSA_BINOP_DF(hadd_u)
876 MSA_BINOP_DF(hsub_s)
877 MSA_BINOP_DF(hsub_u)
878
879 MSA_BINOP_DF(mul_q)
880 MSA_BINOP_DF(mulr_q)
881 #undef MSA_BINOP_DF
882
883 void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
884 uint32_t ws, uint32_t rt)
885 {
886 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
887 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
888
889 msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
890 }
891
892 static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
893 int64_t arg2)
894 {
895 return dest + arg1 * arg2;
896 }
897
898 static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
899 int64_t arg2)
900 {
901 return dest - arg1 * arg2;
902 }
903
904 static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
905 int64_t arg2)
906 {
907 int64_t even_arg1;
908 int64_t even_arg2;
909 int64_t odd_arg1;
910 int64_t odd_arg2;
911 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
912 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
913 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
914 }
915
916 static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
917 int64_t arg2)
918 {
919 int64_t even_arg1;
920 int64_t even_arg2;
921 int64_t odd_arg1;
922 int64_t odd_arg2;
923 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
924 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
925 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
926 }
927
928 static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
929 int64_t arg2)
930 {
931 int64_t even_arg1;
932 int64_t even_arg2;
933 int64_t odd_arg1;
934 int64_t odd_arg2;
935 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
936 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
937 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
938 }
939
940 static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
941 int64_t arg2)
942 {
943 int64_t even_arg1;
944 int64_t even_arg2;
945 int64_t odd_arg1;
946 int64_t odd_arg2;
947 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
948 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
949 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
950 }
951
952 static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
953 int64_t arg2)
954 {
955 int64_t q_prod, q_ret;
956
957 int64_t q_max = DF_MAX_INT(df);
958 int64_t q_min = DF_MIN_INT(df);
959
960 q_prod = arg1 * arg2;
961 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1);
962
963 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
964 }
965
966 static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1,
967 int64_t arg2)
968 {
969 int64_t q_prod, q_ret;
970
971 int64_t q_max = DF_MAX_INT(df);
972 int64_t q_min = DF_MIN_INT(df);
973
974 q_prod = arg1 * arg2;
975 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1);
976
977 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
978 }
979
980 static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
981 int64_t arg2)
982 {
983 int64_t q_prod, q_ret;
984
985 int64_t q_max = DF_MAX_INT(df);
986 int64_t q_min = DF_MIN_INT(df);
987 int64_t r_bit = 1 << (DF_BITS(df) - 2);
988
989 q_prod = arg1 * arg2;
990 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
991
992 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
993 }
994
995 static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
996 int64_t arg2)
997 {
998 int64_t q_prod, q_ret;
999
1000 int64_t q_max = DF_MAX_INT(df);
1001 int64_t q_min = DF_MIN_INT(df);
1002 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1003
1004 q_prod = arg1 * arg2;
1005 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
1006
1007 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1008 }
1009
1010 #define MSA_TEROP_DF(func) \
1011 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1012 uint32_t ws, uint32_t wt) \
1013 { \
1014 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1015 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1016 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1017 uint32_t i; \
1018 \
1019 switch (df) { \
1020 case DF_BYTE: \
1021 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1022 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
1023 pwt->b[i]); \
1024 } \
1025 break; \
1026 case DF_HALF: \
1027 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1028 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
1029 pwt->h[i]); \
1030 } \
1031 break; \
1032 case DF_WORD: \
1033 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1034 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
1035 pwt->w[i]); \
1036 } \
1037 break; \
1038 case DF_DOUBLE: \
1039 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1040 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
1041 pwt->d[i]); \
1042 } \
1043 break; \
1044 default: \
1045 assert(0); \
1046 } \
1047 }
1048
1049 MSA_TEROP_DF(maddv)
1050 MSA_TEROP_DF(msubv)
1051 MSA_TEROP_DF(dpadd_s)
1052 MSA_TEROP_DF(dpadd_u)
1053 MSA_TEROP_DF(dpsub_s)
1054 MSA_TEROP_DF(dpsub_u)
1055 MSA_TEROP_DF(binsl)
1056 MSA_TEROP_DF(binsr)
1057 MSA_TEROP_DF(madd_q)
1058 MSA_TEROP_DF(msub_q)
1059 MSA_TEROP_DF(maddr_q)
1060 MSA_TEROP_DF(msubr_q)
1061 #undef MSA_TEROP_DF
1062
1063 static inline void msa_splat_df(uint32_t df, wr_t *pwd,
1064 wr_t *pws, target_ulong rt)
1065 {
1066 uint32_t n = rt % DF_ELEMENTS(df);
1067 uint32_t i;
1068
1069 switch (df) {
1070 case DF_BYTE:
1071 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1072 pwd->b[i] = pws->b[n];
1073 }
1074 break;
1075 case DF_HALF:
1076 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1077 pwd->h[i] = pws->h[n];
1078 }
1079 break;
1080 case DF_WORD:
1081 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1082 pwd->w[i] = pws->w[n];
1083 }
1084 break;
1085 case DF_DOUBLE:
1086 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1087 pwd->d[i] = pws->d[n];
1088 }
1089 break;
1090 default:
1091 assert(0);
1092 }
1093 }
1094
1095 void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1096 uint32_t ws, uint32_t rt)
1097 {
1098 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1099 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1100
1101 msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]);
1102 }
1103
1104 #define MSA_DO_B MSA_DO(b)
1105 #define MSA_DO_H MSA_DO(h)
1106 #define MSA_DO_W MSA_DO(w)
1107 #define MSA_DO_D MSA_DO(d)
1108
1109 #define MSA_LOOP_B MSA_LOOP(B)
1110 #define MSA_LOOP_H MSA_LOOP(H)
1111 #define MSA_LOOP_W MSA_LOOP(W)
1112 #define MSA_LOOP_D MSA_LOOP(D)
1113
1114 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1115 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1116 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1117 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1118
1119 #define MSA_LOOP(DF) \
1120 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1121 MSA_DO_ ## DF \
1122 }
1123
1124 #define MSA_FN_DF(FUNC) \
1125 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1126 uint32_t ws, uint32_t wt) \
1127 { \
1128 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1129 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1130 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1131 wr_t wx, *pwx = &wx; \
1132 uint32_t i; \
1133 switch (df) { \
1134 case DF_BYTE: \
1135 MSA_LOOP_B \
1136 break; \
1137 case DF_HALF: \
1138 MSA_LOOP_H \
1139 break; \
1140 case DF_WORD: \
1141 MSA_LOOP_W \
1142 break; \
1143 case DF_DOUBLE: \
1144 MSA_LOOP_D \
1145 break; \
1146 default: \
1147 assert(0); \
1148 } \
1149 msa_move_v(pwd, pwx); \
1150 }
1151
1152 #define MSA_LOOP_COND(DF) \
1153 (DF_ELEMENTS(DF) / 2)
1154
1155 #define Rb(pwr, i) (pwr->b[i])
1156 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE)/2])
1157 #define Rh(pwr, i) (pwr->h[i])
1158 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF)/2])
1159 #define Rw(pwr, i) (pwr->w[i])
1160 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD)/2])
1161 #define Rd(pwr, i) (pwr->d[i])
1162 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE)/2])
1163
1164 #define MSA_DO(DF) \
1165 do { \
1166 R##DF(pwx, i) = pwt->DF[2*i]; \
1167 L##DF(pwx, i) = pws->DF[2*i]; \
1168 } while (0);
1169 MSA_FN_DF(pckev_df)
1170 #undef MSA_DO
1171
1172 #define MSA_DO(DF) \
1173 do { \
1174 R##DF(pwx, i) = pwt->DF[2*i+1]; \
1175 L##DF(pwx, i) = pws->DF[2*i+1]; \
1176 } while (0);
1177 MSA_FN_DF(pckod_df)
1178 #undef MSA_DO
1179
1180 #define MSA_DO(DF) \
1181 do { \
1182 pwx->DF[2*i] = L##DF(pwt, i); \
1183 pwx->DF[2*i+1] = L##DF(pws, i); \
1184 } while (0);
1185 MSA_FN_DF(ilvl_df)
1186 #undef MSA_DO
1187
1188 #define MSA_DO(DF) \
1189 do { \
1190 pwx->DF[2*i] = R##DF(pwt, i); \
1191 pwx->DF[2*i+1] = R##DF(pws, i); \
1192 } while (0);
1193 MSA_FN_DF(ilvr_df)
1194 #undef MSA_DO
1195
1196 #define MSA_DO(DF) \
1197 do { \
1198 pwx->DF[2*i] = pwt->DF[2*i]; \
1199 pwx->DF[2*i+1] = pws->DF[2*i]; \
1200 } while (0);
1201 MSA_FN_DF(ilvev_df)
1202 #undef MSA_DO
1203
1204 #define MSA_DO(DF) \
1205 do { \
1206 pwx->DF[2*i] = pwt->DF[2*i+1]; \
1207 pwx->DF[2*i+1] = pws->DF[2*i+1]; \
1208 } while (0);
1209 MSA_FN_DF(ilvod_df)
1210 #undef MSA_DO
1211 #undef MSA_LOOP_COND
1212
1213 #define MSA_LOOP_COND(DF) \
1214 (DF_ELEMENTS(DF))
1215
1216 #define MSA_DO(DF) \
1217 do { \
1218 uint32_t n = DF_ELEMENTS(df); \
1219 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1220 pwx->DF[i] = \
1221 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1222 } while (0);
1223 MSA_FN_DF(vshf_df)
1224 #undef MSA_DO
1225 #undef MSA_LOOP_COND
1226 #undef MSA_FN_DF
1227
1228 void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1229 uint32_t ws, uint32_t n)
1230 {
1231 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1232 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1233
1234 msa_sld_df(df, pwd, pws, n);
1235 }
1236
1237 void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1238 uint32_t ws, uint32_t n)
1239 {
1240 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1241 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1242
1243 msa_splat_df(df, pwd, pws, n);
1244 }
1245
1246 void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1247 uint32_t ws, uint32_t n)
1248 {
1249 n %= DF_ELEMENTS(df);
1250
1251 switch (df) {
1252 case DF_BYTE:
1253 env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
1254 break;
1255 case DF_HALF:
1256 env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
1257 break;
1258 case DF_WORD:
1259 env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
1260 break;
1261 #ifdef TARGET_MIPS64
1262 case DF_DOUBLE:
1263 env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
1264 break;
1265 #endif
1266 default:
1267 assert(0);
1268 }
1269 }
1270
1271 void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1272 uint32_t ws, uint32_t n)
1273 {
1274 n %= DF_ELEMENTS(df);
1275
1276 switch (df) {
1277 case DF_BYTE:
1278 env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
1279 break;
1280 case DF_HALF:
1281 env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
1282 break;
1283 case DF_WORD:
1284 env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
1285 break;
1286 #ifdef TARGET_MIPS64
1287 case DF_DOUBLE:
1288 env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
1289 break;
1290 #endif
1291 default:
1292 assert(0);
1293 }
1294 }
1295
1296 void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1297 uint32_t rs_num, uint32_t n)
1298 {
1299 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1300 target_ulong rs = env->active_tc.gpr[rs_num];
1301
1302 switch (df) {
1303 case DF_BYTE:
1304 pwd->b[n] = (int8_t)rs;
1305 break;
1306 case DF_HALF:
1307 pwd->h[n] = (int16_t)rs;
1308 break;
1309 case DF_WORD:
1310 pwd->w[n] = (int32_t)rs;
1311 break;
1312 case DF_DOUBLE:
1313 pwd->d[n] = (int64_t)rs;
1314 break;
1315 default:
1316 assert(0);
1317 }
1318 }
1319
1320 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1321 uint32_t ws, uint32_t n)
1322 {
1323 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1324 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1325
1326 switch (df) {
1327 case DF_BYTE:
1328 pwd->b[n] = (int8_t)pws->b[0];
1329 break;
1330 case DF_HALF:
1331 pwd->h[n] = (int16_t)pws->h[0];
1332 break;
1333 case DF_WORD:
1334 pwd->w[n] = (int32_t)pws->w[0];
1335 break;
1336 case DF_DOUBLE:
1337 pwd->d[n] = (int64_t)pws->d[0];
1338 break;
1339 default:
1340 assert(0);
1341 }
1342 }
1343
1344 void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd)
1345 {
1346 switch (cd) {
1347 case 0:
1348 break;
1349 case 1:
1350 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK;
1351 restore_msa_fp_status(env);
1352 /* check exception */
1353 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)
1354 & GET_FP_CAUSE(env->active_tc.msacsr)) {
1355 do_raise_exception(env, EXCP_MSAFPE, GETPC());
1356 }
1357 break;
1358 }
1359 }
1360
1361 target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs)
1362 {
1363 switch (cs) {
1364 case 0:
1365 return env->msair;
1366 case 1:
1367 return env->active_tc.msacsr & MSACSR_MASK;
1368 }
1369 return 0;
1370 }
1371
1372 void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
1373 {
1374 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1375 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1376
1377 msa_move_v(pwd, pws);
1378 }
1379
1380 static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
1381 {
1382 uint64_t x;
1383
1384 x = UNSIGNED(arg, df);
1385
1386 x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
1387 x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
1388 x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
1389 x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
1390 x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
1391 x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
1392
1393 return x;
1394 }
1395
1396 static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
1397 {
1398 uint64_t x, y;
1399 int n, c;
1400
1401 x = UNSIGNED(arg, df);
1402 n = DF_BITS(df);
1403 c = DF_BITS(df) / 2;
1404
1405 do {
1406 y = x >> c;
1407 if (y != 0) {
1408 n = n - c;
1409 x = y;
1410 }
1411 c = c >> 1;
1412 } while (c != 0);
1413
1414 return n - x;
1415 }
1416
1417 static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
1418 {
1419 return msa_nlzc_df(df, UNSIGNED((~arg), df));
1420 }
1421
1422 void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1423 uint32_t rs)
1424 {
1425 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1426 uint32_t i;
1427
1428 switch (df) {
1429 case DF_BYTE:
1430 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1431 pwd->b[i] = (int8_t)env->active_tc.gpr[rs];
1432 }
1433 break;
1434 case DF_HALF:
1435 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1436 pwd->h[i] = (int16_t)env->active_tc.gpr[rs];
1437 }
1438 break;
1439 case DF_WORD:
1440 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1441 pwd->w[i] = (int32_t)env->active_tc.gpr[rs];
1442 }
1443 break;
1444 case DF_DOUBLE:
1445 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1446 pwd->d[i] = (int64_t)env->active_tc.gpr[rs];
1447 }
1448 break;
1449 default:
1450 assert(0);
1451 }
1452 }
1453
1454 #define MSA_UNOP_DF(func) \
1455 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1456 uint32_t wd, uint32_t ws) \
1457 { \
1458 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1459 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1460 uint32_t i; \
1461 \
1462 switch (df) { \
1463 case DF_BYTE: \
1464 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1465 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i]); \
1466 } \
1467 break; \
1468 case DF_HALF: \
1469 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1470 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i]); \
1471 } \
1472 break; \
1473 case DF_WORD: \
1474 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1475 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i]); \
1476 } \
1477 break; \
1478 case DF_DOUBLE: \
1479 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1480 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i]); \
1481 } \
1482 break; \
1483 default: \
1484 assert(0); \
1485 } \
1486 }
1487
1488 MSA_UNOP_DF(nlzc)
1489 MSA_UNOP_DF(nloc)
1490 MSA_UNOP_DF(pcnt)
1491 #undef MSA_UNOP_DF
1492
1493 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1494 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1495
1496 #define FLOAT_SNAN16 (float16_default_nan ^ 0x0220)
1497 /* 0x7c20 */
1498 #define FLOAT_SNAN32 (float32_default_nan ^ 0x00400020)
1499 /* 0x7f800020 */
1500 #define FLOAT_SNAN64 (float64_default_nan ^ 0x0008000000000020ULL)
1501 /* 0x7ff0000000000020 */
1502
1503 static inline void clear_msacsr_cause(CPUMIPSState *env)
1504 {
1505 SET_FP_CAUSE(env->active_tc.msacsr, 0);
1506 }
1507
1508 static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
1509 {
1510 if ((GET_FP_CAUSE(env->active_tc.msacsr) &
1511 (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) {
1512 UPDATE_FP_FLAGS(env->active_tc.msacsr,
1513 GET_FP_CAUSE(env->active_tc.msacsr));
1514 } else {
1515 do_raise_exception(env, EXCP_MSAFPE, retaddr);
1516 }
1517 }
1518
1519 /* Flush-to-zero use cases for update_msacsr() */
1520 #define CLEAR_FS_UNDERFLOW 1
1521 #define CLEAR_IS_INEXACT 2
1522 #define RECIPROCAL_INEXACT 4
1523
1524 static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
1525 {
1526 int ieee_ex;
1527
1528 int c;
1529 int cause;
1530 int enable;
1531
1532 ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
1533
1534 /* QEMU softfloat does not signal all underflow cases */
1535 if (denormal) {
1536 ieee_ex |= float_flag_underflow;
1537 }
1538
1539 c = ieee_ex_to_mips(ieee_ex);
1540 enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1541
1542 /* Set Inexact (I) when flushing inputs to zero */
1543 if ((ieee_ex & float_flag_input_denormal) &&
1544 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1545 if (action & CLEAR_IS_INEXACT) {
1546 c &= ~FP_INEXACT;
1547 } else {
1548 c |= FP_INEXACT;
1549 }
1550 }
1551
1552 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
1553 if ((ieee_ex & float_flag_output_denormal) &&
1554 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1555 c |= FP_INEXACT;
1556 if (action & CLEAR_FS_UNDERFLOW) {
1557 c &= ~FP_UNDERFLOW;
1558 } else {
1559 c |= FP_UNDERFLOW;
1560 }
1561 }
1562
1563 /* Set Inexact (I) when Overflow (O) is not enabled */
1564 if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
1565 c |= FP_INEXACT;
1566 }
1567
1568 /* Clear Exact Underflow when Underflow (U) is not enabled */
1569 if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
1570 (c & FP_INEXACT) == 0) {
1571 c &= ~FP_UNDERFLOW;
1572 }
1573
1574 /* Reciprocal operations set only Inexact when valid and not
1575 divide by zero */
1576 if ((action & RECIPROCAL_INEXACT) &&
1577 (c & (FP_INVALID | FP_DIV0)) == 0) {
1578 c = FP_INEXACT;
1579 }
1580
1581 cause = c & enable; /* all current enabled exceptions */
1582
1583 if (cause == 0) {
1584 /* No enabled exception, update the MSACSR Cause
1585 with all current exceptions */
1586 SET_FP_CAUSE(env->active_tc.msacsr,
1587 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1588 } else {
1589 /* Current exceptions are enabled */
1590 if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
1591 /* Exception(s) will trap, update MSACSR Cause
1592 with all enabled exceptions */
1593 SET_FP_CAUSE(env->active_tc.msacsr,
1594 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1595 }
1596 }
1597
1598 return c;
1599 }
1600
1601 static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
1602 {
1603 int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1604 return c & enable;
1605 }
1606
1607 static inline float16 float16_from_float32(int32 a, flag ieee,
1608 float_status *status)
1609 {
1610 float16 f_val;
1611
1612 f_val = float32_to_float16((float32)a, ieee, status);
1613 f_val = float16_maybe_silence_nan(f_val);
1614
1615 return a < 0 ? (f_val | (1 << 15)) : f_val;
1616 }
1617
1618 static inline float32 float32_from_float64(int64 a, float_status *status)
1619 {
1620 float32 f_val;
1621
1622 f_val = float64_to_float32((float64)a, status);
1623 f_val = float32_maybe_silence_nan(f_val);
1624
1625 return a < 0 ? (f_val | (1 << 31)) : f_val;
1626 }
1627
1628 static inline float32 float32_from_float16(int16_t a, flag ieee,
1629 float_status *status)
1630 {
1631 float32 f_val;
1632
1633 f_val = float16_to_float32((float16)a, ieee, status);
1634 f_val = float32_maybe_silence_nan(f_val);
1635
1636 return a < 0 ? (f_val | (1 << 31)) : f_val;
1637 }
1638
1639 static inline float64 float64_from_float32(int32 a, float_status *status)
1640 {
1641 float64 f_val;
1642
1643 f_val = float32_to_float64((float64)a, status);
1644 f_val = float64_maybe_silence_nan(f_val);
1645
1646 return a < 0 ? (f_val | (1ULL << 63)) : f_val;
1647 }
1648
1649 static inline float32 float32_from_q16(int16_t a, float_status *status)
1650 {
1651 float32 f_val;
1652
1653 /* conversion as integer and scaling */
1654 f_val = int32_to_float32(a, status);
1655 f_val = float32_scalbn(f_val, -15, status);
1656
1657 return f_val;
1658 }
1659
1660 static inline float64 float64_from_q32(int32 a, float_status *status)
1661 {
1662 float64 f_val;
1663
1664 /* conversion as integer and scaling */
1665 f_val = int32_to_float64(a, status);
1666 f_val = float64_scalbn(f_val, -31, status);
1667
1668 return f_val;
1669 }
1670
1671 static inline int16_t float32_to_q16(float32 a, float_status *status)
1672 {
1673 int32 q_val;
1674 int32 q_min = 0xffff8000;
1675 int32 q_max = 0x00007fff;
1676
1677 int ieee_ex;
1678
1679 if (float32_is_any_nan(a)) {
1680 float_raise(float_flag_invalid, status);
1681 return 0;
1682 }
1683
1684 /* scaling */
1685 a = float32_scalbn(a, 15, status);
1686
1687 ieee_ex = get_float_exception_flags(status);
1688 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1689 , status);
1690
1691 if (ieee_ex & float_flag_overflow) {
1692 float_raise(float_flag_inexact, status);
1693 return (int32)a < 0 ? q_min : q_max;
1694 }
1695
1696 /* conversion to int */
1697 q_val = float32_to_int32(a, status);
1698
1699 ieee_ex = get_float_exception_flags(status);
1700 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1701 , status);
1702
1703 if (ieee_ex & float_flag_invalid) {
1704 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1705 , status);
1706 float_raise(float_flag_overflow | float_flag_inexact, status);
1707 return (int32)a < 0 ? q_min : q_max;
1708 }
1709
1710 if (q_val < q_min) {
1711 float_raise(float_flag_overflow | float_flag_inexact, status);
1712 return (int16_t)q_min;
1713 }
1714
1715 if (q_max < q_val) {
1716 float_raise(float_flag_overflow | float_flag_inexact, status);
1717 return (int16_t)q_max;
1718 }
1719
1720 return (int16_t)q_val;
1721 }
1722
1723 static inline int32 float64_to_q32(float64 a, float_status *status)
1724 {
1725 int64 q_val;
1726 int64 q_min = 0xffffffff80000000LL;
1727 int64 q_max = 0x000000007fffffffLL;
1728
1729 int ieee_ex;
1730
1731 if (float64_is_any_nan(a)) {
1732 float_raise(float_flag_invalid, status);
1733 return 0;
1734 }
1735
1736 /* scaling */
1737 a = float64_scalbn(a, 31, status);
1738
1739 ieee_ex = get_float_exception_flags(status);
1740 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1741 , status);
1742
1743 if (ieee_ex & float_flag_overflow) {
1744 float_raise(float_flag_inexact, status);
1745 return (int64)a < 0 ? q_min : q_max;
1746 }
1747
1748 /* conversion to integer */
1749 q_val = float64_to_int64(a, status);
1750
1751 ieee_ex = get_float_exception_flags(status);
1752 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1753 , status);
1754
1755 if (ieee_ex & float_flag_invalid) {
1756 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1757 , status);
1758 float_raise(float_flag_overflow | float_flag_inexact, status);
1759 return (int64)a < 0 ? q_min : q_max;
1760 }
1761
1762 if (q_val < q_min) {
1763 float_raise(float_flag_overflow | float_flag_inexact, status);
1764 return (int32)q_min;
1765 }
1766
1767 if (q_max < q_val) {
1768 float_raise(float_flag_overflow | float_flag_inexact, status);
1769 return (int32)q_max;
1770 }
1771
1772 return (int32)q_val;
1773 }
1774
1775 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
1776 do { \
1777 float_status *status = &env->active_tc.msa_fp_status; \
1778 int c; \
1779 int64_t cond; \
1780 set_float_exception_flags(0, status); \
1781 if (!QUIET) { \
1782 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
1783 } else { \
1784 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
1785 } \
1786 DEST = cond ? M_MAX_UINT(BITS) : 0; \
1787 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
1788 \
1789 if (get_enabled_exceptions(env, c)) { \
1790 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
1791 } \
1792 } while (0)
1793
1794 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
1795 do { \
1796 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1797 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
1798 DEST = 0; \
1799 } \
1800 } while (0)
1801
1802 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
1803 do { \
1804 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1805 if (DEST == 0) { \
1806 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1807 } \
1808 } while (0)
1809
1810 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
1811 do { \
1812 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1813 if (DEST == 0) { \
1814 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1815 } \
1816 } while (0)
1817
1818 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
1819 do { \
1820 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1821 if (DEST == 0) { \
1822 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1823 if (DEST == 0) { \
1824 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1825 } \
1826 } \
1827 } while (0)
1828
1829 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
1830 do { \
1831 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1832 if (DEST == 0) { \
1833 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1834 } \
1835 } while (0)
1836
1837 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
1838 do { \
1839 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1840 if (DEST == 0) { \
1841 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1842 } \
1843 } while (0)
1844
1845 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
1846 do { \
1847 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1848 if (DEST == 0) { \
1849 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
1850 } \
1851 } while (0)
1852
1853 static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1854 wr_t *pwt, uint32_t df, int quiet,
1855 uintptr_t retaddr)
1856 {
1857 wr_t wx, *pwx = &wx;
1858 uint32_t i;
1859
1860 clear_msacsr_cause(env);
1861
1862 switch (df) {
1863 case DF_WORD:
1864 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1865 MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1866 }
1867 break;
1868 case DF_DOUBLE:
1869 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1870 MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1871 }
1872 break;
1873 default:
1874 assert(0);
1875 }
1876
1877 check_msacsr_cause(env, retaddr);
1878
1879 msa_move_v(pwd, pwx);
1880 }
1881
1882 static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1883 wr_t *pwt, uint32_t df, int quiet,
1884 uintptr_t retaddr)
1885 {
1886 wr_t wx, *pwx = &wx;
1887 uint32_t i;
1888
1889 clear_msacsr_cause(env);
1890
1891 switch (df) {
1892 case DF_WORD:
1893 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1894 MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32,
1895 quiet);
1896 }
1897 break;
1898 case DF_DOUBLE:
1899 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1900 MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64,
1901 quiet);
1902 }
1903 break;
1904 default:
1905 assert(0);
1906 }
1907
1908 check_msacsr_cause(env, retaddr);
1909
1910 msa_move_v(pwd, pwx);
1911 }
1912
1913 static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1914 wr_t *pwt, uint32_t df, int quiet,
1915 uintptr_t retaddr)
1916 {
1917 wr_t wx, *pwx = &wx;
1918 uint32_t i;
1919
1920 clear_msacsr_cause(env);
1921
1922 switch (df) {
1923 case DF_WORD:
1924 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1925 MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet);
1926 }
1927 break;
1928 case DF_DOUBLE:
1929 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1930 MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet);
1931 }
1932 break;
1933 default:
1934 assert(0);
1935 }
1936
1937 check_msacsr_cause(env, retaddr);
1938
1939 msa_move_v(pwd, pwx);
1940 }
1941
1942 static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1943 wr_t *pwt, uint32_t df, int quiet,
1944 uintptr_t retaddr)
1945 {
1946 wr_t wx, *pwx = &wx;
1947 uint32_t i;
1948
1949 clear_msacsr_cause(env);
1950
1951 switch (df) {
1952 case DF_WORD:
1953 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1954 MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1955 }
1956 break;
1957 case DF_DOUBLE:
1958 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1959 MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1960 }
1961 break;
1962 default:
1963 assert(0);
1964 }
1965
1966 check_msacsr_cause(env, retaddr);
1967
1968 msa_move_v(pwd, pwx);
1969 }
1970
1971 static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1972 wr_t *pwt, uint32_t df, int quiet,
1973 uintptr_t retaddr)
1974 {
1975 wr_t wx, *pwx = &wx;
1976 uint32_t i;
1977
1978 clear_msacsr_cause(env);
1979
1980 switch (df) {
1981 case DF_WORD:
1982 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1983 MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet);
1984 }
1985 break;
1986 case DF_DOUBLE:
1987 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1988 MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet);
1989 }
1990 break;
1991 default:
1992 assert(0);
1993 }
1994
1995 check_msacsr_cause(env, retaddr);
1996
1997 msa_move_v(pwd, pwx);
1998 }
1999
2000 static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2001 wr_t *pwt, uint32_t df, int quiet,
2002 uintptr_t retaddr)
2003 {
2004 wr_t wx, *pwx = &wx;
2005 uint32_t i;
2006
2007 clear_msacsr_cause(env);
2008
2009 switch (df) {
2010 case DF_WORD:
2011 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2012 MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2013 }
2014 break;
2015 case DF_DOUBLE:
2016 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2017 MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2018 }
2019 break;
2020 default:
2021 assert(0);
2022 }
2023
2024 check_msacsr_cause(env, retaddr);
2025
2026 msa_move_v(pwd, pwx);
2027 }
2028
2029 static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2030 wr_t *pwt, uint32_t df, int quiet,
2031 uintptr_t retaddr)
2032 {
2033 wr_t wx, *pwx = &wx;
2034 uint32_t i;
2035
2036 clear_msacsr_cause(env);
2037
2038 switch (df) {
2039 case DF_WORD:
2040 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2041 MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet);
2042 }
2043 break;
2044 case DF_DOUBLE:
2045 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2046 MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet);
2047 }
2048 break;
2049 default:
2050 assert(0);
2051 }
2052
2053 check_msacsr_cause(env, retaddr);
2054
2055 msa_move_v(pwd, pwx);
2056 }
2057
2058 static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2059 wr_t *pwt, uint32_t df, int quiet,
2060 uintptr_t retaddr)
2061 {
2062 wr_t wx, *pwx = &wx;
2063 uint32_t i;
2064
2065 clear_msacsr_cause(env);
2066
2067 switch (df) {
2068 case DF_WORD:
2069 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2070 MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2071 }
2072 break;
2073 case DF_DOUBLE:
2074 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2075 MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2076 }
2077 break;
2078 default:
2079 assert(0);
2080 }
2081
2082 check_msacsr_cause(env, retaddr);
2083
2084 msa_move_v(pwd, pwx);
2085 }
2086
2087 static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2088 wr_t *pwt, uint32_t df, int quiet,
2089 uintptr_t retaddr)
2090 {
2091 wr_t wx, *pwx = &wx;
2092 uint32_t i;
2093
2094 clear_msacsr_cause(env);
2095
2096 switch (df) {
2097 case DF_WORD:
2098 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2099 MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2100 }
2101 break;
2102 case DF_DOUBLE:
2103 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2104 MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2105 }
2106 break;
2107 default:
2108 assert(0);
2109 }
2110
2111 check_msacsr_cause(env, retaddr);
2112
2113 msa_move_v(pwd, pwx);
2114 }
2115
2116 static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2117 wr_t *pwt, uint32_t df, int quiet,
2118 uintptr_t retaddr)
2119 {
2120 wr_t wx, *pwx = &wx;
2121 uint32_t i;
2122
2123 clear_msacsr_cause(env);
2124
2125 switch (df) {
2126 case DF_WORD:
2127 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2128 MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2129 }
2130 break;
2131 case DF_DOUBLE:
2132 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2133 MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2134 }
2135 break;
2136 default:
2137 assert(0);
2138 }
2139
2140 check_msacsr_cause(env, retaddr);
2141
2142 msa_move_v(pwd, pwx);
2143 }
2144
2145 static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2146 wr_t *pwt, uint32_t df, int quiet,
2147 uintptr_t retaddr)
2148 {
2149 wr_t wx, *pwx = &wx;
2150 uint32_t i;
2151
2152 clear_msacsr_cause(env);
2153
2154 switch (df) {
2155 case DF_WORD:
2156 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2157 MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2158 }
2159 break;
2160 case DF_DOUBLE:
2161 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2162 MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2163 }
2164 break;
2165 default:
2166 assert(0);
2167 }
2168
2169 check_msacsr_cause(env, retaddr);
2170
2171 msa_move_v(pwd, pwx);
2172 }
2173
2174 void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2175 uint32_t ws, uint32_t wt)
2176 {
2177 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2178 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2179 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2180 compare_af(env, pwd, pws, pwt, df, 1, GETPC());
2181 }
2182
2183 void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2184 uint32_t ws, uint32_t wt)
2185 {
2186 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2187 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2188 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2189 compare_un(env, pwd, pws, pwt, df, 1, GETPC());
2190 }
2191
2192 void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2193 uint32_t ws, uint32_t wt)
2194 {
2195 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2196 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2197 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2198 compare_eq(env, pwd, pws, pwt, df, 1, GETPC());
2199 }
2200
2201 void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2202 uint32_t ws, uint32_t wt)
2203 {
2204 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2205 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2206 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2207 compare_ueq(env, pwd, pws, pwt, df, 1, GETPC());
2208 }
2209
2210 void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2211 uint32_t ws, uint32_t wt)
2212 {
2213 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2214 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2215 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2216 compare_lt(env, pwd, pws, pwt, df, 1, GETPC());
2217 }
2218
2219 void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2220 uint32_t ws, uint32_t wt)
2221 {
2222 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2223 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2224 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2225 compare_ult(env, pwd, pws, pwt, df, 1, GETPC());
2226 }
2227
2228 void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2229 uint32_t ws, uint32_t wt)
2230 {
2231 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2232 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2233 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2234 compare_le(env, pwd, pws, pwt, df, 1, GETPC());
2235 }
2236
2237 void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2238 uint32_t ws, uint32_t wt)
2239 {
2240 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2241 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2242 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2243 compare_ule(env, pwd, pws, pwt, df, 1, GETPC());
2244 }
2245
2246 void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2247 uint32_t ws, uint32_t wt)
2248 {
2249 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2250 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2251 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2252 compare_af(env, pwd, pws, pwt, df, 0, GETPC());
2253 }
2254
2255 void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2256 uint32_t ws, uint32_t wt)
2257 {
2258 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2259 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2260 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2261 compare_un(env, pwd, pws, pwt, df, 0, GETPC());
2262 }
2263
2264 void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2265 uint32_t ws, uint32_t wt)
2266 {
2267 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2268 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2269 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2270 compare_eq(env, pwd, pws, pwt, df, 0, GETPC());
2271 }
2272
2273 void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2274 uint32_t ws, uint32_t wt)
2275 {
2276 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2277 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2278 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2279 compare_ueq(env, pwd, pws, pwt, df, 0, GETPC());
2280 }
2281
2282 void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2283 uint32_t ws, uint32_t wt)
2284 {
2285 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2286 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2287 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2288 compare_lt(env, pwd, pws, pwt, df, 0, GETPC());
2289 }
2290
2291 void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2292 uint32_t ws, uint32_t wt)
2293 {
2294 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2295 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2296 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2297 compare_ult(env, pwd, pws, pwt, df, 0, GETPC());
2298 }
2299
2300 void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2301 uint32_t ws, uint32_t wt)
2302 {
2303 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2304 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2305 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2306 compare_le(env, pwd, pws, pwt, df, 0, GETPC());
2307 }
2308
2309 void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2310 uint32_t ws, uint32_t wt)
2311 {
2312 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2313 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2314 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2315 compare_ule(env, pwd, pws, pwt, df, 0, GETPC());
2316 }
2317
2318 void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2319 uint32_t ws, uint32_t wt)
2320 {
2321 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2322 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2323 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2324 compare_or(env, pwd, pws, pwt, df, 1, GETPC());
2325 }
2326
2327 void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2328 uint32_t ws, uint32_t wt)
2329 {
2330 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2331 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2332 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2333 compare_une(env, pwd, pws, pwt, df, 1, GETPC());
2334 }
2335
2336 void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2337 uint32_t ws, uint32_t wt)
2338 {
2339 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2340 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2341 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2342 compare_ne(env, pwd, pws, pwt, df, 1, GETPC());
2343 }
2344
2345 void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2346 uint32_t ws, uint32_t wt)
2347 {
2348 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2349 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2350 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2351 compare_or(env, pwd, pws, pwt, df, 0, GETPC());
2352 }
2353
2354 void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2355 uint32_t ws, uint32_t wt)
2356 {
2357 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2358 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2359 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2360 compare_une(env, pwd, pws, pwt, df, 0, GETPC());
2361 }
2362
2363 void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2364 uint32_t ws, uint32_t wt)
2365 {
2366 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2367 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2368 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2369 compare_ne(env, pwd, pws, pwt, df, 0, GETPC());
2370 }
2371
2372 #define float16_is_zero(ARG) 0
2373 #define float16_is_zero_or_denormal(ARG) 0
2374
2375 #define IS_DENORMAL(ARG, BITS) \
2376 (!float ## BITS ## _is_zero(ARG) \
2377 && float ## BITS ## _is_zero_or_denormal(ARG))
2378
2379 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
2380 do { \
2381 float_status *status = &env->active_tc.msa_fp_status; \
2382 int c; \
2383 \
2384 set_float_exception_flags(0, status); \
2385 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2386 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2387 \
2388 if (get_enabled_exceptions(env, c)) { \
2389 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2390 } \
2391 } while (0)
2392
2393 void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2394 uint32_t ws, uint32_t wt)
2395 {
2396 wr_t wx, *pwx = &wx;
2397 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2398 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2399 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2400 uint32_t i;
2401
2402 clear_msacsr_cause(env);
2403
2404 switch (df) {
2405 case DF_WORD:
2406 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2407 MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32);
2408 }
2409 break;
2410 case DF_DOUBLE:
2411 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2412 MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64);
2413 }
2414 break;
2415 default:
2416 assert(0);
2417 }
2418
2419 check_msacsr_cause(env, GETPC());
2420 msa_move_v(pwd, pwx);
2421 }
2422
2423 void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2424 uint32_t ws, uint32_t wt)
2425 {
2426 wr_t wx, *pwx = &wx;
2427 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2428 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2429 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2430 uint32_t i;
2431
2432 clear_msacsr_cause(env);
2433
2434 switch (df) {
2435 case DF_WORD:
2436 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2437 MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32);
2438 }
2439 break;
2440 case DF_DOUBLE:
2441 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2442 MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64);
2443 }
2444 break;
2445 default:
2446 assert(0);
2447 }
2448
2449 check_msacsr_cause(env, GETPC());
2450 msa_move_v(pwd, pwx);
2451 }
2452
2453 void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2454 uint32_t ws, uint32_t wt)
2455 {
2456 wr_t wx, *pwx = &wx;
2457 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2458 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2459 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2460 uint32_t i;
2461
2462 clear_msacsr_cause(env);
2463
2464 switch (df) {
2465 case DF_WORD:
2466 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2467 MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32);
2468 }
2469 break;
2470 case DF_DOUBLE:
2471 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2472 MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64);
2473 }
2474 break;
2475 default:
2476 assert(0);
2477 }
2478
2479 check_msacsr_cause(env, GETPC());
2480
2481 msa_move_v(pwd, pwx);
2482 }
2483
2484 void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2485 uint32_t ws, uint32_t wt)
2486 {
2487 wr_t wx, *pwx = &wx;
2488 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2489 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2490 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2491 uint32_t i;
2492
2493 clear_msacsr_cause(env);
2494
2495 switch (df) {
2496 case DF_WORD:
2497 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2498 MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32);
2499 }
2500 break;
2501 case DF_DOUBLE:
2502 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2503 MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64);
2504 }
2505 break;
2506 default:
2507 assert(0);
2508 }
2509
2510 check_msacsr_cause(env, GETPC());
2511
2512 msa_move_v(pwd, pwx);
2513 }
2514
2515 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
2516 do { \
2517 float_status *status = &env->active_tc.msa_fp_status; \
2518 int c; \
2519 \
2520 set_float_exception_flags(0, status); \
2521 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
2522 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2523 \
2524 if (get_enabled_exceptions(env, c)) { \
2525 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2526 } \
2527 } while (0)
2528
2529 void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2530 uint32_t ws, uint32_t wt)
2531 {
2532 wr_t wx, *pwx = &wx;
2533 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2534 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2535 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2536 uint32_t i;
2537
2538 clear_msacsr_cause(env);
2539
2540 switch (df) {
2541 case DF_WORD:
2542 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2543 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2544 pws->w[i], pwt->w[i], 0, 32);
2545 }
2546 break;
2547 case DF_DOUBLE:
2548 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2549 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2550 pws->d[i], pwt->d[i], 0, 64);
2551 }
2552 break;
2553 default:
2554 assert(0);
2555 }
2556
2557 check_msacsr_cause(env, GETPC());
2558
2559 msa_move_v(pwd, pwx);
2560 }
2561
2562 void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2563 uint32_t ws, uint32_t wt)
2564 {
2565 wr_t wx, *pwx = &wx;
2566 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2567 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2568 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2569 uint32_t i;
2570
2571 clear_msacsr_cause(env);
2572
2573 switch (df) {
2574 case DF_WORD:
2575 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2576 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2577 pws->w[i], pwt->w[i],
2578 float_muladd_negate_product, 32);
2579 }
2580 break;
2581 case DF_DOUBLE:
2582 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2583 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2584 pws->d[i], pwt->d[i],
2585 float_muladd_negate_product, 64);
2586 }
2587 break;
2588 default:
2589 assert(0);
2590 }
2591
2592 check_msacsr_cause(env, GETPC());
2593
2594 msa_move_v(pwd, pwx);
2595 }
2596
2597 void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2598 uint32_t ws, uint32_t wt)
2599 {
2600 wr_t wx, *pwx = &wx;
2601 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2602 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2603 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2604 uint32_t i;
2605
2606 clear_msacsr_cause(env);
2607
2608 switch (df) {
2609 case DF_WORD:
2610 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2611 MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i],
2612 pwt->w[i] > 0x200 ? 0x200 :
2613 pwt->w[i] < -0x200 ? -0x200 : pwt->w[i],
2614 32);
2615 }
2616 break;
2617 case DF_DOUBLE:
2618 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2619 MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i],
2620 pwt->d[i] > 0x1000 ? 0x1000 :
2621 pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i],
2622 64);
2623 }
2624 break;
2625 default:
2626 assert(0);
2627 }
2628
2629 check_msacsr_cause(env, GETPC());
2630
2631 msa_move_v(pwd, pwx);
2632 }
2633
2634 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
2635 do { \
2636 float_status *status = &env->active_tc.msa_fp_status; \
2637 int c; \
2638 \
2639 set_float_exception_flags(0, status); \
2640 DEST = float ## BITS ## _ ## OP(ARG, status); \
2641 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2642 \
2643 if (get_enabled_exceptions(env, c)) { \
2644 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2645 } \
2646 } while (0)
2647
2648 void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2649 uint32_t ws, uint32_t wt)
2650 {
2651 wr_t wx, *pwx = &wx;
2652 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2653 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2654 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2655 uint32_t i;
2656
2657 clear_msacsr_cause(env);
2658
2659 switch (df) {
2660 case DF_WORD:
2661 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2662 /* Half precision floats come in two formats: standard
2663 IEEE and "ARM" format. The latter gains extra exponent
2664 range by omitting the NaN/Inf encodings. */
2665 flag ieee = 1;
2666
2667 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
2668 MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16);
2669 }
2670 break;
2671 case DF_DOUBLE:
2672 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2673 MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32);
2674 MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32);
2675 }
2676 break;
2677 default:
2678 assert(0);
2679 }
2680
2681 check_msacsr_cause(env, GETPC());
2682 msa_move_v(pwd, pwx);
2683 }
2684
2685 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
2686 do { \
2687 float_status *status = &env->active_tc.msa_fp_status; \
2688 int c; \
2689 \
2690 set_float_exception_flags(0, status); \
2691 DEST = float ## BITS ## _ ## OP(ARG, status); \
2692 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2693 \
2694 if (get_enabled_exceptions(env, c)) { \
2695 DEST = ((FLOAT_SNAN ## XBITS >> 6) << 6) | c; \
2696 } \
2697 } while (0)
2698
2699 void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2700 uint32_t ws, uint32_t wt)
2701 {
2702 wr_t wx, *pwx = &wx;
2703 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2704 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2705 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2706 uint32_t i;
2707
2708 clear_msacsr_cause(env);
2709
2710 switch (df) {
2711 case DF_WORD:
2712 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2713 MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16);
2714 MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16);
2715 }
2716 break;
2717 case DF_DOUBLE:
2718 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2719 MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32);
2720 MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32);
2721 }
2722 break;
2723 default:
2724 assert(0);
2725 }
2726
2727 check_msacsr_cause(env, GETPC());
2728
2729 msa_move_v(pwd, pwx);
2730 }
2731
2732 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS) \
2733 !float ## BITS ## _is_any_nan(ARG1) \
2734 && float ## BITS ## _is_quiet_nan(ARG2)
2735
2736 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
2737 do { \
2738 float_status *status = &env->active_tc.msa_fp_status; \
2739 int c; \
2740 \
2741 set_float_exception_flags(0, status); \
2742 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2743 c = update_msacsr(env, 0, 0); \
2744 \
2745 if (get_enabled_exceptions(env, c)) { \
2746 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2747 } \
2748 } while (0)
2749
2750 #define FMAXMIN_A(F, G, X, _S, _T, BITS) \
2751 do { \
2752 uint## BITS ##_t S = _S, T = _T; \
2753 uint## BITS ##_t as, at, xs, xt, xd; \
2754 if (NUMBER_QNAN_PAIR(S, T, BITS)) { \
2755 T = S; \
2756 } \
2757 else if (NUMBER_QNAN_PAIR(T, S, BITS)) { \
2758 S = T; \
2759 } \
2760 as = float## BITS ##_abs(S); \
2761 at = float## BITS ##_abs(T); \
2762 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
2763 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
2764 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
2765 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
2766 } while (0)
2767
2768 void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2769 uint32_t ws, uint32_t wt)
2770 {
2771 wr_t wx, *pwx = &wx;
2772 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2773 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2774 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2775 uint32_t i;
2776
2777 clear_msacsr_cause(env);
2778
2779 switch (df) {
2780 case DF_WORD:
2781 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2782 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
2783 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pws->w[i], 32);
2784 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
2785 MSA_FLOAT_MAXOP(pwx->w[i], min, pwt->w[i], pwt->w[i], 32);
2786 } else {
2787 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pwt->w[i], 32);
2788 }
2789 }
2790 break;
2791 case DF_DOUBLE:
2792 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2793 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
2794 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pws->d[i], 64);
2795 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
2796 MSA_FLOAT_MAXOP(pwx->d[i], min, pwt->d[i], pwt->d[i], 64);
2797 } else {
2798 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pwt->d[i], 64);
2799 }
2800 }
2801 break;
2802 default:
2803 assert(0);
2804 }
2805
2806 check_msacsr_cause(env, GETPC());
2807
2808 msa_move_v(pwd, pwx);
2809 }
2810
2811 void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2812 uint32_t ws, uint32_t wt)
2813 {
2814 wr_t wx, *pwx = &wx;
2815 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2816 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2817 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2818 uint32_t i;
2819
2820 clear_msacsr_cause(env);
2821
2822 switch (df) {
2823 case DF_WORD:
2824 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2825 FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32);
2826 }
2827 break;
2828 case DF_DOUBLE:
2829 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2830 FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64);
2831 }
2832 break;
2833 default:
2834 assert(0);
2835 }
2836
2837 check_msacsr_cause(env, GETPC());
2838
2839 msa_move_v(pwd, pwx);
2840 }
2841
2842 void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2843 uint32_t ws, uint32_t wt)
2844 {
2845 wr_t wx, *pwx = &wx;
2846 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2847 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2848 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2849 uint32_t i;
2850
2851 clear_msacsr_cause(env);
2852
2853 switch (df) {
2854 case DF_WORD:
2855 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2856 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
2857 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pws->w[i], 32);
2858 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
2859 MSA_FLOAT_MAXOP(pwx->w[i], max, pwt->w[i], pwt->w[i], 32);
2860 } else {
2861 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pwt->w[i], 32);
2862 }
2863 }
2864 break;
2865 case DF_DOUBLE:
2866 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2867 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
2868 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pws->d[i], 64);
2869 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
2870 MSA_FLOAT_MAXOP(pwx->d[i], max, pwt->d[i], pwt->d[i], 64);
2871 } else {
2872 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pwt->d[i], 64);
2873 }
2874 }
2875 break;
2876 default:
2877 assert(0);
2878 }
2879
2880 check_msacsr_cause(env, GETPC());
2881
2882 msa_move_v(pwd, pwx);
2883 }
2884
2885 void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2886 uint32_t ws, uint32_t wt)
2887 {
2888 wr_t wx, *pwx = &wx;
2889 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2890 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2891 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2892 uint32_t i;
2893
2894 clear_msacsr_cause(env);
2895
2896 switch (df) {
2897 case DF_WORD:
2898 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2899 FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32);
2900 }
2901 break;
2902 case DF_DOUBLE:
2903 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2904 FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64);
2905 }
2906 break;
2907 default:
2908 assert(0);
2909 }
2910
2911 check_msacsr_cause(env, GETPC());
2912
2913 msa_move_v(pwd, pwx);
2914 }
2915
2916 void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
2917 uint32_t wd, uint32_t ws)
2918 {
2919 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2920 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2921 if (df == DF_WORD) {
2922 pwd->w[0] = helper_float_class_s(pws->w[0]);
2923 pwd->w[1] = helper_float_class_s(pws->w[1]);
2924 pwd->w[2] = helper_float_class_s(pws->w[2]);
2925 pwd->w[3] = helper_float_class_s(pws->w[3]);
2926 } else {
2927 pwd->d[0] = helper_float_class_d(pws->d[0]);
2928 pwd->d[1] = helper_float_class_d(pws->d[1]);
2929 }
2930 }
2931
2932 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
2933 do { \
2934 float_status *status = &env->active_tc.msa_fp_status; \
2935 int c; \
2936 \
2937 set_float_exception_flags(0, status); \
2938 DEST = float ## BITS ## _ ## OP(ARG, status); \
2939 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2940 \
2941 if (get_enabled_exceptions(env, c)) { \
2942 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2943 } else if (float ## BITS ## _is_any_nan(ARG)) { \
2944 DEST = 0; \
2945 } \
2946 } while (0)
2947
2948 void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2949 uint32_t ws)
2950 {
2951 wr_t wx, *pwx = &wx;
2952 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2953 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2954 uint32_t i;
2955
2956 clear_msacsr_cause(env);
2957
2958 switch (df) {
2959 case DF_WORD:
2960 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2961 MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32);
2962 }
2963 break;
2964 case DF_DOUBLE:
2965 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2966 MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64);
2967 }
2968 break;
2969 default:
2970 assert(0);
2971 }
2972
2973 check_msacsr_cause(env, GETPC());
2974
2975 msa_move_v(pwd, pwx);
2976 }
2977
2978 void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2979 uint32_t ws)
2980 {
2981 wr_t wx, *pwx = &wx;
2982 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2983 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2984 uint32_t i;
2985
2986 clear_msacsr_cause(env);
2987
2988 switch (df) {
2989 case DF_WORD:
2990 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2991 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32);
2992 }
2993 break;
2994 case DF_DOUBLE:
2995 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2996 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64);
2997 }
2998 break;
2999 default:
3000 assert(0);
3001 }
3002
3003 check_msacsr_cause(env, GETPC());
3004
3005 msa_move_v(pwd, pwx);
3006 }
3007
3008 void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3009 uint32_t ws)
3010 {
3011 wr_t wx, *pwx = &wx;
3012 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3013 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3014 uint32_t i;
3015
3016 clear_msacsr_cause(env);
3017
3018 switch (df) {
3019 case DF_WORD:
3020 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3021 MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32);
3022 }
3023 break;
3024 case DF_DOUBLE:
3025 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3026 MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64);
3027 }
3028 break;
3029 default:
3030 assert(0);
3031 }
3032
3033 check_msacsr_cause(env, GETPC());
3034
3035 msa_move_v(pwd, pwx);
3036 }
3037
3038 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
3039 do { \
3040 float_status *status = &env->active_tc.msa_fp_status; \
3041 int c; \
3042 \
3043 set_float_exception_flags(0, status); \
3044 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
3045 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
3046 float ## BITS ## _is_quiet_nan(DEST) ? \
3047 0 : RECIPROCAL_INEXACT, \
3048 IS_DENORMAL(DEST, BITS)); \
3049 \
3050 if (get_enabled_exceptions(env, c)) { \
3051 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
3052 } \
3053 } while (0)
3054
3055 void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3056 uint32_t ws)
3057 {
3058 wr_t wx, *pwx = &wx;
3059 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3060 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3061 uint32_t i;
3062
3063 clear_msacsr_cause(env);
3064
3065 switch (df) {
3066 case DF_WORD:
3067 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3068 MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i],
3069 &env->active_tc.msa_fp_status), 32);
3070 }
3071 break;
3072 case DF_DOUBLE:
3073 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3074 MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i],
3075 &env->active_tc.msa_fp_status), 64);
3076 }
3077 break;
3078 default:
3079 assert(0);
3080 }
3081
3082 check_msacsr_cause(env, GETPC());
3083
3084 msa_move_v(pwd, pwx);
3085 }
3086
3087 void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3088 uint32_t ws)
3089 {
3090 wr_t wx, *pwx = &wx;
3091 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3092 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3093 uint32_t i;
3094
3095 clear_msacsr_cause(env);
3096
3097 switch (df) {
3098 case DF_WORD:
3099 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3100 MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32);
3101 }
3102 break;
3103 case DF_DOUBLE:
3104 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3105 MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64);
3106 }
3107 break;
3108 default:
3109 assert(0);
3110 }
3111
3112 check_msacsr_cause(env, GETPC());
3113
3114 msa_move_v(pwd, pwx);
3115 }
3116
3117 void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3118 uint32_t ws)
3119 {
3120 wr_t wx, *pwx = &wx;
3121 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3122 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3123 uint32_t i;
3124
3125 clear_msacsr_cause(env);
3126
3127 switch (df) {
3128 case DF_WORD:
3129 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3130 MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32);
3131 }
3132 break;
3133 case DF_DOUBLE:
3134 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3135 MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64);
3136 }
3137 break;
3138 default:
3139 assert(0);
3140 }
3141
3142 check_msacsr_cause(env, GETPC());
3143
3144 msa_move_v(pwd, pwx);
3145 }
3146
3147 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
3148 do { \
3149 float_status *status = &env->active_tc.msa_fp_status; \
3150 int c; \
3151 \
3152 set_float_exception_flags(0, status); \
3153 set_float_rounding_mode(float_round_down, status); \
3154 DEST = float ## BITS ## _ ## log2(ARG, status); \
3155 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
3156 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
3157 MSACSR_RM_MASK) >> MSACSR_RM], \
3158 status); \
3159 \
3160 set_float_exception_flags(get_float_exception_flags(status) & \
3161 (~float_flag_inexact), \
3162 status); \
3163 \
3164 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3165 \
3166 if (get_enabled_exceptions(env, c)) { \
3167 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
3168 } \
3169 } while (0)
3170
3171 void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3172 uint32_t ws)
3173 {
3174 wr_t wx, *pwx = &wx;
3175 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3176 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3177 uint32_t i;
3178
3179 clear_msacsr_cause(env);
3180
3181 switch (df) {
3182 case DF_WORD:
3183 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3184 MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32);
3185 }
3186 break;
3187 case DF_DOUBLE:
3188 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3189 MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64);
3190 }
3191 break;
3192 default:
3193 assert(0);
3194 }
3195
3196 check_msacsr_cause(env, GETPC());
3197
3198 msa_move_v(pwd, pwx);
3199 }
3200
3201 void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3202 uint32_t ws)
3203 {
3204 wr_t wx, *pwx = &wx;
3205 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3206 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3207 uint32_t i;
3208
3209 clear_msacsr_cause(env);
3210
3211 switch (df) {
3212 case DF_WORD:
3213 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3214 /* Half precision floats come in two formats: standard
3215 IEEE and "ARM" format. The latter gains extra exponent
3216 range by omitting the NaN/Inf encodings. */
3217 flag ieee = 1;
3218
3219 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
3220 }
3221 break;
3222 case DF_DOUBLE:
3223 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3224 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64);
3225 }
3226 break;
3227 default:
3228 assert(0);
3229 }
3230
3231 check_msacsr_cause(env, GETPC());
3232 msa_move_v(pwd, pwx);
3233 }
3234
3235 void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3236 uint32_t ws)
3237 {
3238 wr_t wx, *pwx = &wx;
3239 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3240 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3241 uint32_t i;
3242
3243 clear_msacsr_cause(env);
3244
3245 switch (df) {
3246 case DF_WORD:
3247 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3248 /* Half precision floats come in two formats: standard
3249 IEEE and "ARM" format. The latter gains extra exponent
3250 range by omitting the NaN/Inf encodings. */
3251 flag ieee = 1;
3252
3253 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
3254 }
3255 break;
3256 case DF_DOUBLE:
3257 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3258 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64);
3259 }
3260 break;
3261 default:
3262 assert(0);
3263 }
3264
3265 check_msacsr_cause(env, GETPC());
3266 msa_move_v(pwd, pwx);
3267 }
3268
3269 void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3270 uint32_t ws)
3271 {
3272 wr_t wx, *pwx = &wx;
3273 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3274 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3275 uint32_t i;
3276
3277 switch (df) {
3278 case DF_WORD:
3279 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3280 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32);
3281 }
3282 break;
3283 case DF_DOUBLE:
3284 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3285 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64);
3286 }
3287 break;
3288 default:
3289 assert(0);
3290 }
3291
3292 msa_move_v(pwd, pwx);
3293 }
3294
3295 void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3296 uint32_t ws)
3297 {
3298 wr_t wx, *pwx = &wx;
3299 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3300 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3301 uint32_t i;
3302
3303 switch (df) {
3304 case DF_WORD:
3305 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3306 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32);
3307 }
3308 break;
3309 case DF_DOUBLE:
3310 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3311 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64);
3312 }
3313 break;
3314 default:
3315 assert(0);
3316 }
3317
3318 msa_move_v(pwd, pwx);
3319 }
3320
3321 void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3322 uint32_t ws)
3323 {
3324 wr_t wx, *pwx = &wx;
3325 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3326 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3327 uint32_t i;
3328
3329 clear_msacsr_cause(env);
3330
3331 switch (df) {
3332 case DF_WORD:
3333 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3334 MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32);
3335 }
3336 break;
3337 case DF_DOUBLE:
3338 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3339 MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64);
3340 }
3341 break;
3342 default:
3343 assert(0);
3344 }
3345
3346 check_msacsr_cause(env, GETPC());
3347
3348 msa_move_v(pwd, pwx);
3349 }
3350
3351 void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3352 uint32_t ws)
3353 {
3354 wr_t wx, *pwx = &wx;
3355 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3356 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3357 uint32_t i;
3358
3359 clear_msacsr_cause(env);
3360
3361 switch (df) {
3362 case DF_WORD:
3363 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3364 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32);
3365 }
3366 break;
3367 case DF_DOUBLE:
3368 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3369 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64);
3370 }
3371 break;
3372 default:
3373 assert(0);
3374 }
3375
3376 check_msacsr_cause(env, GETPC());
3377
3378 msa_move_v(pwd, pwx);
3379 }
3380
3381 #define float32_from_int32 int32_to_float32
3382 #define float32_from_uint32 uint32_to_float32
3383
3384 #define float64_from_int64 int64_to_float64
3385 #define float64_from_uint64 uint64_to_float64
3386
3387 void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3388 uint32_t ws)
3389 {
3390 wr_t wx, *pwx = &wx;
3391 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3392 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3393 uint32_t i;
3394
3395 clear_msacsr_cause(env);
3396
3397 switch (df) {
3398 case DF_WORD:
3399 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3400 MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32);
3401 }
3402 break;
3403 case DF_DOUBLE:
3404 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3405 MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64);
3406 }
3407 break;
3408 default:
3409 assert(0);
3410 }
3411
3412 check_msacsr_cause(env, GETPC());
3413
3414 msa_move_v(pwd, pwx);
3415 }
3416
3417 void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3418 uint32_t ws)
3419 {
3420 wr_t wx, *pwx = &wx;
3421 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3422 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3423 uint32_t i;
3424
3425 clear_msacsr_cause(env);
3426
3427 switch (df) {
3428 case DF_WORD:
3429 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3430 MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32);
3431 }
3432 break;
3433 case DF_DOUBLE:
3434 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3435 MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64);
3436 }
3437 break;
3438 default:
3439 assert(0);
3440 }
3441
3442 check_msacsr_cause(env, GETPC());
3443
3444 msa_move_v(pwd, pwx);
3445 }
AR7 emulation for QEMU