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ps2: prevent changing irq state on save and load
[qemu/ar7.git] / hw / i2c / aspeed_i2c.c
bloba2dfa827604fd4800d47386c765730174a1f9cde
1 /*
2 * ARM Aspeed I2C controller
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "qemu/log.h"
24 #include "hw/i2c/aspeed_i2c.h"
25
26 /* I2C Global Register */
27
28 #define I2C_CTRL_STATUS 0x00 /* Device Interrupt Status */
29 #define I2C_CTRL_ASSIGN 0x08 /* Device Interrupt Target
30 Assignment */
31
32 /* I2C Device (Bus) Register */
33
34 #define I2CD_FUN_CTRL_REG 0x00 /* I2CD Function Control */
35 #define I2CD_BUFF_SEL_MASK (0x7 << 20)
36 #define I2CD_BUFF_SEL(x) (x << 20)
37 #define I2CD_M_SDA_LOCK_EN (0x1 << 16)
38 #define I2CD_MULTI_MASTER_DIS (0x1 << 15)
39 #define I2CD_M_SCL_DRIVE_EN (0x1 << 14)
40 #define I2CD_MSB_STS (0x1 << 9)
41 #define I2CD_SDA_DRIVE_1T_EN (0x1 << 8)
42 #define I2CD_M_SDA_DRIVE_1T_EN (0x1 << 7)
43 #define I2CD_M_HIGH_SPEED_EN (0x1 << 6)
44 #define I2CD_DEF_ADDR_EN (0x1 << 5)
45 #define I2CD_DEF_ALERT_EN (0x1 << 4)
46 #define I2CD_DEF_ARP_EN (0x1 << 3)
47 #define I2CD_DEF_GCALL_EN (0x1 << 2)
48 #define I2CD_SLAVE_EN (0x1 << 1)
49 #define I2CD_MASTER_EN (0x1)
50
51 #define I2CD_AC_TIMING_REG1 0x04 /* Clock and AC Timing Control #1 */
52 #define I2CD_AC_TIMING_REG2 0x08 /* Clock and AC Timing Control #1 */
53 #define I2CD_INTR_CTRL_REG 0x0c /* I2CD Interrupt Control */
54 #define I2CD_INTR_STS_REG 0x10 /* I2CD Interrupt Status */
55
56 #define I2CD_INTR_SLAVE_ADDR_MATCH (0x1 << 31) /* 0: addr1 1: addr2 */
57 #define I2CD_INTR_SLAVE_ADDR_RX_PENDING (0x1 << 30)
58 /* bits[19-16] Reserved */
59
60 /* All bits below are cleared by writing 1 */
61 #define I2CD_INTR_SLAVE_INACTIVE_TIMEOUT (0x1 << 15)
62 #define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)
63 #define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)
64 #define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only */
65 #define I2CD_INTR_SMBUS_ARP_ADDR (0x1 << 11) /* Removed */
66 #define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */
67 #define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */
68 #define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */
69 #define I2CD_INTR_SLAVE_ADDR_RX_MATCH (0x1 << 7) /* use RX_DONE */
70 #define I2CD_INTR_SCL_TIMEOUT (0x1 << 6)
71 #define I2CD_INTR_ABNORMAL (0x1 << 5)
72 #define I2CD_INTR_NORMAL_STOP (0x1 << 4)
73 #define I2CD_INTR_ARBIT_LOSS (0x1 << 3)
74 #define I2CD_INTR_RX_DONE (0x1 << 2)
75 #define I2CD_INTR_TX_NAK (0x1 << 1)
76 #define I2CD_INTR_TX_ACK (0x1 << 0)
77
78 #define I2CD_CMD_REG 0x14 /* I2CD Command/Status */
79 #define I2CD_SDA_OE (0x1 << 28)
80 #define I2CD_SDA_O (0x1 << 27)
81 #define I2CD_SCL_OE (0x1 << 26)
82 #define I2CD_SCL_O (0x1 << 25)
83 #define I2CD_TX_TIMING (0x1 << 24)
84 #define I2CD_TX_STATUS (0x1 << 23)
85
86 #define I2CD_TX_STATE_SHIFT 19 /* Tx State Machine */
87 #define I2CD_TX_STATE_MASK 0xf
88 #define I2CD_IDLE 0x0
89 #define I2CD_MACTIVE 0x8
90 #define I2CD_MSTART 0x9
91 #define I2CD_MSTARTR 0xa
92 #define I2CD_MSTOP 0xb
93 #define I2CD_MTXD 0xc
94 #define I2CD_MRXACK 0xd
95 #define I2CD_MRXD 0xe
96 #define I2CD_MTXACK 0xf
97 #define I2CD_SWAIT 0x1
98 #define I2CD_SRXD 0x4
99 #define I2CD_STXACK 0x5
100 #define I2CD_STXD 0x6
101 #define I2CD_SRXACK 0x7
102 #define I2CD_RECOVER 0x3
103
104 #define I2CD_SCL_LINE_STS (0x1 << 18)
105 #define I2CD_SDA_LINE_STS (0x1 << 17)
106 #define I2CD_BUS_BUSY_STS (0x1 << 16)
107 #define I2CD_SDA_OE_OUT_DIR (0x1 << 15)
108 #define I2CD_SDA_O_OUT_DIR (0x1 << 14)
109 #define I2CD_SCL_OE_OUT_DIR (0x1 << 13)
110 #define I2CD_SCL_O_OUT_DIR (0x1 << 12)
111 #define I2CD_BUS_RECOVER_CMD_EN (0x1 << 11)
112 #define I2CD_S_ALT_EN (0x1 << 10)
113 #define I2CD_RX_DMA_ENABLE (0x1 << 9)
114 #define I2CD_TX_DMA_ENABLE (0x1 << 8)
115
116 /* Command Bit */
117 #define I2CD_M_STOP_CMD (0x1 << 5)
118 #define I2CD_M_S_RX_CMD_LAST (0x1 << 4)
119 #define I2CD_M_RX_CMD (0x1 << 3)
120 #define I2CD_S_TX_CMD (0x1 << 2)
121 #define I2CD_M_TX_CMD (0x1 << 1)
122 #define I2CD_M_START_CMD (0x1)
123
124 #define I2CD_DEV_ADDR_REG 0x18 /* Slave Device Address */
125 #define I2CD_BUF_CTRL_REG 0x1c /* Pool Buffer Control */
126 #define I2CD_BYTE_BUF_REG 0x20 /* Transmit/Receive Byte Buffer */
127 #define I2CD_BYTE_BUF_TX_SHIFT 0
128 #define I2CD_BYTE_BUF_TX_MASK 0xff
129 #define I2CD_BYTE_BUF_RX_SHIFT 8
130 #define I2CD_BYTE_BUF_RX_MASK 0xff
131
132
133 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
134 {
135 return bus->ctrl & I2CD_MASTER_EN;
136 }
137
138 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
139 {
140 return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN);
141 }
142
143 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus)
144 {
145 bus->intr_status &= bus->intr_ctrl;
146 if (bus->intr_status) {
147 bus->controller->intr_status |= 1 << bus->id;
148 qemu_irq_raise(bus->controller->irq);
149 }
150 }
151
152 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
153 unsigned size)
154 {
155 AspeedI2CBus *bus = opaque;
156
157 switch (offset) {
158 case I2CD_FUN_CTRL_REG:
159 return bus->ctrl;
160 case I2CD_AC_TIMING_REG1:
161 return bus->timing[0];
162 case I2CD_AC_TIMING_REG2:
163 return bus->timing[1];
164 case I2CD_INTR_CTRL_REG:
165 return bus->intr_ctrl;
166 case I2CD_INTR_STS_REG:
167 return bus->intr_status;
168 case I2CD_BYTE_BUF_REG:
169 return bus->buf;
170 case I2CD_CMD_REG:
171 return bus->cmd | (i2c_bus_busy(bus->bus) << 16);
172 default:
173 qemu_log_mask(LOG_GUEST_ERROR,
174 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
175 return -1;
176 }
177 }
178
179 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)
180 {
181 bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT);
182 bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT;
183 }
184
185 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
186 {
187 return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;
188 }
189
190 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus)
191 {
192 int ret;
193
194 aspeed_i2c_set_state(bus, I2CD_MRXD);
195 ret = i2c_recv(bus->bus);
196 if (ret < 0) {
197 qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
198 ret = 0xff;
199 } else {
200 bus->intr_status |= I2CD_INTR_RX_DONE;
201 }
202 bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
203 if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
204 i2c_nack(bus->bus);
205 }
206 bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
207 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
208 }
209
210 /*
211 * The state machine needs some refinement. It is only used to track
212 * invalid STOP commands for the moment.
213 */
214 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
215 {
216 bus->cmd &= ~0xFFFF;
217 bus->cmd |= value & 0xFFFF;
218
219 if (bus->cmd & I2CD_M_START_CMD) {
220 uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
221 I2CD_MSTARTR : I2CD_MSTART;
222
223 aspeed_i2c_set_state(bus, state);
224
225 if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),
226 extract32(bus->buf, 0, 1))) {
227 bus->intr_status |= I2CD_INTR_TX_NAK;
228 } else {
229 bus->intr_status |= I2CD_INTR_TX_ACK;
230 }
231
232 /* START command is also a TX command, as the slave address is
233 * sent on the bus */
234 bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD);
235
236 /* No slave found */
237 if (!i2c_bus_busy(bus->bus)) {
238 return;
239 }
240 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
241 }
242
243 if (bus->cmd & I2CD_M_TX_CMD) {
244 aspeed_i2c_set_state(bus, I2CD_MTXD);
245 if (i2c_send(bus->bus, bus->buf)) {
246 bus->intr_status |= (I2CD_INTR_TX_NAK);
247 i2c_end_transfer(bus->bus);
248 } else {
249 bus->intr_status |= I2CD_INTR_TX_ACK;
250 }
251 bus->cmd &= ~I2CD_M_TX_CMD;
252 aspeed_i2c_set_state(bus, I2CD_MACTIVE);
253 }
254
255 if ((bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) &&
256 !(bus->intr_status & I2CD_INTR_RX_DONE)) {
257 aspeed_i2c_handle_rx_cmd(bus);
258 }
259
260 if (bus->cmd & I2CD_M_STOP_CMD) {
261 if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) {
262 qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__);
263 bus->intr_status |= I2CD_INTR_ABNORMAL;
264 } else {
265 aspeed_i2c_set_state(bus, I2CD_MSTOP);
266 i2c_end_transfer(bus->bus);
267 bus->intr_status |= I2CD_INTR_NORMAL_STOP;
268 }
269 bus->cmd &= ~I2CD_M_STOP_CMD;
270 aspeed_i2c_set_state(bus, I2CD_IDLE);
271 }
272 }
273
274 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
275 uint64_t value, unsigned size)
276 {
277 AspeedI2CBus *bus = opaque;
278 bool handle_rx;
279
280 switch (offset) {
281 case I2CD_FUN_CTRL_REG:
282 if (value & I2CD_SLAVE_EN) {
283 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
284 __func__);
285 break;
286 }
287 bus->ctrl = value & 0x0071C3FF;
288 break;
289 case I2CD_AC_TIMING_REG1:
290 bus->timing[0] = value & 0xFFFFF0F;
291 break;
292 case I2CD_AC_TIMING_REG2:
293 bus->timing[1] = value & 0x7;
294 break;
295 case I2CD_INTR_CTRL_REG:
296 bus->intr_ctrl = value & 0x7FFF;
297 break;
298 case I2CD_INTR_STS_REG:
299 handle_rx = (bus->intr_status & I2CD_INTR_RX_DONE) &&
300 (value & I2CD_INTR_RX_DONE);
301 bus->intr_status &= ~(value & 0x7FFF);
302 if (!bus->intr_status) {
303 bus->controller->intr_status &= ~(1 << bus->id);
304 qemu_irq_lower(bus->controller->irq);
305 }
306 if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) {
307 aspeed_i2c_handle_rx_cmd(bus);
308 aspeed_i2c_bus_raise_interrupt(bus);
309 }
310 break;
311 case I2CD_DEV_ADDR_REG:
312 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
313 __func__);
314 break;
315 case I2CD_BYTE_BUF_REG:
316 bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT;
317 break;
318 case I2CD_CMD_REG:
319 if (!aspeed_i2c_bus_is_enabled(bus)) {
320 break;
321 }
322
323 if (!aspeed_i2c_bus_is_master(bus)) {
324 qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
325 __func__);
326 break;
327 }
328
329 aspeed_i2c_bus_handle_cmd(bus, value);
330 aspeed_i2c_bus_raise_interrupt(bus);
331 break;
332
333 default:
334 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
335 __func__, offset);
336 }
337 }
338
339 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset,
340 unsigned size)
341 {
342 AspeedI2CState *s = opaque;
343
344 switch (offset) {
345 case I2C_CTRL_STATUS:
346 return s->intr_status;
347 default:
348 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
349 __func__, offset);
350 break;
351 }
352
353 return -1;
354 }
355
356 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset,
357 uint64_t value, unsigned size)
358 {
359 switch (offset) {
360 case I2C_CTRL_STATUS:
361 default:
362 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
363 __func__, offset);
364 break;
365 }
366 }
367
368 static const MemoryRegionOps aspeed_i2c_bus_ops = {
369 .read = aspeed_i2c_bus_read,
370 .write = aspeed_i2c_bus_write,
371 .endianness = DEVICE_LITTLE_ENDIAN,
372 };
373
374 static const MemoryRegionOps aspeed_i2c_ctrl_ops = {
375 .read = aspeed_i2c_ctrl_read,
376 .write = aspeed_i2c_ctrl_write,
377 .endianness = DEVICE_LITTLE_ENDIAN,
378 };
379
380 static const VMStateDescription aspeed_i2c_bus_vmstate = {
381 .name = TYPE_ASPEED_I2C,
382 .version_id = 1,
383 .minimum_version_id = 1,
384 .fields = (VMStateField[]) {
385 VMSTATE_UINT8(id, AspeedI2CBus),
386 VMSTATE_UINT32(ctrl, AspeedI2CBus),
387 VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2),
388 VMSTATE_UINT32(intr_ctrl, AspeedI2CBus),
389 VMSTATE_UINT32(intr_status, AspeedI2CBus),
390 VMSTATE_UINT32(cmd, AspeedI2CBus),
391 VMSTATE_UINT32(buf, AspeedI2CBus),
392 VMSTATE_END_OF_LIST()
393 }
394 };
395
396 static const VMStateDescription aspeed_i2c_vmstate = {
397 .name = TYPE_ASPEED_I2C,
398 .version_id = 1,
399 .minimum_version_id = 1,
400 .fields = (VMStateField[]) {
401 VMSTATE_UINT32(intr_status, AspeedI2CState),
402 VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState,
403 ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate,
404 AspeedI2CBus),
405 VMSTATE_END_OF_LIST()
406 }
407 };
408
409 static void aspeed_i2c_reset(DeviceState *dev)
410 {
411 int i;
412 AspeedI2CState *s = ASPEED_I2C(dev);
413
414 s->intr_status = 0;
415
416 for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
417 s->busses[i].intr_ctrl = 0;
418 s->busses[i].intr_status = 0;
419 s->busses[i].cmd = 0;
420 s->busses[i].buf = 0;
421 i2c_end_transfer(s->busses[i].bus);
422 }
423 }
424
425 /*
426 * Address Definitions
427 *
428 * 0x000 ... 0x03F: Global Register
429 * 0x040 ... 0x07F: Device 1
430 * 0x080 ... 0x0BF: Device 2
431 * 0x0C0 ... 0x0FF: Device 3
432 * 0x100 ... 0x13F: Device 4
433 * 0x140 ... 0x17F: Device 5
434 * 0x180 ... 0x1BF: Device 6
435 * 0x1C0 ... 0x1FF: Device 7
436 * 0x200 ... 0x2FF: Buffer Pool (unused in linux driver)
437 * 0x300 ... 0x33F: Device 8
438 * 0x340 ... 0x37F: Device 9
439 * 0x380 ... 0x3BF: Device 10
440 * 0x3C0 ... 0x3FF: Device 11
441 * 0x400 ... 0x43F: Device 12
442 * 0x440 ... 0x47F: Device 13
443 * 0x480 ... 0x4BF: Device 14
444 * 0x800 ... 0xFFF: Buffer Pool (unused in linux driver)
445 */
446 static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
447 {
448 int i;
449 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
450 AspeedI2CState *s = ASPEED_I2C(dev);
451
452 sysbus_init_irq(sbd, &s->irq);
453 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
454 "aspeed.i2c", 0x1000);
455 sysbus_init_mmio(sbd, &s->iomem);
456
457 for (i = 0; i < ASPEED_I2C_NR_BUSSES; i++) {
458 char name[16];
459 int offset = i < 7 ? 1 : 5;
460 snprintf(name, sizeof(name), "aspeed.i2c.%d", i);
461 s->busses[i].controller = s;
462 s->busses[i].id = i;
463 s->busses[i].bus = i2c_init_bus(dev, name);
464 memory_region_init_io(&s->busses[i].mr, OBJECT(dev),
465 &aspeed_i2c_bus_ops, &s->busses[i], name, 0x40);
466 memory_region_add_subregion(&s->iomem, 0x40 * (i + offset),
467 &s->busses[i].mr);
468 }
469 }
470
471 static void aspeed_i2c_class_init(ObjectClass *klass, void *data)
472 {
473 DeviceClass *dc = DEVICE_CLASS(klass);
474
475 dc->vmsd = &aspeed_i2c_vmstate;
476 dc->reset = aspeed_i2c_reset;
477 dc->realize = aspeed_i2c_realize;
478 dc->desc = "Aspeed I2C Controller";
479 }
480
481 static const TypeInfo aspeed_i2c_info = {
482 .name = TYPE_ASPEED_I2C,
483 .parent = TYPE_SYS_BUS_DEVICE,
484 .instance_size = sizeof(AspeedI2CState),
485 .class_init = aspeed_i2c_class_init,
486 };
487
488 static void aspeed_i2c_register_types(void)
489 {
490 type_register_static(&aspeed_i2c_info);
491 }
492
493 type_init(aspeed_i2c_register_types)
494
495
496 I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr)
497 {
498 AspeedI2CState *s = ASPEED_I2C(dev);
499 I2CBus *bus = NULL;
500
501 if (busnr >= 0 && busnr < ASPEED_I2C_NR_BUSSES) {
502 bus = s->busses[busnr].bus;
503 }
504
505 return bus;
506 }
AR7 emulation for QEMU