4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
43 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
45 ARMCPU
*cpu
= ARM_CPU(cs
);
46 CPUARMState
*env
= &cpu
->env
;
52 env
->regs
[15] = value
& ~1;
53 env
->thumb
= value
& 1;
57 static void arm_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
59 ARMCPU
*cpu
= ARM_CPU(cs
);
60 CPUARMState
*env
= &cpu
->env
;
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
69 env
->regs
[15] = tb
->pc
;
73 static bool arm_cpu_has_work(CPUState
*cs
)
75 ARMCPU
*cpu
= ARM_CPU(cs
);
77 return (cpu
->power_state
!= PSCI_OFF
)
78 && cs
->interrupt_request
&
79 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB
);
84 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
87 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
90 entry
->opaque
= opaque
;
92 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
95 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
98 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
101 entry
->opaque
= opaque
;
103 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
106 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo
*ri
= value
;
110 ARMCPU
*cpu
= opaque
;
112 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
117 ri
->resetfn(&cpu
->env
, ri
);
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
126 if (!ri
->fieldoffset
) {
130 if (cpreg_field_is_64bit(ri
)) {
131 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
133 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
137 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
144 ARMCPRegInfo
*ri
= value
;
145 ARMCPU
*cpu
= opaque
;
146 uint64_t oldvalue
, newvalue
;
148 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
152 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
153 cp_reg_reset(key
, value
, opaque
);
154 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
155 assert(oldvalue
== newvalue
);
158 /* CPUClass::reset() */
159 static void arm_cpu_reset(CPUState
*s
)
161 ARMCPU
*cpu
= ARM_CPU(s
);
162 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
163 CPUARMState
*env
= &cpu
->env
;
165 acc
->parent_reset(s
);
167 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
169 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
170 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
172 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
173 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
174 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
175 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
177 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
178 s
->halted
= cpu
->start_powered_off
;
180 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
181 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
184 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
185 /* 64 bit CPUs always start in 64 bit mode */
187 #if defined(CONFIG_USER_ONLY)
188 env
->pstate
= PSTATE_MODE_EL0t
;
189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
190 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
191 /* Enable all PAC keys. */
192 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
193 SCTLR_EnDA
| SCTLR_EnDB
);
194 /* Enable all PAC instructions */
195 env
->cp15
.hcr_el2
|= HCR_API
;
196 env
->cp15
.scr_el3
|= SCR_API
;
197 /* and to the FP/Neon instructions */
198 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
199 /* and to the SVE instructions */
200 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
201 env
->cp15
.cptr_el
[3] |= CPTR_EZ
;
202 /* with maximum vector length */
203 env
->vfp
.zcr_el
[1] = cpu_isar_feature(aa64_sve
, cpu
) ?
204 cpu
->sve_max_vq
- 1 : 0;
205 env
->vfp
.zcr_el
[2] = env
->vfp
.zcr_el
[1];
206 env
->vfp
.zcr_el
[3] = env
->vfp
.zcr_el
[1];
208 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
209 * turning on both here will produce smaller code and otherwise
210 * make no difference to the user-level emulation.
212 env
->cp15
.tcr_el
[1].raw_tcr
= (3ULL << 37);
214 /* Reset into the highest available EL */
215 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
216 env
->pstate
= PSTATE_MODE_EL3h
;
217 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
218 env
->pstate
= PSTATE_MODE_EL2h
;
220 env
->pstate
= PSTATE_MODE_EL1h
;
222 env
->pc
= cpu
->rvbar
;
225 #if defined(CONFIG_USER_ONLY)
226 /* Userspace expects access to cp10 and cp11 for FP/Neon */
227 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
231 #if defined(CONFIG_USER_ONLY)
232 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
233 /* For user mode we must enable access to coprocessors */
234 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
235 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
236 env
->cp15
.c15_cpar
= 3;
237 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
238 env
->cp15
.c15_cpar
= 1;
243 * If the highest available EL is EL2, AArch32 will start in Hyp
244 * mode; otherwise it starts in SVC. Note that if we start in
245 * AArch64 then these values in the uncached_cpsr will be ignored.
247 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
248 !arm_feature(env
, ARM_FEATURE_EL3
)) {
249 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
251 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
253 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
255 if (arm_feature(env
, ARM_FEATURE_M
)) {
256 uint32_t initial_msp
; /* Loaded from 0x0 */
257 uint32_t initial_pc
; /* Loaded from 0x4 */
261 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
262 env
->v7m
.secure
= true;
264 /* This bit resets to 0 if security is supported, but 1 if
265 * it is not. The bit is not present in v7M, but we set it
266 * here so we can avoid having to make checks on it conditional
267 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
269 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
271 * Set NSACR to indicate "NS access permitted to everything";
272 * this avoids having to have all the tests of it being
273 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
274 * v8.1M the guest-visible value of NSACR in a CPU without the
275 * Security Extension is 0xcff.
277 env
->v7m
.nsacr
= 0xcff;
280 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
281 * that it resets to 1, so QEMU always does that rather than making
282 * it dependent on CPU model. In v8M it is RES1.
284 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
285 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
286 if (arm_feature(env
, ARM_FEATURE_V8
)) {
287 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
288 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
289 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
291 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
292 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
293 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
296 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
297 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
298 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
299 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
301 /* Unlike A/R profile, M profile defines the reset LR value */
302 env
->regs
[14] = 0xffffffff;
304 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
306 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
307 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
308 rom
= rom_ptr(vecbase
, 8);
310 /* Address zero is covered by ROM which hasn't yet been
311 * copied into physical memory.
313 initial_msp
= ldl_p(rom
);
314 initial_pc
= ldl_p(rom
+ 4);
316 /* Address zero not covered by a ROM blob, or the ROM blob
317 * is in non-modifiable memory and this is a second reset after
318 * it got copied into memory. In the latter case, rom_ptr
319 * will return a NULL pointer and we should use ldl_phys instead.
321 initial_msp
= ldl_phys(s
->as
, vecbase
);
322 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
325 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
326 env
->regs
[15] = initial_pc
& ~1;
327 env
->thumb
= initial_pc
& 1;
330 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
331 * executing as AArch32 then check if highvecs are enabled and
332 * adjust the PC accordingly.
334 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
335 env
->regs
[15] = 0xFFFF0000;
338 /* M profile requires that reset clears the exclusive monitor;
339 * A profile does not, but clearing it makes more sense than having it
340 * set with an exclusive access on address zero.
342 arm_clear_exclusive(env
);
344 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
347 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
348 if (cpu
->pmsav7_dregion
> 0) {
349 if (arm_feature(env
, ARM_FEATURE_V8
)) {
350 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
351 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
352 * cpu
->pmsav7_dregion
);
353 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
354 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
355 * cpu
->pmsav7_dregion
);
356 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
357 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
358 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
359 * cpu
->pmsav7_dregion
);
360 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
361 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
362 * cpu
->pmsav7_dregion
);
364 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
365 memset(env
->pmsav7
.drbar
, 0,
366 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
367 memset(env
->pmsav7
.drsr
, 0,
368 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
369 memset(env
->pmsav7
.dracr
, 0,
370 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
373 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
374 env
->pmsav7
.rnr
[M_REG_S
] = 0;
375 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
376 env
->pmsav8
.mair0
[M_REG_S
] = 0;
377 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
378 env
->pmsav8
.mair1
[M_REG_S
] = 0;
381 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
382 if (cpu
->sau_sregion
> 0) {
383 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
384 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
387 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
388 * the Cortex-M33 does.
393 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
394 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
395 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
396 set_float_detect_tininess(float_tininess_before_rounding
,
397 &env
->vfp
.fp_status
);
398 set_float_detect_tininess(float_tininess_before_rounding
,
399 &env
->vfp
.standard_fp_status
);
400 set_float_detect_tininess(float_tininess_before_rounding
,
401 &env
->vfp
.fp_status_f16
);
402 #ifndef CONFIG_USER_ONLY
404 kvm_arm_reset_vcpu(cpu
);
408 hw_breakpoint_update_all(cpu
);
409 hw_watchpoint_update_all(cpu
);
410 arm_rebuild_hflags(env
);
413 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
414 unsigned int target_el
,
415 unsigned int cur_el
, bool secure
,
418 CPUARMState
*env
= cs
->env_ptr
;
419 bool pstate_unmasked
;
420 bool unmasked
= false;
423 * Don't take exceptions if they target a lower EL.
424 * This check should catch any exceptions that would not be taken
427 if (cur_el
> target_el
) {
433 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
437 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
441 if (secure
|| !(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
442 /* VFIQs are only taken when hypervized and non-secure. */
445 return !(env
->daif
& PSTATE_F
);
447 if (secure
|| !(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
448 /* VIRQs are only taken when hypervized and non-secure. */
451 return !(env
->daif
& PSTATE_I
);
453 g_assert_not_reached();
457 * Use the target EL, current execution state and SCR/HCR settings to
458 * determine whether the corresponding CPSR bit is used to mask the
461 if ((target_el
> cur_el
) && (target_el
!= 1)) {
462 /* Exceptions targeting a higher EL may not be maskable */
463 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
465 * 64-bit masking rules are simple: exceptions to EL3
466 * can't be masked, and exceptions to EL2 can only be
467 * masked from Secure state. The HCR and SCR settings
468 * don't affect the masking logic, only the interrupt routing.
470 if (target_el
== 3 || !secure
) {
475 * The old 32-bit-only environment has a more complicated
476 * masking setup. HCR and SCR bits not only affect interrupt
477 * routing but also change the behaviour of masking.
484 * If FIQs are routed to EL3 or EL2 then there are cases where
485 * we override the CPSR.F in determining if the exception is
486 * masked or not. If neither of these are set then we fall back
487 * to the CPSR.F setting otherwise we further assess the state
490 hcr
= hcr_el2
& HCR_FMO
;
491 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
494 * When EL3 is 32-bit, the SCR.FW bit controls whether the
495 * CPSR.F bit masks FIQ interrupts when taken in non-secure
496 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
497 * when non-secure but only when FIQs are only routed to EL3.
499 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
503 * When EL3 execution state is 32-bit, if HCR.IMO is set then
504 * we may override the CPSR.I masking when in non-secure state.
505 * The SCR.IRQ setting has already been taken into consideration
506 * when setting the target EL, so it does not have a further
509 hcr
= hcr_el2
& HCR_IMO
;
513 g_assert_not_reached();
516 if ((scr
|| hcr
) && !secure
) {
523 * The PSTATE bits only mask the interrupt if we have not overriden the
526 return unmasked
|| pstate_unmasked
;
529 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
531 CPUClass
*cc
= CPU_GET_CLASS(cs
);
532 CPUARMState
*env
= cs
->env_ptr
;
533 uint32_t cur_el
= arm_current_el(env
);
534 bool secure
= arm_is_secure(env
);
535 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
539 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
541 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
543 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
544 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
545 cur_el
, secure
, hcr_el2
)) {
549 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
551 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
552 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
553 cur_el
, secure
, hcr_el2
)) {
557 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
558 excp_idx
= EXCP_VIRQ
;
560 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
561 cur_el
, secure
, hcr_el2
)) {
565 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
566 excp_idx
= EXCP_VFIQ
;
568 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
569 cur_el
, secure
, hcr_el2
)) {
576 cs
->exception_index
= excp_idx
;
577 env
->exception
.target_el
= target_el
;
578 cc
->do_interrupt(cs
);
582 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
583 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
585 CPUClass
*cc
= CPU_GET_CLASS(cs
);
586 ARMCPU
*cpu
= ARM_CPU(cs
);
587 CPUARMState
*env
= &cpu
->env
;
590 /* ARMv7-M interrupt masking works differently than -A or -R.
591 * There is no FIQ/IRQ distinction. Instead of I and F bits
592 * masking FIQ and IRQ interrupts, an exception is taken only
593 * if it is higher priority than the current execution priority
594 * (which depends on state like BASEPRI, FAULTMASK and the
595 * currently active exception).
597 if (interrupt_request
& CPU_INTERRUPT_HARD
598 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
599 cs
->exception_index
= EXCP_IRQ
;
600 cc
->do_interrupt(cs
);
607 void arm_cpu_update_virq(ARMCPU
*cpu
)
610 * Update the interrupt level for VIRQ, which is the logical OR of
611 * the HCR_EL2.VI bit and the input line level from the GIC.
613 CPUARMState
*env
= &cpu
->env
;
614 CPUState
*cs
= CPU(cpu
);
616 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
617 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
619 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
621 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
623 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
628 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
631 * Update the interrupt level for VFIQ, which is the logical OR of
632 * the HCR_EL2.VF bit and the input line level from the GIC.
634 CPUARMState
*env
= &cpu
->env
;
635 CPUState
*cs
= CPU(cpu
);
637 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
638 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
640 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
642 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
644 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
649 #ifndef CONFIG_USER_ONLY
650 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
652 ARMCPU
*cpu
= opaque
;
653 CPUARMState
*env
= &cpu
->env
;
654 CPUState
*cs
= CPU(cpu
);
655 static const int mask
[] = {
656 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
657 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
658 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
659 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
663 env
->irq_line_state
|= mask
[irq
];
665 env
->irq_line_state
&= ~mask
[irq
];
670 assert(arm_feature(env
, ARM_FEATURE_EL2
));
671 arm_cpu_update_virq(cpu
);
674 assert(arm_feature(env
, ARM_FEATURE_EL2
));
675 arm_cpu_update_vfiq(cpu
);
680 cpu_interrupt(cs
, mask
[irq
]);
682 cpu_reset_interrupt(cs
, mask
[irq
]);
686 g_assert_not_reached();
690 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
693 ARMCPU
*cpu
= opaque
;
694 CPUARMState
*env
= &cpu
->env
;
695 CPUState
*cs
= CPU(cpu
);
696 uint32_t linestate_bit
;
701 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
702 linestate_bit
= CPU_INTERRUPT_HARD
;
705 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
706 linestate_bit
= CPU_INTERRUPT_FIQ
;
709 g_assert_not_reached();
713 env
->irq_line_state
|= linestate_bit
;
715 env
->irq_line_state
&= ~linestate_bit
;
717 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
721 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
723 ARMCPU
*cpu
= ARM_CPU(cs
);
724 CPUARMState
*env
= &cpu
->env
;
726 cpu_synchronize_state(cs
);
727 return arm_cpu_data_is_big_endian(env
);
732 static inline void set_feature(CPUARMState
*env
, int feature
)
734 env
->features
|= 1ULL << feature
;
737 static inline void unset_feature(CPUARMState
*env
, int feature
)
739 env
->features
&= ~(1ULL << feature
);
743 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
745 return print_insn_arm(pc
| 1, info
);
748 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
750 ARMCPU
*ac
= ARM_CPU(cpu
);
751 CPUARMState
*env
= &ac
->env
;
755 /* We might not be compiled with the A64 disassembler
756 * because it needs a C++ compiler. Leave print_insn
757 * unset in this case to use the caller default behaviour.
759 #if defined(CONFIG_ARM_A64_DIS)
760 info
->print_insn
= print_insn_arm_a64
;
762 info
->cap_arch
= CS_ARCH_ARM64
;
763 info
->cap_insn_unit
= 4;
764 info
->cap_insn_split
= 4;
768 info
->print_insn
= print_insn_thumb1
;
769 info
->cap_insn_unit
= 2;
770 info
->cap_insn_split
= 4;
771 cap_mode
= CS_MODE_THUMB
;
773 info
->print_insn
= print_insn_arm
;
774 info
->cap_insn_unit
= 4;
775 info
->cap_insn_split
= 4;
776 cap_mode
= CS_MODE_ARM
;
778 if (arm_feature(env
, ARM_FEATURE_V8
)) {
779 cap_mode
|= CS_MODE_V8
;
781 if (arm_feature(env
, ARM_FEATURE_M
)) {
782 cap_mode
|= CS_MODE_MCLASS
;
784 info
->cap_arch
= CS_ARCH_ARM
;
785 info
->cap_mode
= cap_mode
;
788 sctlr_b
= arm_sctlr_b(env
);
789 if (bswap_code(sctlr_b
)) {
790 #ifdef TARGET_WORDS_BIGENDIAN
791 info
->endian
= BFD_ENDIAN_LITTLE
;
793 info
->endian
= BFD_ENDIAN_BIG
;
796 info
->flags
&= ~INSN_ARM_BE32
;
797 #ifndef CONFIG_USER_ONLY
799 info
->flags
|= INSN_ARM_BE32
;
804 #ifdef TARGET_AARCH64
806 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
808 ARMCPU
*cpu
= ARM_CPU(cs
);
809 CPUARMState
*env
= &cpu
->env
;
810 uint32_t psr
= pstate_read(env
);
812 int el
= arm_current_el(env
);
813 const char *ns_status
;
815 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
816 for (i
= 0; i
< 32; i
++) {
818 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
820 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
821 (i
+ 2) % 3 ? " " : "\n");
825 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
826 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
830 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
832 psr
& PSTATE_N
? 'N' : '-',
833 psr
& PSTATE_Z
? 'Z' : '-',
834 psr
& PSTATE_C
? 'C' : '-',
835 psr
& PSTATE_V
? 'V' : '-',
838 psr
& PSTATE_SP
? 'h' : 't');
840 if (cpu_isar_feature(aa64_bti
, cpu
)) {
841 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
843 if (!(flags
& CPU_DUMP_FPU
)) {
844 qemu_fprintf(f
, "\n");
847 if (fp_exception_el(env
, el
) != 0) {
848 qemu_fprintf(f
, " FPU disabled\n");
851 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
852 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
854 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
855 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
857 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
859 if (i
== FFR_PRED_NUM
) {
860 qemu_fprintf(f
, "FFR=");
861 /* It's last, so end the line. */
864 qemu_fprintf(f
, "P%02d=", i
);
877 /* More than one quadword per predicate. */
882 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
884 if (j
* 4 + 4 <= zcr_len
+ 1) {
887 digits
= (zcr_len
% 4 + 1) * 4;
889 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
890 env
->vfp
.pregs
[i
].p
[j
],
891 j
? ":" : eol
? "\n" : " ");
895 for (i
= 0; i
< 32; i
++) {
897 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
898 i
, env
->vfp
.zregs
[i
].d
[1],
899 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
900 } else if (zcr_len
== 1) {
901 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
902 ":%016" PRIx64
":%016" PRIx64
"\n",
903 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
904 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
906 for (j
= zcr_len
; j
>= 0; j
--) {
907 bool odd
= (zcr_len
- j
) % 2 != 0;
909 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
912 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
914 qemu_fprintf(f
, " [%x]=", j
);
917 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
918 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
919 env
->vfp
.zregs
[i
].d
[j
* 2],
920 odd
|| j
== 0 ? "\n" : ":");
925 for (i
= 0; i
< 32; i
++) {
926 uint64_t *q
= aa64_vfp_qreg(env
, i
);
927 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
928 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
935 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
937 g_assert_not_reached();
942 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
944 ARMCPU
*cpu
= ARM_CPU(cs
);
945 CPUARMState
*env
= &cpu
->env
;
949 aarch64_cpu_dump_state(cs
, f
, flags
);
953 for (i
= 0; i
< 16; i
++) {
954 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
956 qemu_fprintf(f
, "\n");
958 qemu_fprintf(f
, " ");
962 if (arm_feature(env
, ARM_FEATURE_M
)) {
963 uint32_t xpsr
= xpsr_read(env
);
965 const char *ns_status
= "";
967 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
968 ns_status
= env
->v7m
.secure
? "S " : "NS ";
971 if (xpsr
& XPSR_EXCP
) {
974 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
975 mode
= "unpriv-thread";
977 mode
= "priv-thread";
981 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
983 xpsr
& XPSR_N
? 'N' : '-',
984 xpsr
& XPSR_Z
? 'Z' : '-',
985 xpsr
& XPSR_C
? 'C' : '-',
986 xpsr
& XPSR_V
? 'V' : '-',
987 xpsr
& XPSR_T
? 'T' : 'A',
991 uint32_t psr
= cpsr_read(env
);
992 const char *ns_status
= "";
994 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
995 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
996 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
999 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1001 psr
& CPSR_N
? 'N' : '-',
1002 psr
& CPSR_Z
? 'Z' : '-',
1003 psr
& CPSR_C
? 'C' : '-',
1004 psr
& CPSR_V
? 'V' : '-',
1005 psr
& CPSR_T
? 'T' : 'A',
1007 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1010 if (flags
& CPU_DUMP_FPU
) {
1012 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
1015 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
1018 for (i
= 0; i
< numvfpregs
; i
++) {
1019 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1020 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1022 i
* 2 + 1, (uint32_t)(v
>> 32),
1025 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1029 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
1031 uint32_t Aff1
= idx
/ clustersz
;
1032 uint32_t Aff0
= idx
% clustersz
;
1033 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1036 static void cpreg_hashtable_data_destroy(gpointer data
)
1039 * Destroy function for cpu->cp_regs hashtable data entries.
1040 * We must free the name string because it was g_strdup()ed in
1041 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1042 * from r->name because we know we definitely allocated it.
1044 ARMCPRegInfo
*r
= data
;
1046 g_free((void *)r
->name
);
1050 static void arm_cpu_initfn(Object
*obj
)
1052 ARMCPU
*cpu
= ARM_CPU(obj
);
1054 cpu_set_cpustate_pointers(cpu
);
1055 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
1056 g_free
, cpreg_hashtable_data_destroy
);
1058 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1059 QLIST_INIT(&cpu
->el_change_hooks
);
1061 #ifndef CONFIG_USER_ONLY
1062 /* Our inbound IRQ and FIQ lines */
1063 if (kvm_enabled()) {
1064 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1065 * the same interface as non-KVM CPUs.
1067 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1069 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1072 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1073 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1075 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1076 "gicv3-maintenance-interrupt", 1);
1077 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1078 "pmu-interrupt", 1);
1081 /* DTB consumers generally don't in fact care what the 'compatible'
1082 * string is, so always provide some string and trust that a hypothetical
1083 * picky DTB consumer will also provide a helpful error message.
1085 cpu
->dtb_compatible
= "qemu,unknown";
1086 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
1087 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1089 if (tcg_enabled()) {
1090 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
1094 static Property arm_cpu_gt_cntfrq_property
=
1095 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1096 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1098 static Property arm_cpu_reset_cbar_property
=
1099 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1101 static Property arm_cpu_reset_hivecs_property
=
1102 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1104 static Property arm_cpu_rvbar_property
=
1105 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
1107 static Property arm_cpu_has_el2_property
=
1108 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1110 static Property arm_cpu_has_el3_property
=
1111 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1113 static Property arm_cpu_cfgend_property
=
1114 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1116 static Property arm_cpu_has_vfp_property
=
1117 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1119 static Property arm_cpu_has_neon_property
=
1120 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1122 static Property arm_cpu_has_dsp_property
=
1123 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1125 static Property arm_cpu_has_mpu_property
=
1126 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1128 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1129 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1130 * the right value for that particular CPU type, and we don't want
1131 * to override that with an incorrect constant value.
1133 static Property arm_cpu_pmsav7_dregion_property
=
1134 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1136 qdev_prop_uint32
, uint32_t);
1138 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1140 ARMCPU
*cpu
= ARM_CPU(obj
);
1142 return cpu
->has_pmu
;
1145 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1147 ARMCPU
*cpu
= ARM_CPU(obj
);
1150 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu
))) {
1151 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1154 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1156 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1158 cpu
->has_pmu
= value
;
1161 static void arm_get_init_svtor(Object
*obj
, Visitor
*v
, const char *name
,
1162 void *opaque
, Error
**errp
)
1164 ARMCPU
*cpu
= ARM_CPU(obj
);
1166 visit_type_uint32(v
, name
, &cpu
->init_svtor
, errp
);
1169 static void arm_set_init_svtor(Object
*obj
, Visitor
*v
, const char *name
,
1170 void *opaque
, Error
**errp
)
1172 ARMCPU
*cpu
= ARM_CPU(obj
);
1174 visit_type_uint32(v
, name
, &cpu
->init_svtor
, errp
);
1177 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1180 * The exact approach to calculating guest ticks is:
1182 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1183 * NANOSECONDS_PER_SECOND);
1185 * We don't do that. Rather we intentionally use integer division
1186 * truncation below and in the caller for the conversion of host monotonic
1187 * time to guest ticks to provide the exact inverse for the semantics of
1188 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1189 * it loses precision when representing frequencies where
1190 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1191 * provide an exact inverse leads to scheduling timers with negative
1192 * periods, which in turn leads to sticky behaviour in the guest.
1194 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1195 * cannot become zero.
1197 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1198 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1201 void arm_cpu_post_init(Object
*obj
)
1203 ARMCPU
*cpu
= ARM_CPU(obj
);
1205 /* M profile implies PMSA. We have to do this here rather than
1206 * in realize with the other feature-implication checks because
1207 * we look at the PMSA bit to see if we should add some properties.
1209 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1210 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1212 /* Similarly for the VFP feature bits */
1213 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP4
)) {
1214 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1216 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP3
)) {
1217 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1220 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1221 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1222 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1225 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1226 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1229 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1230 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
);
1233 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1234 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1235 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1237 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1239 #ifndef CONFIG_USER_ONLY
1240 object_property_add_link(obj
, "secure-memory",
1242 (Object
**)&cpu
->secure_memory
,
1243 qdev_prop_allow_set_link_before_realize
,
1244 OBJ_PROP_LINK_STRONG
,
1249 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1250 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1253 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1254 cpu
->has_pmu
= true;
1255 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
,
1260 * Allow user to turn off VFP and Neon support, but only for TCG --
1261 * KVM does not currently allow us to lie to the guest about its
1262 * ID/feature registers, so the guest always sees what the host has.
1264 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1265 cpu
->has_vfp
= true;
1266 if (!kvm_enabled()) {
1267 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1271 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1272 cpu
->has_neon
= true;
1273 if (!kvm_enabled()) {
1274 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1278 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1279 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1280 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1283 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1284 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1285 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1286 qdev_property_add_static(DEVICE(obj
),
1287 &arm_cpu_pmsav7_dregion_property
);
1291 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1292 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1293 qdev_prop_allow_set_link_before_realize
,
1294 OBJ_PROP_LINK_STRONG
,
1297 * M profile: initial value of the Secure VTOR. We can't just use
1298 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1299 * the property to be set after realize.
1301 object_property_add(obj
, "init-svtor", "uint32",
1302 arm_get_init_svtor
, arm_set_init_svtor
,
1303 NULL
, NULL
, &error_abort
);
1306 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1308 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1309 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1313 static void arm_cpu_finalizefn(Object
*obj
)
1315 ARMCPU
*cpu
= ARM_CPU(obj
);
1316 ARMELChangeHook
*hook
, *next
;
1318 g_hash_table_destroy(cpu
->cp_regs
);
1320 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1321 QLIST_REMOVE(hook
, node
);
1324 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1325 QLIST_REMOVE(hook
, node
);
1328 #ifndef CONFIG_USER_ONLY
1329 if (cpu
->pmu_timer
) {
1330 timer_del(cpu
->pmu_timer
);
1331 timer_deinit(cpu
->pmu_timer
);
1332 timer_free(cpu
->pmu_timer
);
1337 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1339 Error
*local_err
= NULL
;
1341 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1342 arm_cpu_sve_finalize(cpu
, &local_err
);
1343 if (local_err
!= NULL
) {
1344 error_propagate(errp
, local_err
);
1350 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1352 CPUState
*cs
= CPU(dev
);
1353 ARMCPU
*cpu
= ARM_CPU(dev
);
1354 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1355 CPUARMState
*env
= &cpu
->env
;
1357 Error
*local_err
= NULL
;
1358 bool no_aa32
= false;
1360 /* If we needed to query the host kernel for the CPU features
1361 * then it's possible that might have failed in the initfn, but
1362 * this is the first point where we can report it.
1364 if (cpu
->host_cpu_probe_failed
) {
1365 if (!kvm_enabled()) {
1366 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
1368 error_setg(errp
, "Failed to retrieve host CPU features");
1373 #ifndef CONFIG_USER_ONLY
1374 /* The NVIC and M-profile CPU are two halves of a single piece of
1375 * hardware; trying to use one without the other is a command line
1376 * error and will result in segfaults if not caught here.
1378 if (arm_feature(env
, ARM_FEATURE_M
)) {
1380 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1385 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1393 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1394 if (!cpu
->gt_cntfrq_hz
) {
1395 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1399 scale
= gt_cntfrq_period_ns(cpu
);
1401 scale
= GTIMER_SCALE
;
1404 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1405 arm_gt_ptimer_cb
, cpu
);
1406 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1407 arm_gt_vtimer_cb
, cpu
);
1408 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1409 arm_gt_htimer_cb
, cpu
);
1410 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1411 arm_gt_stimer_cb
, cpu
);
1412 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1413 arm_gt_hvtimer_cb
, cpu
);
1417 cpu_exec_realizefn(cs
, &local_err
);
1418 if (local_err
!= NULL
) {
1419 error_propagate(errp
, local_err
);
1423 arm_cpu_finalize_features(cpu
, &local_err
);
1424 if (local_err
!= NULL
) {
1425 error_propagate(errp
, local_err
);
1429 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1430 cpu
->has_vfp
!= cpu
->has_neon
) {
1432 * This is an architectural requirement for AArch64; AArch32 is
1433 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1436 "AArch64 CPUs must have both VFP and Neon or neither");
1440 if (!cpu
->has_vfp
) {
1444 unset_feature(env
, ARM_FEATURE_VFP
);
1445 unset_feature(env
, ARM_FEATURE_VFP3
);
1446 unset_feature(env
, ARM_FEATURE_VFP4
);
1448 t
= cpu
->isar
.id_aa64isar1
;
1449 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1450 cpu
->isar
.id_aa64isar1
= t
;
1452 t
= cpu
->isar
.id_aa64pfr0
;
1453 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1454 cpu
->isar
.id_aa64pfr0
= t
;
1456 u
= cpu
->isar
.id_isar6
;
1457 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1458 cpu
->isar
.id_isar6
= u
;
1460 u
= cpu
->isar
.mvfr0
;
1461 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1462 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1463 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1464 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1465 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1466 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1467 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1468 cpu
->isar
.mvfr0
= u
;
1470 u
= cpu
->isar
.mvfr1
;
1471 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1472 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1473 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1474 cpu
->isar
.mvfr1
= u
;
1476 u
= cpu
->isar
.mvfr2
;
1477 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1478 cpu
->isar
.mvfr2
= u
;
1481 if (!cpu
->has_neon
) {
1485 unset_feature(env
, ARM_FEATURE_NEON
);
1487 t
= cpu
->isar
.id_aa64isar0
;
1488 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1489 cpu
->isar
.id_aa64isar0
= t
;
1491 t
= cpu
->isar
.id_aa64isar1
;
1492 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1493 cpu
->isar
.id_aa64isar1
= t
;
1495 t
= cpu
->isar
.id_aa64pfr0
;
1496 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1497 cpu
->isar
.id_aa64pfr0
= t
;
1499 u
= cpu
->isar
.id_isar5
;
1500 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1501 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1502 cpu
->isar
.id_isar5
= u
;
1504 u
= cpu
->isar
.id_isar6
;
1505 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1506 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1507 cpu
->isar
.id_isar6
= u
;
1509 u
= cpu
->isar
.mvfr1
;
1510 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1511 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1512 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1513 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1514 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1515 cpu
->isar
.mvfr1
= u
;
1517 u
= cpu
->isar
.mvfr2
;
1518 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1519 cpu
->isar
.mvfr2
= u
;
1522 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1526 t
= cpu
->isar
.id_aa64isar0
;
1527 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1528 cpu
->isar
.id_aa64isar0
= t
;
1530 t
= cpu
->isar
.id_aa64isar1
;
1531 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1532 cpu
->isar
.id_aa64isar1
= t
;
1534 u
= cpu
->isar
.mvfr0
;
1535 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1536 cpu
->isar
.mvfr0
= u
;
1539 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1542 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1544 u
= cpu
->isar
.id_isar1
;
1545 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1546 cpu
->isar
.id_isar1
= u
;
1548 u
= cpu
->isar
.id_isar2
;
1549 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1550 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1551 cpu
->isar
.id_isar2
= u
;
1553 u
= cpu
->isar
.id_isar3
;
1554 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1555 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1556 cpu
->isar
.id_isar3
= u
;
1559 /* Some features automatically imply others: */
1560 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1561 if (arm_feature(env
, ARM_FEATURE_M
)) {
1562 set_feature(env
, ARM_FEATURE_V7
);
1564 set_feature(env
, ARM_FEATURE_V7VE
);
1569 * There exist AArch64 cpus without AArch32 support. When KVM
1570 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1571 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1572 * As a general principle, we also do not make ID register
1573 * consistency checks anywhere unless using TCG, because only
1574 * for TCG would a consistency-check failure be a QEMU bug.
1576 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1577 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1580 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1581 /* v7 Virtualization Extensions. In real hardware this implies
1582 * EL2 and also the presence of the Security Extensions.
1583 * For QEMU, for backwards-compatibility we implement some
1584 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1585 * include the various other features that V7VE implies.
1586 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1587 * Security Extensions is ARM_FEATURE_EL3.
1589 assert(!tcg_enabled() || no_aa32
||
1590 cpu_isar_feature(aa32_arm_div
, cpu
));
1591 set_feature(env
, ARM_FEATURE_LPAE
);
1592 set_feature(env
, ARM_FEATURE_V7
);
1594 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1595 set_feature(env
, ARM_FEATURE_VAPA
);
1596 set_feature(env
, ARM_FEATURE_THUMB2
);
1597 set_feature(env
, ARM_FEATURE_MPIDR
);
1598 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1599 set_feature(env
, ARM_FEATURE_V6K
);
1601 set_feature(env
, ARM_FEATURE_V6
);
1604 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1605 * non-EL3 configs. This is needed by some legacy boards.
1607 set_feature(env
, ARM_FEATURE_VBAR
);
1609 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1610 set_feature(env
, ARM_FEATURE_V6
);
1611 set_feature(env
, ARM_FEATURE_MVFR
);
1613 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1614 set_feature(env
, ARM_FEATURE_V5
);
1615 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1616 assert(!tcg_enabled() || no_aa32
||
1617 cpu_isar_feature(aa32_jazelle
, cpu
));
1618 set_feature(env
, ARM_FEATURE_AUXCR
);
1621 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1622 set_feature(env
, ARM_FEATURE_V4T
);
1624 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1625 set_feature(env
, ARM_FEATURE_V7MP
);
1626 set_feature(env
, ARM_FEATURE_PXN
);
1628 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1629 set_feature(env
, ARM_FEATURE_CBAR
);
1631 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1632 !arm_feature(env
, ARM_FEATURE_M
)) {
1633 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1637 * We rely on no XScale CPU having VFP so we can use the same bits in the
1638 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1640 assert(!(arm_feature(env
, ARM_FEATURE_VFP
) &&
1641 arm_feature(env
, ARM_FEATURE_XSCALE
)));
1643 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1644 !arm_feature(env
, ARM_FEATURE_M
) &&
1645 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1646 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1651 /* For CPUs which might have tiny 1K pages, or which have an
1652 * MPU and might have small region sizes, stick with 1K pages.
1656 if (!set_preferred_target_page_bits(pagebits
)) {
1657 /* This can only ever happen for hotplugging a CPU, or if
1658 * the board code incorrectly creates a CPU which it has
1659 * promised via minimum_page_size that it will not.
1661 error_setg(errp
, "This CPU requires a smaller page size than the "
1666 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1667 * We don't support setting cluster ID ([16..23]) (known as Aff2
1668 * in later ARM ARM versions), or any of the higher affinity level fields,
1669 * so these bits always RAZ.
1671 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1672 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1673 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1676 if (cpu
->reset_hivecs
) {
1677 cpu
->reset_sctlr
|= (1 << 13);
1681 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1682 cpu
->reset_sctlr
|= SCTLR_EE
;
1684 cpu
->reset_sctlr
|= SCTLR_B
;
1688 if (!cpu
->has_el3
) {
1689 /* If the has_el3 CPU property is disabled then we need to disable the
1692 unset_feature(env
, ARM_FEATURE_EL3
);
1694 /* Disable the security extension feature bits in the processor feature
1695 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1697 cpu
->id_pfr1
&= ~0xf0;
1698 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1701 if (!cpu
->has_el2
) {
1702 unset_feature(env
, ARM_FEATURE_EL2
);
1705 if (!cpu
->has_pmu
) {
1706 unset_feature(env
, ARM_FEATURE_PMU
);
1708 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1711 if (!kvm_enabled()) {
1712 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1713 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1716 #ifndef CONFIG_USER_ONLY
1717 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1721 cpu
->isar
.id_aa64dfr0
=
1722 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
1723 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
1728 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1729 /* Disable the hypervisor feature bits in the processor feature
1730 * registers if we don't have EL2. These are id_pfr1[15:12] and
1731 * id_aa64pfr0_el1[11:8].
1733 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1734 cpu
->id_pfr1
&= ~0xf000;
1737 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1738 * to false or by setting pmsav7-dregion to 0.
1740 if (!cpu
->has_mpu
) {
1741 cpu
->pmsav7_dregion
= 0;
1743 if (cpu
->pmsav7_dregion
== 0) {
1744 cpu
->has_mpu
= false;
1747 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1748 arm_feature(env
, ARM_FEATURE_V7
)) {
1749 uint32_t nr
= cpu
->pmsav7_dregion
;
1752 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1757 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1759 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1760 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1761 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1762 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1763 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1766 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1767 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1768 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1773 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1774 uint32_t nr
= cpu
->sau_sregion
;
1777 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1782 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1783 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1787 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1788 set_feature(env
, ARM_FEATURE_VBAR
);
1791 register_cp_regs_for_features(cpu
);
1792 arm_cpu_register_gdb_regs_for_features(cpu
);
1794 init_cpreg_list(cpu
);
1796 #ifndef CONFIG_USER_ONLY
1797 MachineState
*ms
= MACHINE(qdev_get_machine());
1798 unsigned int smp_cpus
= ms
->smp
.cpus
;
1800 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1803 if (!cpu
->secure_memory
) {
1804 cpu
->secure_memory
= cs
->memory
;
1806 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1807 cpu
->secure_memory
);
1811 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1813 /* No core_count specified, default to smp_cpus. */
1814 if (cpu
->core_count
== -1) {
1815 cpu
->core_count
= smp_cpus
;
1822 acc
->parent_realize(dev
, errp
);
1825 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1830 const char *cpunamestr
;
1832 cpuname
= g_strsplit(cpu_model
, ",", 1);
1833 cpunamestr
= cpuname
[0];
1834 #ifdef CONFIG_USER_ONLY
1835 /* For backwards compatibility usermode emulation allows "-cpu any",
1836 * which has the same semantics as "-cpu max".
1838 if (!strcmp(cpunamestr
, "any")) {
1842 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1843 oc
= object_class_by_name(typename
);
1844 g_strfreev(cpuname
);
1846 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1847 object_class_is_abstract(oc
)) {
1853 /* CPU models. These are not needed for the AArch64 linux-user build. */
1854 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1856 static void arm926_initfn(Object
*obj
)
1858 ARMCPU
*cpu
= ARM_CPU(obj
);
1860 cpu
->dtb_compatible
= "arm,arm926";
1861 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1862 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1863 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1864 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1865 cpu
->midr
= 0x41069265;
1866 cpu
->reset_fpsid
= 0x41011090;
1867 cpu
->ctr
= 0x1dd20d2;
1868 cpu
->reset_sctlr
= 0x00090078;
1871 * ARMv5 does not have the ID_ISAR registers, but we can still
1872 * set the field to indicate Jazelle support within QEMU.
1874 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1876 * Similarly, we need to set MVFR0 fields to enable double precision
1877 * and short vector support even though ARMv5 doesn't have this register.
1879 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
1880 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
1883 static void arm946_initfn(Object
*obj
)
1885 ARMCPU
*cpu
= ARM_CPU(obj
);
1887 cpu
->dtb_compatible
= "arm,arm946";
1888 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1889 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1890 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1891 cpu
->midr
= 0x41059461;
1892 cpu
->ctr
= 0x0f004006;
1893 cpu
->reset_sctlr
= 0x00000078;
1896 static void arm1026_initfn(Object
*obj
)
1898 ARMCPU
*cpu
= ARM_CPU(obj
);
1900 cpu
->dtb_compatible
= "arm,arm1026";
1901 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1902 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1903 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
1904 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1905 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1906 cpu
->midr
= 0x4106a262;
1907 cpu
->reset_fpsid
= 0x410110a0;
1908 cpu
->ctr
= 0x1dd20d2;
1909 cpu
->reset_sctlr
= 0x00090078;
1910 cpu
->reset_auxcr
= 1;
1913 * ARMv5 does not have the ID_ISAR registers, but we can still
1914 * set the field to indicate Jazelle support within QEMU.
1916 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1918 * Similarly, we need to set MVFR0 fields to enable double precision
1919 * and short vector support even though ARMv5 doesn't have this register.
1921 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
1922 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
1925 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1926 ARMCPRegInfo ifar
= {
1927 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1929 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
1932 define_one_arm_cp_reg(cpu
, &ifar
);
1936 static void arm1136_r2_initfn(Object
*obj
)
1938 ARMCPU
*cpu
= ARM_CPU(obj
);
1939 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1940 * older core than plain "arm1136". In particular this does not
1941 * have the v6K features.
1942 * These ID register values are correct for 1136 but may be wrong
1943 * for 1136_r2 (in particular r0p2 does not actually implement most
1944 * of the ID registers).
1947 cpu
->dtb_compatible
= "arm,arm1136";
1948 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1949 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1950 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1951 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1952 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1953 cpu
->midr
= 0x4107b362;
1954 cpu
->reset_fpsid
= 0x410120b4;
1955 cpu
->isar
.mvfr0
= 0x11111111;
1956 cpu
->isar
.mvfr1
= 0x00000000;
1957 cpu
->ctr
= 0x1dd20d2;
1958 cpu
->reset_sctlr
= 0x00050078;
1959 cpu
->id_pfr0
= 0x111;
1961 cpu
->isar
.id_dfr0
= 0x2;
1963 cpu
->id_mmfr0
= 0x01130003;
1964 cpu
->id_mmfr1
= 0x10030302;
1965 cpu
->id_mmfr2
= 0x01222110;
1966 cpu
->isar
.id_isar0
= 0x00140011;
1967 cpu
->isar
.id_isar1
= 0x12002111;
1968 cpu
->isar
.id_isar2
= 0x11231111;
1969 cpu
->isar
.id_isar3
= 0x01102131;
1970 cpu
->isar
.id_isar4
= 0x141;
1971 cpu
->reset_auxcr
= 7;
1974 static void arm1136_initfn(Object
*obj
)
1976 ARMCPU
*cpu
= ARM_CPU(obj
);
1978 cpu
->dtb_compatible
= "arm,arm1136";
1979 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1980 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1981 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1982 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1983 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1984 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1985 cpu
->midr
= 0x4117b363;
1986 cpu
->reset_fpsid
= 0x410120b4;
1987 cpu
->isar
.mvfr0
= 0x11111111;
1988 cpu
->isar
.mvfr1
= 0x00000000;
1989 cpu
->ctr
= 0x1dd20d2;
1990 cpu
->reset_sctlr
= 0x00050078;
1991 cpu
->id_pfr0
= 0x111;
1993 cpu
->isar
.id_dfr0
= 0x2;
1995 cpu
->id_mmfr0
= 0x01130003;
1996 cpu
->id_mmfr1
= 0x10030302;
1997 cpu
->id_mmfr2
= 0x01222110;
1998 cpu
->isar
.id_isar0
= 0x00140011;
1999 cpu
->isar
.id_isar1
= 0x12002111;
2000 cpu
->isar
.id_isar2
= 0x11231111;
2001 cpu
->isar
.id_isar3
= 0x01102131;
2002 cpu
->isar
.id_isar4
= 0x141;
2003 cpu
->reset_auxcr
= 7;
2006 static void arm1176_initfn(Object
*obj
)
2008 ARMCPU
*cpu
= ARM_CPU(obj
);
2010 cpu
->dtb_compatible
= "arm,arm1176";
2011 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
2012 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
2013 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
2014 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2015 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
2016 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
2017 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2018 cpu
->midr
= 0x410fb767;
2019 cpu
->reset_fpsid
= 0x410120b5;
2020 cpu
->isar
.mvfr0
= 0x11111111;
2021 cpu
->isar
.mvfr1
= 0x00000000;
2022 cpu
->ctr
= 0x1dd20d2;
2023 cpu
->reset_sctlr
= 0x00050078;
2024 cpu
->id_pfr0
= 0x111;
2025 cpu
->id_pfr1
= 0x11;
2026 cpu
->isar
.id_dfr0
= 0x33;
2028 cpu
->id_mmfr0
= 0x01130003;
2029 cpu
->id_mmfr1
= 0x10030302;
2030 cpu
->id_mmfr2
= 0x01222100;
2031 cpu
->isar
.id_isar0
= 0x0140011;
2032 cpu
->isar
.id_isar1
= 0x12002111;
2033 cpu
->isar
.id_isar2
= 0x11231121;
2034 cpu
->isar
.id_isar3
= 0x01102131;
2035 cpu
->isar
.id_isar4
= 0x01141;
2036 cpu
->reset_auxcr
= 7;
2039 static void arm11mpcore_initfn(Object
*obj
)
2041 ARMCPU
*cpu
= ARM_CPU(obj
);
2043 cpu
->dtb_compatible
= "arm,arm11mpcore";
2044 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
2045 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
2046 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
2047 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
2048 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2049 cpu
->midr
= 0x410fb022;
2050 cpu
->reset_fpsid
= 0x410120b4;
2051 cpu
->isar
.mvfr0
= 0x11111111;
2052 cpu
->isar
.mvfr1
= 0x00000000;
2053 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
2054 cpu
->id_pfr0
= 0x111;
2056 cpu
->isar
.id_dfr0
= 0;
2058 cpu
->id_mmfr0
= 0x01100103;
2059 cpu
->id_mmfr1
= 0x10020302;
2060 cpu
->id_mmfr2
= 0x01222000;
2061 cpu
->isar
.id_isar0
= 0x00100011;
2062 cpu
->isar
.id_isar1
= 0x12002111;
2063 cpu
->isar
.id_isar2
= 0x11221011;
2064 cpu
->isar
.id_isar3
= 0x01102131;
2065 cpu
->isar
.id_isar4
= 0x141;
2066 cpu
->reset_auxcr
= 1;
2069 static void cortex_m0_initfn(Object
*obj
)
2071 ARMCPU
*cpu
= ARM_CPU(obj
);
2072 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
2073 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2075 cpu
->midr
= 0x410cc200;
2078 static void cortex_m3_initfn(Object
*obj
)
2080 ARMCPU
*cpu
= ARM_CPU(obj
);
2081 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2082 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2083 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2084 cpu
->midr
= 0x410fc231;
2085 cpu
->pmsav7_dregion
= 8;
2086 cpu
->id_pfr0
= 0x00000030;
2087 cpu
->id_pfr1
= 0x00000200;
2088 cpu
->isar
.id_dfr0
= 0x00100000;
2089 cpu
->id_afr0
= 0x00000000;
2090 cpu
->id_mmfr0
= 0x00000030;
2091 cpu
->id_mmfr1
= 0x00000000;
2092 cpu
->id_mmfr2
= 0x00000000;
2093 cpu
->id_mmfr3
= 0x00000000;
2094 cpu
->isar
.id_isar0
= 0x01141110;
2095 cpu
->isar
.id_isar1
= 0x02111000;
2096 cpu
->isar
.id_isar2
= 0x21112231;
2097 cpu
->isar
.id_isar3
= 0x01111110;
2098 cpu
->isar
.id_isar4
= 0x01310102;
2099 cpu
->isar
.id_isar5
= 0x00000000;
2100 cpu
->isar
.id_isar6
= 0x00000000;
2103 static void cortex_m4_initfn(Object
*obj
)
2105 ARMCPU
*cpu
= ARM_CPU(obj
);
2107 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2108 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2109 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2110 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2111 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2112 cpu
->midr
= 0x410fc240; /* r0p0 */
2113 cpu
->pmsav7_dregion
= 8;
2114 cpu
->isar
.mvfr0
= 0x10110021;
2115 cpu
->isar
.mvfr1
= 0x11000011;
2116 cpu
->isar
.mvfr2
= 0x00000000;
2117 cpu
->id_pfr0
= 0x00000030;
2118 cpu
->id_pfr1
= 0x00000200;
2119 cpu
->isar
.id_dfr0
= 0x00100000;
2120 cpu
->id_afr0
= 0x00000000;
2121 cpu
->id_mmfr0
= 0x00000030;
2122 cpu
->id_mmfr1
= 0x00000000;
2123 cpu
->id_mmfr2
= 0x00000000;
2124 cpu
->id_mmfr3
= 0x00000000;
2125 cpu
->isar
.id_isar0
= 0x01141110;
2126 cpu
->isar
.id_isar1
= 0x02111000;
2127 cpu
->isar
.id_isar2
= 0x21112231;
2128 cpu
->isar
.id_isar3
= 0x01111110;
2129 cpu
->isar
.id_isar4
= 0x01310102;
2130 cpu
->isar
.id_isar5
= 0x00000000;
2131 cpu
->isar
.id_isar6
= 0x00000000;
2134 static void cortex_m7_initfn(Object
*obj
)
2136 ARMCPU
*cpu
= ARM_CPU(obj
);
2138 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2139 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2140 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2141 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2142 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2143 cpu
->midr
= 0x411fc272; /* r1p2 */
2144 cpu
->pmsav7_dregion
= 8;
2145 cpu
->isar
.mvfr0
= 0x10110221;
2146 cpu
->isar
.mvfr1
= 0x12000011;
2147 cpu
->isar
.mvfr2
= 0x00000040;
2148 cpu
->id_pfr0
= 0x00000030;
2149 cpu
->id_pfr1
= 0x00000200;
2150 cpu
->isar
.id_dfr0
= 0x00100000;
2151 cpu
->id_afr0
= 0x00000000;
2152 cpu
->id_mmfr0
= 0x00100030;
2153 cpu
->id_mmfr1
= 0x00000000;
2154 cpu
->id_mmfr2
= 0x01000000;
2155 cpu
->id_mmfr3
= 0x00000000;
2156 cpu
->isar
.id_isar0
= 0x01101110;
2157 cpu
->isar
.id_isar1
= 0x02112000;
2158 cpu
->isar
.id_isar2
= 0x20232231;
2159 cpu
->isar
.id_isar3
= 0x01111131;
2160 cpu
->isar
.id_isar4
= 0x01310132;
2161 cpu
->isar
.id_isar5
= 0x00000000;
2162 cpu
->isar
.id_isar6
= 0x00000000;
2165 static void cortex_m33_initfn(Object
*obj
)
2167 ARMCPU
*cpu
= ARM_CPU(obj
);
2169 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2170 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2171 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2172 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
2173 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2174 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2175 cpu
->midr
= 0x410fd213; /* r0p3 */
2176 cpu
->pmsav7_dregion
= 16;
2177 cpu
->sau_sregion
= 8;
2178 cpu
->isar
.mvfr0
= 0x10110021;
2179 cpu
->isar
.mvfr1
= 0x11000011;
2180 cpu
->isar
.mvfr2
= 0x00000040;
2181 cpu
->id_pfr0
= 0x00000030;
2182 cpu
->id_pfr1
= 0x00000210;
2183 cpu
->isar
.id_dfr0
= 0x00200000;
2184 cpu
->id_afr0
= 0x00000000;
2185 cpu
->id_mmfr0
= 0x00101F40;
2186 cpu
->id_mmfr1
= 0x00000000;
2187 cpu
->id_mmfr2
= 0x01000000;
2188 cpu
->id_mmfr3
= 0x00000000;
2189 cpu
->isar
.id_isar0
= 0x01101110;
2190 cpu
->isar
.id_isar1
= 0x02212000;
2191 cpu
->isar
.id_isar2
= 0x20232232;
2192 cpu
->isar
.id_isar3
= 0x01111131;
2193 cpu
->isar
.id_isar4
= 0x01310132;
2194 cpu
->isar
.id_isar5
= 0x00000000;
2195 cpu
->isar
.id_isar6
= 0x00000000;
2196 cpu
->clidr
= 0x00000000;
2197 cpu
->ctr
= 0x8000c000;
2200 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
2202 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2203 CPUClass
*cc
= CPU_CLASS(oc
);
2206 #ifndef CONFIG_USER_ONLY
2207 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
2210 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
2213 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
2214 /* Dummy the TCM region regs for the moment */
2215 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2216 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
2217 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2218 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
2219 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
2220 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
2224 static void cortex_r5_initfn(Object
*obj
)
2226 ARMCPU
*cpu
= ARM_CPU(obj
);
2228 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2229 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
2230 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
2231 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2232 cpu
->midr
= 0x411fc153; /* r1p3 */
2233 cpu
->id_pfr0
= 0x0131;
2234 cpu
->id_pfr1
= 0x001;
2235 cpu
->isar
.id_dfr0
= 0x010400;
2237 cpu
->id_mmfr0
= 0x0210030;
2238 cpu
->id_mmfr1
= 0x00000000;
2239 cpu
->id_mmfr2
= 0x01200000;
2240 cpu
->id_mmfr3
= 0x0211;
2241 cpu
->isar
.id_isar0
= 0x02101111;
2242 cpu
->isar
.id_isar1
= 0x13112111;
2243 cpu
->isar
.id_isar2
= 0x21232141;
2244 cpu
->isar
.id_isar3
= 0x01112131;
2245 cpu
->isar
.id_isar4
= 0x0010142;
2246 cpu
->isar
.id_isar5
= 0x0;
2247 cpu
->isar
.id_isar6
= 0x0;
2248 cpu
->mp_is_up
= true;
2249 cpu
->pmsav7_dregion
= 16;
2250 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
2253 static void cortex_r5f_initfn(Object
*obj
)
2255 ARMCPU
*cpu
= ARM_CPU(obj
);
2257 cortex_r5_initfn(obj
);
2258 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2259 cpu
->isar
.mvfr0
= 0x10110221;
2260 cpu
->isar
.mvfr1
= 0x00000011;
2263 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
2264 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
2265 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2266 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2267 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2271 static void cortex_a8_initfn(Object
*obj
)
2273 ARMCPU
*cpu
= ARM_CPU(obj
);
2275 cpu
->dtb_compatible
= "arm,cortex-a8";
2276 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2277 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2278 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2279 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2280 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2281 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2282 cpu
->midr
= 0x410fc080;
2283 cpu
->reset_fpsid
= 0x410330c0;
2284 cpu
->isar
.mvfr0
= 0x11110222;
2285 cpu
->isar
.mvfr1
= 0x00011111;
2286 cpu
->ctr
= 0x82048004;
2287 cpu
->reset_sctlr
= 0x00c50078;
2288 cpu
->id_pfr0
= 0x1031;
2289 cpu
->id_pfr1
= 0x11;
2290 cpu
->isar
.id_dfr0
= 0x400;
2292 cpu
->id_mmfr0
= 0x31100003;
2293 cpu
->id_mmfr1
= 0x20000000;
2294 cpu
->id_mmfr2
= 0x01202000;
2295 cpu
->id_mmfr3
= 0x11;
2296 cpu
->isar
.id_isar0
= 0x00101111;
2297 cpu
->isar
.id_isar1
= 0x12112111;
2298 cpu
->isar
.id_isar2
= 0x21232031;
2299 cpu
->isar
.id_isar3
= 0x11112131;
2300 cpu
->isar
.id_isar4
= 0x00111142;
2301 cpu
->isar
.dbgdidr
= 0x15141000;
2302 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
2303 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
2304 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
2305 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
2306 cpu
->reset_auxcr
= 2;
2307 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
2310 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
2311 /* power_control should be set to maximum latency. Again,
2312 * default to 0 and set by private hook
2314 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2315 .access
= PL1_RW
, .resetvalue
= 0,
2316 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
2317 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
2318 .access
= PL1_RW
, .resetvalue
= 0,
2319 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
2320 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
2321 .access
= PL1_RW
, .resetvalue
= 0,
2322 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
2323 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2324 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2325 /* TLB lockdown control */
2326 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
2327 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
2328 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
2329 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
2330 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
2331 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2332 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
2333 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2334 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
2335 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2339 static void cortex_a9_initfn(Object
*obj
)
2341 ARMCPU
*cpu
= ARM_CPU(obj
);
2343 cpu
->dtb_compatible
= "arm,cortex-a9";
2344 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2345 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2346 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2347 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2348 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2349 /* Note that A9 supports the MP extensions even for
2350 * A9UP and single-core A9MP (which are both different
2351 * and valid configurations; we don't model A9UP).
2353 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
2354 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
2355 cpu
->midr
= 0x410fc090;
2356 cpu
->reset_fpsid
= 0x41033090;
2357 cpu
->isar
.mvfr0
= 0x11110222;
2358 cpu
->isar
.mvfr1
= 0x01111111;
2359 cpu
->ctr
= 0x80038003;
2360 cpu
->reset_sctlr
= 0x00c50078;
2361 cpu
->id_pfr0
= 0x1031;
2362 cpu
->id_pfr1
= 0x11;
2363 cpu
->isar
.id_dfr0
= 0x000;
2365 cpu
->id_mmfr0
= 0x00100103;
2366 cpu
->id_mmfr1
= 0x20000000;
2367 cpu
->id_mmfr2
= 0x01230000;
2368 cpu
->id_mmfr3
= 0x00002111;
2369 cpu
->isar
.id_isar0
= 0x00101111;
2370 cpu
->isar
.id_isar1
= 0x13112111;
2371 cpu
->isar
.id_isar2
= 0x21232041;
2372 cpu
->isar
.id_isar3
= 0x11112131;
2373 cpu
->isar
.id_isar4
= 0x00111142;
2374 cpu
->isar
.dbgdidr
= 0x35141000;
2375 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
2376 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
2377 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
2378 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
2381 #ifndef CONFIG_USER_ONLY
2382 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2384 MachineState
*ms
= MACHINE(qdev_get_machine());
2386 /* Linux wants the number of processors from here.
2387 * Might as well set the interrupt-controller bit too.
2389 return ((ms
->smp
.cpus
- 1) << 24) | (1 << 23);
2393 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
2394 #ifndef CONFIG_USER_ONLY
2395 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2396 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
2397 .writefn
= arm_cp_write_ignore
, },
2399 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
2400 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2404 static void cortex_a7_initfn(Object
*obj
)
2406 ARMCPU
*cpu
= ARM_CPU(obj
);
2408 cpu
->dtb_compatible
= "arm,cortex-a7";
2409 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2410 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2411 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2412 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2413 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2414 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2415 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2416 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2417 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2418 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2419 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
2420 cpu
->midr
= 0x410fc075;
2421 cpu
->reset_fpsid
= 0x41023075;
2422 cpu
->isar
.mvfr0
= 0x10110222;
2423 cpu
->isar
.mvfr1
= 0x11111111;
2424 cpu
->ctr
= 0x84448003;
2425 cpu
->reset_sctlr
= 0x00c50078;
2426 cpu
->id_pfr0
= 0x00001131;
2427 cpu
->id_pfr1
= 0x00011011;
2428 cpu
->isar
.id_dfr0
= 0x02010555;
2429 cpu
->id_afr0
= 0x00000000;
2430 cpu
->id_mmfr0
= 0x10101105;
2431 cpu
->id_mmfr1
= 0x40000000;
2432 cpu
->id_mmfr2
= 0x01240000;
2433 cpu
->id_mmfr3
= 0x02102211;
2434 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2435 * table 4-41 gives 0x02101110, which includes the arm div insns.
2437 cpu
->isar
.id_isar0
= 0x02101110;
2438 cpu
->isar
.id_isar1
= 0x13112111;
2439 cpu
->isar
.id_isar2
= 0x21232041;
2440 cpu
->isar
.id_isar3
= 0x11112131;
2441 cpu
->isar
.id_isar4
= 0x10011142;
2442 cpu
->isar
.dbgdidr
= 0x3515f005;
2443 cpu
->clidr
= 0x0a200023;
2444 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2445 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2446 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2447 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
2450 static void cortex_a15_initfn(Object
*obj
)
2452 ARMCPU
*cpu
= ARM_CPU(obj
);
2454 cpu
->dtb_compatible
= "arm,cortex-a15";
2455 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2456 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2457 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2458 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2459 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2460 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2461 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2462 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2463 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2464 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2465 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
2466 cpu
->midr
= 0x412fc0f1;
2467 cpu
->reset_fpsid
= 0x410430f0;
2468 cpu
->isar
.mvfr0
= 0x10110222;
2469 cpu
->isar
.mvfr1
= 0x11111111;
2470 cpu
->ctr
= 0x8444c004;
2471 cpu
->reset_sctlr
= 0x00c50078;
2472 cpu
->id_pfr0
= 0x00001131;
2473 cpu
->id_pfr1
= 0x00011011;
2474 cpu
->isar
.id_dfr0
= 0x02010555;
2475 cpu
->id_afr0
= 0x00000000;
2476 cpu
->id_mmfr0
= 0x10201105;
2477 cpu
->id_mmfr1
= 0x20000000;
2478 cpu
->id_mmfr2
= 0x01240000;
2479 cpu
->id_mmfr3
= 0x02102211;
2480 cpu
->isar
.id_isar0
= 0x02101110;
2481 cpu
->isar
.id_isar1
= 0x13112111;
2482 cpu
->isar
.id_isar2
= 0x21232041;
2483 cpu
->isar
.id_isar3
= 0x11112131;
2484 cpu
->isar
.id_isar4
= 0x10011142;
2485 cpu
->isar
.dbgdidr
= 0x3515f021;
2486 cpu
->clidr
= 0x0a200023;
2487 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2488 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2489 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2490 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
2493 static void ti925t_initfn(Object
*obj
)
2495 ARMCPU
*cpu
= ARM_CPU(obj
);
2496 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
2497 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
2498 cpu
->midr
= ARM_CPUID_TI925T
;
2499 cpu
->ctr
= 0x5109149;
2500 cpu
->reset_sctlr
= 0x00000070;
2503 static void sa1100_initfn(Object
*obj
)
2505 ARMCPU
*cpu
= ARM_CPU(obj
);
2507 cpu
->dtb_compatible
= "intel,sa1100";
2508 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2509 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2510 cpu
->midr
= 0x4401A11B;
2511 cpu
->reset_sctlr
= 0x00000070;
2514 static void sa1110_initfn(Object
*obj
)
2516 ARMCPU
*cpu
= ARM_CPU(obj
);
2517 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2518 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2519 cpu
->midr
= 0x6901B119;
2520 cpu
->reset_sctlr
= 0x00000070;
2523 static void pxa250_initfn(Object
*obj
)
2525 ARMCPU
*cpu
= ARM_CPU(obj
);
2527 cpu
->dtb_compatible
= "marvell,xscale";
2528 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2529 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2530 cpu
->midr
= 0x69052100;
2531 cpu
->ctr
= 0xd172172;
2532 cpu
->reset_sctlr
= 0x00000078;
2535 static void pxa255_initfn(Object
*obj
)
2537 ARMCPU
*cpu
= ARM_CPU(obj
);
2539 cpu
->dtb_compatible
= "marvell,xscale";
2540 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2541 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2542 cpu
->midr
= 0x69052d00;
2543 cpu
->ctr
= 0xd172172;
2544 cpu
->reset_sctlr
= 0x00000078;
2547 static void pxa260_initfn(Object
*obj
)
2549 ARMCPU
*cpu
= ARM_CPU(obj
);
2551 cpu
->dtb_compatible
= "marvell,xscale";
2552 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2553 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2554 cpu
->midr
= 0x69052903;
2555 cpu
->ctr
= 0xd172172;
2556 cpu
->reset_sctlr
= 0x00000078;
2559 static void pxa261_initfn(Object
*obj
)
2561 ARMCPU
*cpu
= ARM_CPU(obj
);
2563 cpu
->dtb_compatible
= "marvell,xscale";
2564 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2565 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2566 cpu
->midr
= 0x69052d05;
2567 cpu
->ctr
= 0xd172172;
2568 cpu
->reset_sctlr
= 0x00000078;
2571 static void pxa262_initfn(Object
*obj
)
2573 ARMCPU
*cpu
= ARM_CPU(obj
);
2575 cpu
->dtb_compatible
= "marvell,xscale";
2576 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2577 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2578 cpu
->midr
= 0x69052d06;
2579 cpu
->ctr
= 0xd172172;
2580 cpu
->reset_sctlr
= 0x00000078;
2583 static void pxa270a0_initfn(Object
*obj
)
2585 ARMCPU
*cpu
= ARM_CPU(obj
);
2587 cpu
->dtb_compatible
= "marvell,xscale";
2588 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2589 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2590 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2591 cpu
->midr
= 0x69054110;
2592 cpu
->ctr
= 0xd172172;
2593 cpu
->reset_sctlr
= 0x00000078;
2596 static void pxa270a1_initfn(Object
*obj
)
2598 ARMCPU
*cpu
= ARM_CPU(obj
);
2600 cpu
->dtb_compatible
= "marvell,xscale";
2601 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2602 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2603 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2604 cpu
->midr
= 0x69054111;
2605 cpu
->ctr
= 0xd172172;
2606 cpu
->reset_sctlr
= 0x00000078;
2609 static void pxa270b0_initfn(Object
*obj
)
2611 ARMCPU
*cpu
= ARM_CPU(obj
);
2613 cpu
->dtb_compatible
= "marvell,xscale";
2614 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2615 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2616 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2617 cpu
->midr
= 0x69054112;
2618 cpu
->ctr
= 0xd172172;
2619 cpu
->reset_sctlr
= 0x00000078;
2622 static void pxa270b1_initfn(Object
*obj
)
2624 ARMCPU
*cpu
= ARM_CPU(obj
);
2626 cpu
->dtb_compatible
= "marvell,xscale";
2627 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2628 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2629 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2630 cpu
->midr
= 0x69054113;
2631 cpu
->ctr
= 0xd172172;
2632 cpu
->reset_sctlr
= 0x00000078;
2635 static void pxa270c0_initfn(Object
*obj
)
2637 ARMCPU
*cpu
= ARM_CPU(obj
);
2639 cpu
->dtb_compatible
= "marvell,xscale";
2640 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2641 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2642 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2643 cpu
->midr
= 0x69054114;
2644 cpu
->ctr
= 0xd172172;
2645 cpu
->reset_sctlr
= 0x00000078;
2648 static void pxa270c5_initfn(Object
*obj
)
2650 ARMCPU
*cpu
= ARM_CPU(obj
);
2652 cpu
->dtb_compatible
= "marvell,xscale";
2653 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2654 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2655 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2656 cpu
->midr
= 0x69054117;
2657 cpu
->ctr
= 0xd172172;
2658 cpu
->reset_sctlr
= 0x00000078;
2661 #ifndef TARGET_AARCH64
2662 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2663 * otherwise, a CPU with as many features enabled as our emulation supports.
2664 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2665 * this only needs to handle 32 bits.
2667 static void arm_max_initfn(Object
*obj
)
2669 ARMCPU
*cpu
= ARM_CPU(obj
);
2671 if (kvm_enabled()) {
2672 kvm_arm_set_cpu_features_from_host(cpu
);
2673 kvm_arm_add_vcpu_properties(obj
);
2675 cortex_a15_initfn(obj
);
2677 /* old-style VFP short-vector support */
2678 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
2680 #ifdef CONFIG_USER_ONLY
2681 /* We don't set these in system emulation mode for the moment,
2682 * since we don't correctly set (all of) the ID registers to
2685 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2689 t
= cpu
->isar
.id_isar5
;
2690 t
= FIELD_DP32(t
, ID_ISAR5
, AES
, 2);
2691 t
= FIELD_DP32(t
, ID_ISAR5
, SHA1
, 1);
2692 t
= FIELD_DP32(t
, ID_ISAR5
, SHA2
, 1);
2693 t
= FIELD_DP32(t
, ID_ISAR5
, CRC32
, 1);
2694 t
= FIELD_DP32(t
, ID_ISAR5
, RDM
, 1);
2695 t
= FIELD_DP32(t
, ID_ISAR5
, VCMA
, 1);
2696 cpu
->isar
.id_isar5
= t
;
2698 t
= cpu
->isar
.id_isar6
;
2699 t
= FIELD_DP32(t
, ID_ISAR6
, JSCVT
, 1);
2700 t
= FIELD_DP32(t
, ID_ISAR6
, DP
, 1);
2701 t
= FIELD_DP32(t
, ID_ISAR6
, FHM
, 1);
2702 t
= FIELD_DP32(t
, ID_ISAR6
, SB
, 1);
2703 t
= FIELD_DP32(t
, ID_ISAR6
, SPECRES
, 1);
2704 cpu
->isar
.id_isar6
= t
;
2706 t
= cpu
->isar
.mvfr1
;
2707 t
= FIELD_DP32(t
, MVFR1
, FPHP
, 2); /* v8.0 FP support */
2708 cpu
->isar
.mvfr1
= t
;
2710 t
= cpu
->isar
.mvfr2
;
2711 t
= FIELD_DP32(t
, MVFR2
, SIMDMISC
, 3); /* SIMD MaxNum */
2712 t
= FIELD_DP32(t
, MVFR2
, FPMISC
, 4); /* FP MaxNum */
2713 cpu
->isar
.mvfr2
= t
;
2716 t
= FIELD_DP32(t
, ID_MMFR3
, PAN
, 2); /* ATS1E1 */
2720 t
= FIELD_DP32(t
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
2728 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2732 void (*initfn
)(Object
*obj
);
2733 void (*class_init
)(ObjectClass
*oc
, void *data
);
2736 static const ARMCPUInfo arm_cpus
[] = {
2737 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2738 { .name
= "arm926", .initfn
= arm926_initfn
},
2739 { .name
= "arm946", .initfn
= arm946_initfn
},
2740 { .name
= "arm1026", .initfn
= arm1026_initfn
},
2741 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2742 * older core than plain "arm1136". In particular this does not
2743 * have the v6K features.
2745 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
2746 { .name
= "arm1136", .initfn
= arm1136_initfn
},
2747 { .name
= "arm1176", .initfn
= arm1176_initfn
},
2748 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
2749 { .name
= "cortex-m0", .initfn
= cortex_m0_initfn
,
2750 .class_init
= arm_v7m_class_init
},
2751 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
2752 .class_init
= arm_v7m_class_init
},
2753 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
2754 .class_init
= arm_v7m_class_init
},
2755 { .name
= "cortex-m7", .initfn
= cortex_m7_initfn
,
2756 .class_init
= arm_v7m_class_init
},
2757 { .name
= "cortex-m33", .initfn
= cortex_m33_initfn
,
2758 .class_init
= arm_v7m_class_init
},
2759 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
2760 { .name
= "cortex-r5f", .initfn
= cortex_r5f_initfn
},
2761 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
2762 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
2763 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
2764 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
2765 { .name
= "ti925t", .initfn
= ti925t_initfn
},
2766 { .name
= "sa1100", .initfn
= sa1100_initfn
},
2767 { .name
= "sa1110", .initfn
= sa1110_initfn
},
2768 { .name
= "pxa250", .initfn
= pxa250_initfn
},
2769 { .name
= "pxa255", .initfn
= pxa255_initfn
},
2770 { .name
= "pxa260", .initfn
= pxa260_initfn
},
2771 { .name
= "pxa261", .initfn
= pxa261_initfn
},
2772 { .name
= "pxa262", .initfn
= pxa262_initfn
},
2773 /* "pxa270" is an alias for "pxa270-a0" */
2774 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
2775 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
2776 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
2777 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
2778 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
2779 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
2780 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
2781 #ifndef TARGET_AARCH64
2782 { .name
= "max", .initfn
= arm_max_initfn
},
2784 #ifdef CONFIG_USER_ONLY
2785 { .name
= "any", .initfn
= arm_max_initfn
},
2791 static Property arm_cpu_properties
[] = {
2792 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
2793 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
2794 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
2795 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2796 mp_affinity
, ARM64_AFFINITY_INVALID
),
2797 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2798 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2799 DEFINE_PROP_END_OF_LIST()
2802 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2804 ARMCPU
*cpu
= ARM_CPU(cs
);
2805 CPUARMState
*env
= &cpu
->env
;
2807 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2808 return g_strdup("iwmmxt");
2810 return g_strdup("arm");
2813 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2815 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2816 CPUClass
*cc
= CPU_CLASS(acc
);
2817 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2819 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2820 &acc
->parent_realize
);
2822 device_class_set_props(dc
, arm_cpu_properties
);
2823 cpu_class_set_parent_reset(cc
, arm_cpu_reset
, &acc
->parent_reset
);
2825 cc
->class_by_name
= arm_cpu_class_by_name
;
2826 cc
->has_work
= arm_cpu_has_work
;
2827 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
2828 cc
->dump_state
= arm_cpu_dump_state
;
2829 cc
->set_pc
= arm_cpu_set_pc
;
2830 cc
->synchronize_from_tb
= arm_cpu_synchronize_from_tb
;
2831 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2832 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2833 #ifndef CONFIG_USER_ONLY
2834 cc
->do_interrupt
= arm_cpu_do_interrupt
;
2835 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
2836 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
2837 cc
->vmsd
= &vmstate_arm_cpu
;
2838 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
2839 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
2840 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
2842 cc
->gdb_num_core_regs
= 26;
2843 cc
->gdb_core_xml_file
= "arm-core.xml";
2844 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2845 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2846 cc
->gdb_stop_before_watchpoint
= true;
2847 cc
->disas_set_info
= arm_disas_set_info
;
2849 cc
->tcg_initialize
= arm_translate_init
;
2850 cc
->tlb_fill
= arm_cpu_tlb_fill
;
2851 cc
->debug_excp_handler
= arm_debug_excp_handler
;
2852 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
2853 #if !defined(CONFIG_USER_ONLY)
2854 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
2855 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
2856 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
2857 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2862 static void arm_host_initfn(Object
*obj
)
2864 ARMCPU
*cpu
= ARM_CPU(obj
);
2866 kvm_arm_set_cpu_features_from_host(cpu
);
2867 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
2868 aarch64_add_sve_properties(obj
);
2870 kvm_arm_add_vcpu_properties(obj
);
2871 arm_cpu_post_init(obj
);
2874 static const TypeInfo host_arm_cpu_type_info
= {
2875 .name
= TYPE_ARM_HOST_CPU
,
2876 #ifdef TARGET_AARCH64
2877 .parent
= TYPE_AARCH64_CPU
,
2879 .parent
= TYPE_ARM_CPU
,
2881 .instance_init
= arm_host_initfn
,
2886 static void arm_cpu_instance_init(Object
*obj
)
2888 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2890 acc
->info
->initfn(obj
);
2891 arm_cpu_post_init(obj
);
2894 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2896 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2901 static void cpu_register(const ARMCPUInfo
*info
)
2903 TypeInfo type_info
= {
2904 .parent
= TYPE_ARM_CPU
,
2905 .instance_size
= sizeof(ARMCPU
),
2906 .instance_init
= arm_cpu_instance_init
,
2907 .class_size
= sizeof(ARMCPUClass
),
2908 .class_init
= info
->class_init
?: cpu_register_class_init
,
2909 .class_data
= (void *)info
,
2912 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2913 type_register(&type_info
);
2914 g_free((void *)type_info
.name
);
2917 static const TypeInfo arm_cpu_type_info
= {
2918 .name
= TYPE_ARM_CPU
,
2920 .instance_size
= sizeof(ARMCPU
),
2921 .instance_init
= arm_cpu_initfn
,
2922 .instance_finalize
= arm_cpu_finalizefn
,
2924 .class_size
= sizeof(ARMCPUClass
),
2925 .class_init
= arm_cpu_class_init
,
2928 static const TypeInfo idau_interface_type_info
= {
2929 .name
= TYPE_IDAU_INTERFACE
,
2930 .parent
= TYPE_INTERFACE
,
2931 .class_size
= sizeof(IDAUInterfaceClass
),
2934 static void arm_cpu_register_types(void)
2936 const ARMCPUInfo
*info
= arm_cpus
;
2938 type_register_static(&arm_cpu_type_info
);
2939 type_register_static(&idau_interface_type_info
);
2941 while (info
->name
) {
2947 type_register_static(&host_arm_cpu_type_info
);
2951 type_init(arm_cpu_register_types
)