2 * QEMU i8255x (PRO100) emulation
4 * Copyright (c) 2006-2007 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
36 #if defined(TARGET_I386)
37 # warning "PXE boot still not working!"
40 #include <stddef.h> /* offsetof */
45 #include "eeprom93xx.h"
47 /* Common declarations for all PCI devices. */
49 #define PCI_CONFIG_8(offset, value) \
50 (pci_conf[offset] = (value))
51 #define PCI_CONFIG_16(offset, value) \
52 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
53 #define PCI_CONFIG_32(offset, value) \
54 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
58 /* Debug EEPRO100 card. */
59 //~ #define DEBUG_EEPRO100
62 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
64 #define logout(fmt, ...) ((void)0)
67 /* Set flags to 0 to disable debug output. */
68 #define INT 1 /* interrupt related actions */
69 #define MDI 1 /* mdi related actions */
72 #define EEPROM 1 /* eeprom related actions */
74 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
76 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
78 #define MAX_ETH_FRAME_SIZE 1514
80 /* This driver supports several different devices which are declared here. */
81 #define i82550 0x82550
82 #define i82551 0x82551
83 #define i82557A 0x82557a
84 #define i82557B 0x82557b
85 #define i82557C 0x82557c
86 #define i82558A 0x82558a
87 #define i82558B 0x82558b
88 #define i82559A 0x82559a
89 #define i82559B 0x82559b
90 #define i82559C 0x82559c
91 #define i82559ER 0x82559e
92 #define i82562 0x82562
94 /* Use 64 word EEPROM. TODO: could be a runtime option. */
95 #define EEPROM_SIZE 64
97 #define PCI_MEM_SIZE (4 * KiB)
98 #define PCI_IO_SIZE 64
99 #define PCI_FLASH_SIZE (128 * KiB)
101 #define BIT(n) (1 << (n))
102 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
104 /* The SCB accepts the following controls for the Tx and Rx units: */
105 #define CU_NOP 0x0000 /* No operation. */
106 #define CU_START 0x0010 /* CU start. */
107 #define CU_RESUME 0x0020 /* CU resume. */
108 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
109 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
110 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
111 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
112 #define CU_SRESUME 0x00a0 /* CU static resume. */
114 #define RU_NOP 0x0000
115 #define RX_START 0x0001
116 #define RX_RESUME 0x0002
117 #define RX_ABORT 0x0004
118 #define RX_ADDR_LOAD 0x0006
119 #define RX_RESUMENR 0x0007
120 #define INT_MASK 0x0100
121 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
123 /* Offsets to the various registers.
124 All accesses need not be longword aligned. */
125 enum speedo_offsets
{
128 SCBCmd
= 2, /* Rx/Command Unit command and status. */
130 SCBPointer
= 4, /* General purpose pointer. */
131 SCBPort
= 8, /* Misc. commands and operands. */
132 SCBflash
= 12, SCBeeprom
= 14, /* EEPROM and flash memory control. */
133 SCBCtrlMDI
= 16, /* MDI interface control. */
134 SCBEarlyRx
= 20, /* Early receive byte count. */
138 /* A speedo3 transmit buffer descriptor with two buffers... */
142 uint32_t link
; /* void * */
143 uint32_t tx_desc_addr
; /* transmit buffer decsriptor array address. */
144 uint16_t tcb_bytes
; /* transmit command block byte count (in lower 14 bits */
145 uint8_t tx_threshold
; /* transmit threshold */
146 uint8_t tbd_count
; /* TBD number */
147 //~ /* This constitutes two "TBD" entries: hdr and data */
148 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
149 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
150 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
151 //~ int32_t tx_buf_size1; /* Length of Tx data. */
154 /* Receive frame descriptor. */
158 uint32_t link
; /* struct RxFD * */
159 uint32_t rx_buf_addr
; /* void * */
162 char packet
[MAX_ETH_FRAME_SIZE
+ 4];
166 uint32_t tx_good_frames
, tx_max_collisions
, tx_late_collisions
,
167 tx_underruns
, tx_lost_crs
, tx_deferred
, tx_single_collisions
,
168 tx_multiple_collisions
, tx_total_collisions
;
169 uint32_t rx_good_frames
, rx_crc_errors
, rx_alignment_errors
,
170 rx_resource_errors
, rx_overrun_errors
, rx_cdt_errors
,
171 rx_short_frame_errors
;
172 uint32_t fc_xmt_pause
, fc_rcv_pause
, fc_rcv_unsupported
;
173 uint16_t xmt_tco_frames
, rcv_tco_frames
;
194 uint8_t mult
[8]; /* multicast mask array */
197 uint8_t scb_stat
; /* SCB stat/ack byte */
198 uint8_t int_stat
; /* PCI interrupt status */
199 /* region must not be saved by nic_save. */
200 uint32_t region
[3]; /* PCI region addresses */
204 uint32_t device
; /* device variant */
206 /* (cu_base + cu_offset) address the next command block in the command block list. */
207 uint32_t cu_base
; /* CU base address */
208 uint32_t cu_offset
; /* CU address offset */
209 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
210 uint32_t ru_base
; /* RU base address */
211 uint32_t ru_offset
; /* RU address offset */
212 uint32_t statsaddr
; /* pointer to eepro100_stats_t */
213 eepro100_stats_t statistics
; /* statistical counters */
218 /* Configuration bytes. */
219 uint8_t configuration
[22];
221 /* Data in mem is always in the byte order of the controller (le). */
222 uint8_t mem
[PCI_MEM_SIZE
];
225 /* Default values for MDI (PHY) registers */
226 static const uint16_t eepro100_mdi_default
[] = {
227 /* MDI Registers 0 - 6, 7 */
228 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
229 /* MDI Registers 8 - 15 */
230 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
231 /* MDI Registers 16 - 31 */
232 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
233 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
236 /* Readonly mask for MDI (PHY) registers */
237 static const uint16_t eepro100_mdi_mask
[] = {
238 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
239 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
240 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
241 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
244 #define POLYNOMIAL 0x04c11db6
248 static int compute_mcast_idx(const uint8_t * ep
)
255 for (i
= 0; i
< 6; i
++) {
257 for (j
= 0; j
< 8; j
++) {
258 carry
= ((crc
& 0x80000000L
) ? 1 : 0) ^ (b
& 0x01);
262 crc
= ((crc
^ POLYNOMIAL
) | carry
);
269 #if defined(DEBUG_EEPRO100)
270 static const char *nic_dump(const uint8_t * buf
, unsigned size
)
272 static char dump
[3 * 16 + 1];
278 p
+= sprintf(p
, " %02x", *buf
++);
282 #endif /* DEBUG_EEPRO100 */
285 stat_ack_not_ours
= 0x00,
286 stat_ack_sw_gen
= 0x04,
288 stat_ack_cu_idle
= 0x20,
289 stat_ack_frame_rx
= 0x40,
290 stat_ack_cu_cmd_done
= 0x80,
291 stat_ack_not_present
= 0xFF,
292 stat_ack_rx
= (stat_ack_sw_gen
| stat_ack_rnr
| stat_ack_frame_rx
),
293 stat_ack_tx
= (stat_ack_cu_idle
| stat_ack_cu_cmd_done
),
296 static void disable_interrupt(EEPRO100State
* s
)
299 TRACE(INT
, logout("interrupt disabled\n"));
300 qemu_irq_lower(s
->dev
.irq
[0]);
305 static void enable_interrupt(EEPRO100State
* s
)
308 TRACE(INT
, logout("interrupt enabled\n"));
309 qemu_irq_raise(s
->dev
.irq
[0]);
314 static void eepro100_acknowledge(EEPRO100State
* s
)
316 s
->scb_stat
&= ~s
->mem
[SCBAck
];
317 s
->mem
[SCBAck
] = s
->scb_stat
;
318 if (s
->scb_stat
== 0) {
319 disable_interrupt(s
);
323 static void eepro100_interrupt(EEPRO100State
* s
, uint8_t stat
)
325 uint8_t mask
= ~s
->mem
[SCBIntmask
];
326 s
->mem
[SCBAck
] |= stat
;
327 stat
= s
->scb_stat
= s
->mem
[SCBAck
];
328 stat
&= (mask
| 0x0f);
329 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
330 if (stat
&& (mask
& 0x01)) {
331 /* SCB mask and SCB Bit M do not disable interrupt. */
333 } else if (s
->int_stat
) {
334 disable_interrupt(s
);
338 static void eepro100_cx_interrupt(EEPRO100State
* s
)
340 /* CU completed action command. */
341 /* Transmit not ok (82557 only, not in emulation). */
342 eepro100_interrupt(s
, 0x80);
345 static void eepro100_cna_interrupt(EEPRO100State
* s
)
347 /* CU left the active state. */
348 eepro100_interrupt(s
, 0x20);
351 static void eepro100_fr_interrupt(EEPRO100State
* s
)
353 /* RU received a complete frame. */
354 eepro100_interrupt(s
, 0x40);
358 static void eepro100_rnr_interrupt(EEPRO100State
* s
)
360 /* RU is not ready. */
361 eepro100_interrupt(s
, 0x10);
365 static void eepro100_mdi_interrupt(EEPRO100State
* s
)
367 /* MDI completed read or write cycle. */
368 eepro100_interrupt(s
, 0x08);
371 static void eepro100_swi_interrupt(EEPRO100State
* s
)
373 /* Software has requested an interrupt. */
374 eepro100_interrupt(s
, 0x04);
378 static void eepro100_fcp_interrupt(EEPRO100State
* s
)
380 /* Flow control pause interrupt (82558 and later). */
381 eepro100_interrupt(s
, 0x01);
385 static void pci_reset(EEPRO100State
* s
)
387 uint32_t device
= s
->device
;
388 uint8_t *pci_conf
= s
->dev
.config
;
390 TRACE(OTHER
, logout("%p\n", s
));
393 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
394 /* PCI Device ID depends on device and is set below. */
396 PCI_CONFIG_16(PCI_COMMAND
, 0x0000);
398 PCI_CONFIG_16(PCI_STATUS
, 0x2800);
399 /* PCI Revision ID */
400 PCI_CONFIG_8(PCI_REVISION_ID
, 0x08);
402 PCI_CONFIG_8(0x09, 0x00);
403 pci_config_set_class(pci_conf
, PCI_CLASS_NETWORK_ETHERNET
);
404 /* PCI Cache Line Size */
405 /* check cache line size!!! */
406 //~ PCI_CONFIG_8(0x0c, 0x00);
407 /* PCI Latency Timer */
408 PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
409 /* PCI Header Type */
410 /* BIST (built-in self test) */
411 #if defined(TARGET_I386)
412 // !!! workaround for buggy bios
413 //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
416 /* PCI Base Address Registers */
417 /* CSR Memory Mapped Base Address */
418 PCI_CONFIG_32(PCI_BASE_ADDRESS_0
,
419 PCI_ADDRESS_SPACE_MEM
| PCI_ADDRESS_SPACE_MEM_PREFETCH
);
420 /* CSR I/O Mapped Base Address */
421 PCI_CONFIG_32(PCI_BASE_ADDRESS_1
, PCI_ADDRESS_SPACE_IO
);
423 /* Flash Memory Mapped Base Address */
424 PCI_CONFIG_32(PCI_BASE_ADDRESS_2
, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM
);
427 /* Expansion ROM Base Address (depends on boot disable!!!) */
428 PCI_CONFIG_32(0x30, 0x00000000);
429 /* Capability Pointer */
430 PCI_CONFIG_8(0x34, 0xdc);
433 PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
435 PCI_CONFIG_8(0x3e, 0x08);
436 /* Maximum Latency */
437 PCI_CONFIG_8(0x3f, 0x18);
438 /* Power Management Capabilities / Next Item Pointer / Capability ID */
439 PCI_CONFIG_32(0xdc, 0x7e210001);
443 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
444 PCI_CONFIG_8(PCI_REVISION_ID
, 0x0f);
447 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
448 PCI_CONFIG_8(PCI_REVISION_ID
, 0x02);
451 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
452 PCI_CONFIG_8(PCI_REVISION_ID
, 0x03);
455 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
456 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
457 PCI_CONFIG_8(PCI_REVISION_ID
, 0x05);
460 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82557
);
461 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
462 //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
465 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82551IT
);
466 PCI_CONFIG_16(PCI_STATUS
, 0x2810);
467 PCI_CONFIG_8(PCI_REVISION_ID
, 0x09);
469 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
470 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
472 logout("Device %X is undefined!\n", device
);
475 if (device
== i82557C
|| device
== i82558B
|| device
== i82559C
) {
476 logout("Get device id and revision from EEPROM!!!\n");
480 static void nic_selective_reset(EEPRO100State
* s
)
483 uint16_t *eeprom_contents
= eeprom93xx_data(s
->eeprom
);
484 //~ eeprom93xx_reset(s->eeprom);
485 memcpy(eeprom_contents
, s
->macaddr
, 6);
486 eeprom_contents
[0xa] = 0x4000;
487 if (s
->device
== i82557B
|| s
->device
== i82557C
)
488 eeprom_contents
[5] = 0x0100;
490 for (i
= 0; i
< EEPROM_SIZE
- 1; i
++) {
491 sum
+= eeprom_contents
[i
];
493 eeprom_contents
[EEPROM_SIZE
- 1] = 0xbaba - sum
;
494 TRACE(EEPROM
, logout("checksum=0x%04x\n", eeprom_contents
[EEPROM_SIZE
- 1]));
496 memset(s
->mem
, 0, sizeof(s
->mem
));
497 uint32_t val
= BIT(21);
498 memcpy(&s
->mem
[SCBCtrlMDI
], &val
, sizeof(val
));
500 assert(sizeof(s
->mdimem
) == sizeof(eepro100_mdi_default
));
501 memcpy(&s
->mdimem
[0], &eepro100_mdi_default
[0], sizeof(s
->mdimem
));
504 static void nic_reset(void *opaque
)
506 EEPRO100State
*s
= opaque
;
507 TRACE(OTHER
, logout("%p\n", s
));
508 nic_selective_reset(s
);
511 #if defined(DEBUG_EEPRO100)
512 static const char * const reg
[PCI_IO_SIZE
/ 4] = {
516 "EEPROM/Flash Control",
518 "Receive DMA Byte Count",
520 "General Status/Control"
523 static char *regname(uint32_t addr
)
526 if (addr
< PCI_IO_SIZE
) {
527 const char *r
= reg
[addr
/ 4];
529 snprintf(buf
, sizeof(buf
), "%s+%u", r
, addr
% 4);
531 snprintf(buf
, sizeof(buf
), "0x%02x", addr
);
534 snprintf(buf
, sizeof(buf
), "??? 0x%08x", addr
);
538 #endif /* DEBUG_EEPRO100 */
541 static uint16_t eepro100_read_status(EEPRO100State
* s
)
543 uint16_t val
= s
->status
;
544 TRACE(OTHER
, logout("val=0x%04x\n", val
));
548 static void eepro100_write_status(EEPRO100State
* s
, uint16_t val
)
550 TRACE(OTHER
, logout("val=0x%04x\n", val
));
555 /*****************************************************************************
559 ****************************************************************************/
562 static uint16_t eepro100_read_command(EEPRO100State
* s
)
564 uint16_t val
= 0xffff;
565 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
570 static bool device_supports_eTxCB(EEPRO100State
* s
)
572 return (s
->device
!= i82557B
&& s
->device
!= i82557C
);
575 /* Commands that can be put in a command list entry. */
580 CmdMulticastList
= 3,
582 CmdTDR
= 5, /* load microcode */
586 /* And some extra flags: */
587 CmdSuspend
= 0x4000, /* Suspend after completion. */
588 CmdIntr
= 0x2000, /* Interrupt after completion. */
589 CmdTxFlex
= 0x0008, /* Use "Flexible mode" for CmdTx command. */
592 static cu_state_t
get_cu_state(EEPRO100State
* s
)
594 return ((s
->mem
[SCBStatus
] >> 6) & 0x03);
597 static void set_cu_state(EEPRO100State
* s
, cu_state_t state
)
599 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0x3f) + (state
<< 6);
602 static ru_state_t
get_ru_state(EEPRO100State
* s
)
604 return ((s
->mem
[SCBStatus
] >> 2) & 0x0f);
607 static void set_ru_state(EEPRO100State
* s
, ru_state_t state
)
609 s
->mem
[SCBStatus
] = (s
->mem
[SCBStatus
] & 0xc3) + (state
<< 2);
612 static void dump_statistics(EEPRO100State
* s
)
614 /* Dump statistical data. Most data is never changed by the emulation
615 * and always 0, so we first just copy the whole block and then those
616 * values which really matter.
617 * Number of data should check configuration!!!
619 cpu_physical_memory_write(s
->statsaddr
, (uint8_t *) & s
->statistics
, 64);
620 stl_phys(s
->statsaddr
+ 0, s
->statistics
.tx_good_frames
);
621 stl_phys(s
->statsaddr
+ 36, s
->statistics
.rx_good_frames
);
622 stl_phys(s
->statsaddr
+ 48, s
->statistics
.rx_resource_errors
);
623 stl_phys(s
->statsaddr
+ 60, s
->statistics
.rx_short_frame_errors
);
624 //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
625 //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
626 //~ missing("CU dump statistical counters");
629 static void eepro100_cu_command(EEPRO100State
* s
, uint8_t val
)
638 if (get_cu_state(s
) != cu_idle
) {
639 /* Intel documentation says that CU must be idle for the CU
640 * start command. Intel driver for Linux also starts the CU
641 * from suspended state. */
642 logout("CU state is %u, should be %u\n", get_cu_state(s
), cu_idle
);
643 //~ assert(!"wrong CU state");
645 set_cu_state(s
, cu_active
);
646 s
->cu_offset
= s
->pointer
;
648 cb_address
= s
->cu_base
+ s
->cu_offset
;
649 cpu_physical_memory_read(cb_address
, (uint8_t *) & tx
, sizeof(tx
));
650 uint16_t status
= le16_to_cpu(tx
.status
);
651 uint16_t command
= le16_to_cpu(tx
.command
);
653 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
654 val
, status
, command
, tx
.link
);
655 bool bit_el
= ((command
& 0x8000) != 0);
656 bool bit_s
= ((command
& 0x4000) != 0);
657 bool bit_i
= ((command
& 0x2000) != 0);
658 bool bit_nc
= ((command
& 0x0010) != 0);
660 //~ bool bit_sf = ((command & 0x0008) != 0);
661 uint16_t cmd
= command
& 0x0007;
662 s
->cu_offset
= le32_to_cpu(tx
.link
);
668 cpu_physical_memory_read(cb_address
+ 8, &s
->macaddr
[0], 6);
669 TRACE(OTHER
, logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6)));
672 cpu_physical_memory_read(cb_address
+ 8, &s
->configuration
[0],
673 sizeof(s
->configuration
));
674 TRACE(OTHER
, logout("configuration: %s\n", nic_dump(&s
->configuration
[0], 16)));
676 case CmdMulticastList
:
677 //~ missing("multicast list");
681 uint32_t tbd_array
= le32_to_cpu(tx
.tx_desc_addr
);
682 uint16_t tcb_bytes
= (le16_to_cpu(tx
.tcb_bytes
) & 0x3fff);
684 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
685 tbd_array
, tcb_bytes
, tx
.tbd_count
));
688 missing("CmdTx: NC = 0");
693 if (tcb_bytes
> 2600) {
694 logout("TCB byte count too large, using 2600\n");
697 /* Next assertion fails for local configuration. */
698 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
699 if (!((tcb_bytes
> 0) || (tbd_array
!= 0xffffffff))) {
701 ("illegal values of TBD array address and TCB byte count!\n");
703 // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
706 uint32_t tbd_address
= cb_address
+ 0x10;
707 assert(tcb_bytes
<= sizeof(buf
));
708 while (size
< tcb_bytes
) {
709 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
710 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
711 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
714 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
715 tx_buffer_address
, tx_buffer_size
));
716 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
717 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
719 size
+= tx_buffer_size
;
721 if (tbd_array
== 0xffffffff) {
722 /* Simplified mode. Was already handled by code above. */
725 uint8_t tbd_count
= 0;
726 if (device_supports_eTxCB(s
) && !(s
->configuration
[6] & BIT(4))) {
727 /* Extended Flexible TCB. */
728 for (; tbd_count
< 2; tbd_count
++) {
729 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
730 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
731 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
734 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
735 tx_buffer_address
, tx_buffer_size
));
736 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
737 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
739 size
+= tx_buffer_size
;
740 if (tx_buffer_el
& 1) {
745 tbd_address
= tbd_array
;
746 for (; tbd_count
< tx
.tbd_count
; tbd_count
++) {
747 uint32_t tx_buffer_address
= ldl_phys(tbd_address
);
748 uint16_t tx_buffer_size
= lduw_phys(tbd_address
+ 4);
749 uint16_t tx_buffer_el
= lduw_phys(tbd_address
+ 6);
752 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
753 tx_buffer_address
, tx_buffer_size
));
754 tx_buffer_size
= MIN(tx_buffer_size
, sizeof(buf
) - size
);
755 cpu_physical_memory_read(tx_buffer_address
, &buf
[size
],
757 size
+= tx_buffer_size
;
758 if (tx_buffer_el
& 1) {
763 TRACE(RXTX
, logout("%p sending frame, len=%d,%s\n", s
, size
, nic_dump(buf
, size
)));
764 qemu_send_packet(s
->vc
, buf
, size
);
765 s
->statistics
.tx_good_frames
++;
766 /* Transmit with bad status would raise an CX/TNO interrupt.
767 * (82557 only). Emulation never has bad status. */
768 //~ eepro100_cx_interrupt(s);
771 TRACE(OTHER
, logout("load microcode\n"));
772 /* Starting with offset 8, the command contains
773 * 64 dwords microcode which we just ignore here. */
776 missing("undefined command");
780 /* Write new status. */
781 stw_phys(cb_address
, status
| 0x8000 | (success
? 0x2000 : 0));
783 /* CU completed action. */
784 eepro100_cx_interrupt(s
);
787 /* CU becomes idle. Terminate command loop. */
788 set_cu_state(s
, cu_idle
);
789 eepro100_cna_interrupt(s
);
791 /* CU becomes suspended. */
792 set_cu_state(s
, cu_suspended
);
793 eepro100_cna_interrupt(s
);
795 /* More entries in list. */
796 TRACE(OTHER
, logout("CU list with at least one more entry\n"));
799 TRACE(OTHER
, logout("CU list empty\n"));
800 /* List is empty. Now CU is idle or suspended. */
803 if (get_cu_state(s
) != cu_suspended
) {
804 logout("bad CU resume from CU state %u\n", get_cu_state(s
));
805 /* Workaround for bad Linux eepro100 driver which resumes
806 * from idle state. */
807 //~ missing("cu resume");
808 set_cu_state(s
, cu_suspended
);
810 if (get_cu_state(s
) == cu_suspended
) {
811 TRACE(OTHER
, logout("CU resuming\n"));
812 set_cu_state(s
, cu_active
);
817 /* Load dump counters address. */
818 s
->statsaddr
= s
->pointer
;
819 TRACE(OTHER
, logout("val=0x%02x (status address)\n", val
));
822 /* Dump statistical counters. */
823 TRACE(OTHER
, logout("val=0x%02x (dump stats)\n", val
));
828 TRACE(OTHER
, logout("val=0x%02x (CU base address)\n", val
));
829 s
->cu_base
= s
->pointer
;
832 /* Dump and reset statistical counters. */
833 TRACE(OTHER
, logout("val=0x%02x (dump stats and reset)\n", val
));
835 memset(&s
->statistics
, 0, sizeof(s
->statistics
));
838 /* CU static resume. */
839 missing("CU static resume");
842 missing("Undefined CU command");
846 static void eepro100_ru_command(EEPRO100State
* s
, uint8_t val
)
854 if (get_ru_state(s
) != ru_idle
) {
855 logout("RU state is %u, should be %u\n", get_ru_state(s
), ru_idle
);
856 //~ assert(!"wrong RU state");
858 set_ru_state(s
, ru_ready
);
859 s
->ru_offset
= s
->pointer
;
860 TRACE(OTHER
, logout("val=0x%02x (rx start)\n", val
));
864 if (get_ru_state(s
) != ru_suspended
) {
865 logout("RU state is %u, should be %u\n", get_ru_state(s
),
867 //~ assert(!"wrong RU state");
869 set_ru_state(s
, ru_ready
);
873 TRACE(OTHER
, logout("val=0x%02x (RU base address)\n", val
));
874 s
->ru_base
= s
->pointer
;
877 logout("val=0x%02x (undefined RU command)\n", val
);
878 missing("Undefined SU command");
882 static void eepro100_write_command(EEPRO100State
* s
, uint8_t val
)
884 eepro100_ru_command(s
, val
& 0x0f);
885 eepro100_cu_command(s
, val
& 0xf0);
887 TRACE(OTHER
, logout("val=0x%02x\n", val
));
889 /* Clear command byte after command was accepted. */
893 /*****************************************************************************
897 ****************************************************************************/
899 #define EEPROM_CS 0x02
900 #define EEPROM_SK 0x01
901 #define EEPROM_DI 0x04
902 #define EEPROM_DO 0x08
904 static uint16_t eepro100_read_eeprom(EEPRO100State
* s
)
907 memcpy(&val
, &s
->mem
[SCBeeprom
], sizeof(val
));
908 if (eeprom93xx_read(s
->eeprom
)) {
913 TRACE(EEPROM
, logout("val=0x%04x\n", val
));
917 static void eepro100_write_eeprom(eeprom_t
* eeprom
, uint8_t val
)
919 TRACE(EEPROM
, logout("val=0x%02x\n", val
));
921 /* mask unwriteable bits */
922 //~ val = SET_MASKED(val, 0x31, eeprom->value);
924 int eecs
= ((val
& EEPROM_CS
) != 0);
925 int eesk
= ((val
& EEPROM_SK
) != 0);
926 int eedi
= ((val
& EEPROM_DI
) != 0);
927 eeprom93xx_write(eeprom
, eecs
, eesk
, eedi
);
930 static void eepro100_write_pointer(EEPRO100State
* s
, uint32_t val
)
932 s
->pointer
= le32_to_cpu(val
);
933 TRACE(OTHER
, logout("val=0x%08x\n", val
));
936 /*****************************************************************************
940 ****************************************************************************/
942 #if defined(DEBUG_EEPRO100)
943 static const char * const mdi_op_name
[] = {
950 static const char * const mdi_reg_name
[] = {
953 "PHY Identification (Word 1)",
954 "PHY Identification (Word 2)",
955 "Auto-Negotiation Advertisement",
956 "Auto-Negotiation Link Partner Ability",
957 "Auto-Negotiation Expansion"
960 static const char *reg2name(uint8_t reg
)
962 static char buffer
[10];
963 const char *p
= buffer
;
964 if (reg
< ARRAY_SIZE(mdi_reg_name
)) {
965 p
= mdi_reg_name
[reg
];
967 snprintf(buffer
, sizeof(buffer
), "reg=0x%02x", reg
);
971 #endif /* DEBUG_EEPRO100 */
973 static uint32_t eepro100_read_mdi(EEPRO100State
* s
)
976 memcpy(&val
, &s
->mem
[0x10], sizeof(val
));
978 #ifdef DEBUG_EEPRO100
979 uint8_t raiseint
= (val
& BIT(29)) >> 29;
980 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
981 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
982 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
983 uint16_t data
= (val
& BITS(15, 0));
985 /* Emulation takes no time to finish MDI transaction. */
987 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
988 val
, raiseint
, mdi_op_name
[opcode
], phy
,
989 reg2name(reg
), data
));
993 static void eepro100_write_mdi(EEPRO100State
* s
, uint32_t val
)
995 uint8_t raiseint
= (val
& BIT(29)) >> 29;
996 uint8_t opcode
= (val
& BITS(27, 26)) >> 26;
997 uint8_t phy
= (val
& BITS(25, 21)) >> 21;
998 uint8_t reg
= (val
& BITS(20, 16)) >> 16;
999 uint16_t data
= (val
& BITS(15, 0));
1000 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1001 val
, raiseint
, mdi_op_name
[opcode
], phy
, reg2name(reg
), data
));
1003 /* Unsupported PHY address. */
1004 //~ logout("phy must be 1 but is %u\n", phy);
1006 } else if (opcode
!= 1 && opcode
!= 2) {
1007 /* Unsupported opcode. */
1008 logout("opcode must be 1 or 2 but is %u\n", opcode
);
1010 } else if (reg
> 6) {
1011 /* Unsupported register. */
1012 logout("register must be 0...6 but is %u\n", reg
);
1015 TRACE(MDI
, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1016 val
, raiseint
, mdi_op_name
[opcode
], phy
,
1017 reg2name(reg
), data
));
1021 case 0: /* Control Register */
1022 if (data
& 0x8000) {
1023 /* Reset status and control registers to default. */
1024 s
->mdimem
[0] = eepro100_mdi_default
[0];
1025 s
->mdimem
[1] = eepro100_mdi_default
[1];
1026 data
= s
->mdimem
[reg
];
1028 /* Restart Auto Configuration = Normal Operation */
1032 case 1: /* Status Register */
1033 missing("not writable");
1034 data
= s
->mdimem
[reg
];
1036 case 2: /* PHY Identification Register (Word 1) */
1037 case 3: /* PHY Identification Register (Word 2) */
1038 missing("not implemented");
1040 case 4: /* Auto-Negotiation Advertisement Register */
1041 case 5: /* Auto-Negotiation Link Partner Ability Register */
1043 case 6: /* Auto-Negotiation Expansion Register */
1045 missing("not implemented");
1047 s
->mdimem
[reg
] = data
;
1048 } else if (opcode
== 2) {
1051 case 0: /* Control Register */
1052 if (data
& 0x8000) {
1053 /* Reset status and control registers to default. */
1054 s
->mdimem
[0] = eepro100_mdi_default
[0];
1055 s
->mdimem
[1] = eepro100_mdi_default
[1];
1058 case 1: /* Status Register */
1059 s
->mdimem
[reg
] |= 0x0020;
1061 case 2: /* PHY Identification Register (Word 1) */
1062 case 3: /* PHY Identification Register (Word 2) */
1063 case 4: /* Auto-Negotiation Advertisement Register */
1065 case 5: /* Auto-Negotiation Link Partner Ability Register */
1066 s
->mdimem
[reg
] = 0x41fe;
1068 case 6: /* Auto-Negotiation Expansion Register */
1069 s
->mdimem
[reg
] = 0x0001;
1072 data
= s
->mdimem
[reg
];
1074 /* Emulation takes no time to finish MDI transaction.
1075 * Set MDI bit in SCB status register. */
1076 s
->mem
[SCBAck
] |= 0x08;
1079 eepro100_mdi_interrupt(s
);
1082 val
= (val
& 0xffff0000) + data
;
1083 memcpy(&s
->mem
[0x10], &val
, sizeof(val
));
1086 /*****************************************************************************
1090 ****************************************************************************/
1092 #define PORT_SOFTWARE_RESET 0
1093 #define PORT_SELFTEST 1
1094 #define PORT_SELECTIVE_RESET 2
1096 #define PORT_SELECTION_MASK 3
1099 uint32_t st_sign
; /* Self Test Signature */
1100 uint32_t st_result
; /* Self Test Results */
1101 } eepro100_selftest_t
;
1103 static uint32_t eepro100_read_port(EEPRO100State
* s
)
1108 static void eepro100_write_port(EEPRO100State
* s
, uint32_t val
)
1110 val
= le32_to_cpu(val
);
1111 uint32_t address
= (val
& ~PORT_SELECTION_MASK
);
1112 uint8_t selection
= (val
& PORT_SELECTION_MASK
);
1113 switch (selection
) {
1114 case PORT_SOFTWARE_RESET
:
1118 TRACE(OTHER
, logout("selftest address=0x%08x\n", address
));
1119 eepro100_selftest_t data
;
1120 cpu_physical_memory_read(address
, (uint8_t *) & data
, sizeof(data
));
1121 data
.st_sign
= 0xffffffff;
1123 cpu_physical_memory_write(address
, (uint8_t *) & data
, sizeof(data
));
1125 case PORT_SELECTIVE_RESET
:
1126 TRACE(OTHER
, logout("selective reset, selftest address=0x%08x\n", address
));
1127 nic_selective_reset(s
);
1130 logout("val=0x%08x\n", val
);
1131 missing("unknown port selection");
1135 /*****************************************************************************
1137 * General hardware emulation.
1139 ****************************************************************************/
1141 static uint8_t eepro100_read1(EEPRO100State
* s
, uint32_t addr
)
1144 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1145 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1150 //~ val = eepro100_read_status(s);
1151 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1154 //~ val = eepro100_read_status(s);
1155 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1158 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1159 //~ val = eepro100_read_command(s);
1162 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1165 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1168 val
= eepro100_read_eeprom(s
);
1170 case 0x1b: /* PMDR (power management driver register) */
1172 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1174 case 0x1d: /* general status register */
1175 /* 100 Mbps full duplex, valid link */
1177 TRACE(OTHER
, logout("addr=General Status val=%02x\n", val
));
1180 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1181 missing("unknown byte read");
1186 static uint16_t eepro100_read2(EEPRO100State
* s
, uint32_t addr
)
1189 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1190 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1195 //~ val = eepro100_read_status(s);
1197 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1200 val
= eepro100_read_eeprom(s
);
1201 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1204 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1205 missing("unknown word read");
1210 static uint32_t eepro100_read4(EEPRO100State
* s
, uint32_t addr
)
1213 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1214 memcpy(&val
, &s
->mem
[addr
], sizeof(val
));
1219 //~ val = eepro100_read_status(s);
1220 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1223 //~ val = eepro100_read_pointer(s);
1224 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1227 val
= eepro100_read_port(s
);
1228 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1231 val
= eepro100_read_mdi(s
);
1234 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1235 missing("unknown longword read");
1240 static void eepro100_write1(EEPRO100State
* s
, uint32_t addr
, uint8_t val
)
1242 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1243 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1246 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1250 //~ eepro100_write_status(s, val);
1253 eepro100_acknowledge(s
);
1256 eepro100_write_command(s
, val
);
1260 eepro100_swi_interrupt(s
);
1262 eepro100_interrupt(s
, 0);
1265 case SCBFlow
: /* does not exist on 82557 */
1269 TRACE(OTHER
, logout("addr=%s val=0x%02x\n", regname(addr
), val
));
1272 eepro100_write_eeprom(s
->eeprom
, val
);
1275 logout("addr=%s val=0x%02x\n", regname(addr
), val
);
1276 missing("unknown byte write");
1280 static void eepro100_write2(EEPRO100State
* s
, uint32_t addr
, uint16_t val
)
1282 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1283 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1286 TRACE(OTHER
, logout("addr=%s val=0x%04x\n", regname(addr
), val
));
1290 //~ eepro100_write_status(s, val);
1291 eepro100_acknowledge(s
);
1294 eepro100_write_command(s
, val
);
1295 eepro100_write1(s
, SCBIntmask
, val
>> 8);
1298 eepro100_write_eeprom(s
->eeprom
, val
);
1301 logout("addr=%s val=0x%04x\n", regname(addr
), val
);
1302 missing("unknown word write");
1306 static void eepro100_write4(EEPRO100State
* s
, uint32_t addr
, uint32_t val
)
1308 if (addr
<= sizeof(s
->mem
) - sizeof(val
)) {
1309 memcpy(&s
->mem
[addr
], &val
, sizeof(val
));
1314 eepro100_write_pointer(s
, val
);
1317 TRACE(OTHER
, logout("addr=%s val=0x%08x\n", regname(addr
), val
));
1318 eepro100_write_port(s
, val
);
1321 eepro100_write_mdi(s
, val
);
1324 logout("addr=%s val=0x%08x\n", regname(addr
), val
);
1325 missing("unknown longword write");
1329 /*****************************************************************************
1333 ****************************************************************************/
1335 static uint32_t ioport_read1(void *opaque
, uint32_t addr
)
1337 EEPRO100State
*s
= opaque
;
1338 //~ logout("addr=%s\n", regname(addr));
1339 return eepro100_read1(s
, addr
- s
->region
[1]);
1342 static uint32_t ioport_read2(void *opaque
, uint32_t addr
)
1344 EEPRO100State
*s
= opaque
;
1345 return eepro100_read2(s
, addr
- s
->region
[1]);
1348 static uint32_t ioport_read4(void *opaque
, uint32_t addr
)
1350 EEPRO100State
*s
= opaque
;
1351 return eepro100_read4(s
, addr
- s
->region
[1]);
1354 static void ioport_write1(void *opaque
, uint32_t addr
, uint32_t val
)
1356 EEPRO100State
*s
= opaque
;
1357 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1358 eepro100_write1(s
, addr
- s
->region
[1], val
);
1361 static void ioport_write2(void *opaque
, uint32_t addr
, uint32_t val
)
1363 EEPRO100State
*s
= opaque
;
1364 eepro100_write2(s
, addr
- s
->region
[1], val
);
1367 static void ioport_write4(void *opaque
, uint32_t addr
, uint32_t val
)
1369 EEPRO100State
*s
= opaque
;
1370 eepro100_write4(s
, addr
- s
->region
[1], val
);
1373 /***********************************************************/
1374 /* PCI EEPRO100 definitions */
1376 static void pci_map(PCIDevice
* pci_dev
, int region_num
,
1377 uint32_t addr
, uint32_t size
, int type
)
1379 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1381 TRACE(OTHER
, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1382 region_num
, addr
, size
, type
));
1384 assert(region_num
== 1);
1385 register_ioport_write(addr
, size
, 1, ioport_write1
, s
);
1386 register_ioport_read(addr
, size
, 1, ioport_read1
, s
);
1387 register_ioport_write(addr
, size
, 2, ioport_write2
, s
);
1388 register_ioport_read(addr
, size
, 2, ioport_read2
, s
);
1389 register_ioport_write(addr
, size
, 4, ioport_write4
, s
);
1390 register_ioport_read(addr
, size
, 4, ioport_read4
, s
);
1392 s
->region
[region_num
] = addr
;
1395 /*****************************************************************************
1397 * Memory mapped I/O.
1399 ****************************************************************************/
1401 static void pci_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1403 EEPRO100State
*s
= opaque
;
1404 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1405 eepro100_write1(s
, addr
, val
);
1408 static void pci_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1410 EEPRO100State
*s
= opaque
;
1411 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1412 eepro100_write2(s
, addr
, val
);
1415 static void pci_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1417 EEPRO100State
*s
= opaque
;
1418 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1419 eepro100_write4(s
, addr
, val
);
1422 static uint32_t pci_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1424 EEPRO100State
*s
= opaque
;
1425 //~ logout("addr=%s\n", regname(addr));
1426 return eepro100_read1(s
, addr
);
1429 static uint32_t pci_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1431 EEPRO100State
*s
= opaque
;
1432 //~ logout("addr=%s\n", regname(addr));
1433 return eepro100_read2(s
, addr
);
1436 static uint32_t pci_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1438 EEPRO100State
*s
= opaque
;
1439 //~ logout("addr=%s\n", regname(addr));
1440 return eepro100_read4(s
, addr
);
1443 static CPUWriteMemoryFunc
* const pci_mmio_write
[] = {
1449 static CPUReadMemoryFunc
* const pci_mmio_read
[] = {
1455 static void pci_mmio_map(PCIDevice
* pci_dev
, int region_num
,
1456 uint32_t addr
, uint32_t size
, int type
)
1458 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1460 TRACE(OTHER
, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1461 region_num
, addr
, size
, type
));
1463 if (region_num
== 0) {
1464 /* Map control / status registers. */
1465 cpu_register_physical_memory(addr
, size
, s
->mmio_index
);
1466 s
->region
[region_num
] = addr
;
1470 static int nic_can_receive(VLANClientState
*vc
)
1472 EEPRO100State
*s
= vc
->opaque
;
1473 TRACE(RXTX
, logout("%p\n", s
));
1474 return get_ru_state(s
) == ru_ready
;
1475 //~ return !eepro100_buffer_full(s);
1478 static ssize_t
nic_receive(VLANClientState
*vc
, const uint8_t * buf
, size_t size
)
1481 * - Magic packets should set bit 30 in power management driver register.
1482 * - Interesting packets should set bit 29 in power management driver register.
1484 EEPRO100State
*s
= vc
->opaque
;
1485 uint16_t rfd_status
= 0xa000;
1486 static const uint8_t broadcast_macaddr
[6] =
1487 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1489 /* TODO: check multiple IA bit. */
1490 if (s
->configuration
[20] & BIT(6)) {
1491 missing("Multiple IA bit");
1495 if (s
->configuration
[8] & 0x80) {
1496 /* CSMA is disabled. */
1497 logout("%p received while CSMA is disabled\n", s
);
1499 } else if (size
< 64 && (s
->configuration
[7] & 1)) {
1500 /* Short frame and configuration byte 7/0 (discard short receive) set:
1501 * Short frame is discarded */
1502 logout("%p received short frame (%zu byte)\n", s
, size
);
1503 s
->statistics
.rx_short_frame_errors
++;
1505 } else if ((size
> MAX_ETH_FRAME_SIZE
+ 4) && !(s
->configuration
[18] & 8)) {
1506 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1507 * Long frames are discarded. */
1508 logout("%p received long frame (%zu byte), ignored\n", s
, size
);
1510 } else if (memcmp(buf
, s
->macaddr
, 6) == 0) { // !!!
1511 /* Frame matches individual address. */
1512 /* TODO: check configuration byte 15/4 (ignore U/L). */
1513 TRACE(RXTX
, logout("%p received frame for me, len=%zu\n", s
, size
));
1514 } else if (memcmp(buf
, broadcast_macaddr
, 6) == 0) {
1515 /* Broadcast frame. */
1516 TRACE(RXTX
, logout("%p received broadcast, len=%zu\n", s
, size
));
1517 rfd_status
|= 0x0002;
1518 } else if (buf
[0] & 0x01) { // !!!
1519 /* Multicast frame. */
1520 TRACE(RXTX
, logout("%p received multicast, len=%zu\n", s
, size
));
1521 /* TODO: check multicast all bit. */
1522 if (s
->configuration
[21] & BIT(3)) {
1523 missing("Multicast All bit");
1525 int mcast_idx
= compute_mcast_idx(buf
);
1526 if (!(s
->mult
[mcast_idx
>> 3] & (1 << (mcast_idx
& 7)))) {
1529 rfd_status
|= 0x0002;
1530 } else if (s
->configuration
[15] & 1) {
1531 /* Promiscuous: receive all. */
1532 TRACE(RXTX
, logout("%p received frame in promiscuous mode, len=%zu\n", s
, size
));
1533 rfd_status
|= 0x0004;
1535 TRACE(RXTX
, logout("%p received frame, ignored, len=%zu,%s\n", s
, size
,
1536 nic_dump(buf
, size
)));
1540 if (get_ru_state(s
) != ru_ready
) {
1541 /* No resources available. */
1542 logout("no resources, state=%u\n", get_ru_state(s
));
1543 s
->statistics
.rx_resource_errors
++;
1544 //~ assert(!"no resources");
1548 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1550 cpu_physical_memory_read(s
->ru_base
+ s
->ru_offset
, (uint8_t *) & rx
,
1551 offsetof(eepro100_rx_t
, packet
));
1552 uint16_t rfd_command
= le16_to_cpu(rx
.command
);
1553 uint16_t rfd_size
= le16_to_cpu(rx
.size
);
1555 if (size
> rfd_size
) {
1556 logout("Receive buffer (%" PRId16
" bytes) too small for data "
1557 "(%zu bytes); data truncated\n", rfd_size
, size
);
1561 rfd_status
|= 0x0080;
1563 TRACE(OTHER
, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1564 rfd_command
, rx
.link
, rx
.rx_buf_addr
, rfd_size
));
1565 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, status
),
1567 stw_phys(s
->ru_base
+ s
->ru_offset
+ offsetof(eepro100_rx_t
, count
), size
);
1568 /* Early receive interrupt not supported. */
1569 //~ eepro100_er_interrupt(s);
1570 /* Receive CRC Transfer not supported. */
1571 if (s
->configuration
[18] & 4) {
1572 missing("Receive CRC Transfer");
1575 /* TODO: check stripping enable bit. */
1576 //~ assert(!(s->configuration[17] & 1));
1577 cpu_physical_memory_write(s
->ru_base
+ s
->ru_offset
+
1578 offsetof(eepro100_rx_t
, packet
), buf
, size
);
1579 s
->statistics
.rx_good_frames
++;
1580 eepro100_fr_interrupt(s
);
1581 s
->ru_offset
= le32_to_cpu(rx
.link
);
1582 if (rfd_command
& 0x8000) {
1583 /* EL bit is set, so this was the last frame. */
1584 logout("receive: Running out of frames\n");
1585 set_ru_state(s
, ru_suspended
);
1587 if (rfd_command
& 0x4000) {
1589 set_ru_state(s
, ru_suspended
);
1594 static int nic_load(QEMUFile
* f
, void *opaque
, int version_id
)
1596 EEPRO100State
*s
= opaque
;
1603 ret
= pci_device_load(&s
->dev
, f
);
1608 /* Skip unused entries. */
1609 qemu_fseek(f
, 32, SEEK_CUR
);
1611 qemu_get_buffer(f
, s
->mult
, 8);
1612 qemu_get_buffer(f
, s
->mem
, sizeof(s
->mem
));
1614 /* Restore all members of struct between scb_stat and mem. */
1615 qemu_get_8s(f
, &s
->scb_stat
);
1616 qemu_get_8s(f
, &s
->int_stat
);
1617 /* Skip unused entries. */
1618 qemu_fseek(f
, 3 * 4, SEEK_CUR
);
1619 qemu_get_buffer(f
, s
->macaddr
, 6);
1620 /* Skip unused entries. */
1621 qemu_fseek(f
, 19 * 4, SEEK_CUR
);
1622 for (i
= 0; i
< 32; i
++) {
1623 qemu_get_be16s(f
, &s
->mdimem
[i
]);
1625 /* The eeprom should be saved and restored by its own routines. */
1626 qemu_get_be32s(f
, &s
->device
);
1627 // TODO check device.
1628 qemu_get_be32s(f
, &s
->pointer
);
1629 qemu_get_be32s(f
, &s
->cu_base
);
1630 qemu_get_be32s(f
, &s
->cu_offset
);
1631 qemu_get_be32s(f
, &s
->ru_base
);
1632 qemu_get_be32s(f
, &s
->ru_offset
);
1633 qemu_get_be32s(f
, &s
->statsaddr
);
1634 /* Restore epro100_stats_t statistics. */
1635 qemu_get_be32s(f
, &s
->statistics
.tx_good_frames
);
1636 qemu_get_be32s(f
, &s
->statistics
.tx_max_collisions
);
1637 qemu_get_be32s(f
, &s
->statistics
.tx_late_collisions
);
1638 qemu_get_be32s(f
, &s
->statistics
.tx_underruns
);
1639 qemu_get_be32s(f
, &s
->statistics
.tx_lost_crs
);
1640 qemu_get_be32s(f
, &s
->statistics
.tx_deferred
);
1641 qemu_get_be32s(f
, &s
->statistics
.tx_single_collisions
);
1642 qemu_get_be32s(f
, &s
->statistics
.tx_multiple_collisions
);
1643 qemu_get_be32s(f
, &s
->statistics
.tx_total_collisions
);
1644 qemu_get_be32s(f
, &s
->statistics
.rx_good_frames
);
1645 qemu_get_be32s(f
, &s
->statistics
.rx_crc_errors
);
1646 qemu_get_be32s(f
, &s
->statistics
.rx_alignment_errors
);
1647 qemu_get_be32s(f
, &s
->statistics
.rx_resource_errors
);
1648 qemu_get_be32s(f
, &s
->statistics
.rx_overrun_errors
);
1649 qemu_get_be32s(f
, &s
->statistics
.rx_cdt_errors
);
1650 qemu_get_be32s(f
, &s
->statistics
.rx_short_frame_errors
);
1651 qemu_get_be32s(f
, &s
->statistics
.fc_xmt_pause
);
1652 qemu_get_be32s(f
, &s
->statistics
.fc_rcv_pause
);
1653 qemu_get_be32s(f
, &s
->statistics
.fc_rcv_unsupported
);
1654 qemu_get_be16s(f
, &s
->statistics
.xmt_tco_frames
);
1655 qemu_get_be16s(f
, &s
->statistics
.rcv_tco_frames
);
1656 qemu_get_be32s(f
, &s
->statistics
.complete
);
1658 qemu_get_be16s(f
, &s
->status
);
1661 /* Configuration bytes. */
1662 qemu_get_buffer(f
, s
->configuration
, sizeof(s
->configuration
));
1667 static void nic_save(QEMUFile
* f
, void *opaque
)
1669 EEPRO100State
*s
= opaque
;
1672 pci_device_save(&s
->dev
, f
);
1674 /* Skip unused entries. */
1675 qemu_fseek(f
, 32, SEEK_CUR
);
1677 qemu_put_buffer(f
, s
->mult
, 8);
1678 qemu_put_buffer(f
, s
->mem
, sizeof(s
->mem
));
1680 /* Save all members of struct between scb_stat and mem. */
1681 qemu_put_8s(f
, &s
->scb_stat
);
1682 qemu_put_8s(f
, &s
->int_stat
);
1683 /* Skip unused entries. */
1684 qemu_fseek(f
, 3 * 4, SEEK_CUR
);
1685 qemu_put_buffer(f
, s
->macaddr
, 6);
1686 /* Skip unused entries. */
1687 qemu_fseek(f
, 19 * 4, SEEK_CUR
);
1688 for (i
= 0; i
< 32; i
++) {
1689 qemu_put_be16s(f
, &s
->mdimem
[i
]);
1691 /* The eeprom should be saved and restored by its own routines. */
1692 qemu_put_be32s(f
, &s
->device
);
1693 qemu_put_be32s(f
, &s
->pointer
);
1694 qemu_put_be32s(f
, &s
->cu_base
);
1695 qemu_put_be32s(f
, &s
->cu_offset
);
1696 qemu_put_be32s(f
, &s
->ru_base
);
1697 qemu_put_be32s(f
, &s
->ru_offset
);
1698 qemu_put_be32s(f
, &s
->statsaddr
);
1699 /* Save epro100_stats_t statistics. */
1700 qemu_put_be32s(f
, &s
->statistics
.tx_good_frames
);
1701 qemu_put_be32s(f
, &s
->statistics
.tx_max_collisions
);
1702 qemu_put_be32s(f
, &s
->statistics
.tx_late_collisions
);
1703 qemu_put_be32s(f
, &s
->statistics
.tx_underruns
);
1704 qemu_put_be32s(f
, &s
->statistics
.tx_lost_crs
);
1705 qemu_put_be32s(f
, &s
->statistics
.tx_deferred
);
1706 qemu_put_be32s(f
, &s
->statistics
.tx_single_collisions
);
1707 qemu_put_be32s(f
, &s
->statistics
.tx_multiple_collisions
);
1708 qemu_put_be32s(f
, &s
->statistics
.tx_total_collisions
);
1709 qemu_put_be32s(f
, &s
->statistics
.rx_good_frames
);
1710 qemu_put_be32s(f
, &s
->statistics
.rx_crc_errors
);
1711 qemu_put_be32s(f
, &s
->statistics
.rx_alignment_errors
);
1712 qemu_put_be32s(f
, &s
->statistics
.rx_resource_errors
);
1713 qemu_put_be32s(f
, &s
->statistics
.rx_overrun_errors
);
1714 qemu_put_be32s(f
, &s
->statistics
.rx_cdt_errors
);
1715 qemu_put_be32s(f
, &s
->statistics
.rx_short_frame_errors
);
1716 qemu_put_be32s(f
, &s
->statistics
.fc_xmt_pause
);
1717 qemu_put_be32s(f
, &s
->statistics
.fc_rcv_pause
);
1718 qemu_put_be32s(f
, &s
->statistics
.fc_rcv_unsupported
);
1719 qemu_put_be16s(f
, &s
->statistics
.xmt_tco_frames
);
1720 qemu_put_be16s(f
, &s
->statistics
.rcv_tco_frames
);
1721 qemu_put_be32s(f
, &s
->statistics
.complete
);
1723 qemu_put_be16s(f
, &s
->status
);
1726 /* Configuration bytes. */
1727 qemu_put_buffer(f
, s
->configuration
, sizeof(s
->configuration
));
1730 static void nic_cleanup(VLANClientState
*vc
)
1732 EEPRO100State
*s
= vc
->opaque
;
1734 unregister_savevm(vc
->model
, s
);
1736 eeprom93xx_free(s
->eeprom
);
1739 static int pci_nic_uninit(PCIDevice
*pci_dev
)
1741 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1743 cpu_unregister_io_memory(s
->mmio_index
);
1748 static int nic_init(PCIDevice
*pci_dev
, uint32_t device
)
1750 EEPRO100State
*s
= DO_UPCAST(EEPRO100State
, dev
, pci_dev
);
1752 TRACE(OTHER
, logout("\n"));
1758 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1759 * i82559 and later support 64 or 256 word EEPROM. */
1760 s
->eeprom
= eeprom93xx_new(EEPROM_SIZE
);
1762 /* Handler for memory-mapped I/O */
1764 cpu_register_io_memory(pci_mmio_read
, pci_mmio_write
, s
);
1766 pci_register_bar(&s
->dev
, 0, PCI_MEM_SIZE
,
1767 PCI_ADDRESS_SPACE_MEM
|
1768 PCI_ADDRESS_SPACE_MEM_PREFETCH
, pci_mmio_map
);
1769 pci_register_bar(&s
->dev
, 1, PCI_IO_SIZE
, PCI_ADDRESS_SPACE_IO
,
1771 pci_register_bar(&s
->dev
, 2, PCI_FLASH_SIZE
, PCI_ADDRESS_SPACE_MEM
,
1774 qdev_get_macaddr(&s
->dev
.qdev
, s
->macaddr
);
1775 logout("macaddr: %s\n", nic_dump(&s
->macaddr
[0], 6));
1776 assert(s
->region
[1] == 0);
1780 s
->vc
= qdev_get_vlan_client(&s
->dev
.qdev
,
1781 nic_can_receive
, nic_receive
, NULL
,
1784 qemu_format_nic_info_str(s
->vc
, s
->macaddr
);
1785 TRACE(OTHER
, logout("%s\n", s
->vc
->info_str
));
1787 qemu_register_reset(nic_reset
, s
);
1789 register_savevm(s
->vc
->model
, -1, 3, nic_save
, nic_load
, s
);
1793 static int pci_i82550_init(PCIDevice
*pci_dev
)
1795 return nic_init(pci_dev
, i82550
);
1798 static int pci_i82551_init(PCIDevice
*pci_dev
)
1800 return nic_init(pci_dev
, i82551
);
1803 static int pci_i82557a_init(PCIDevice
*pci_dev
)
1805 return nic_init(pci_dev
, i82557A
);
1808 static int pci_i82557b_init(PCIDevice
*pci_dev
)
1810 return nic_init(pci_dev
, i82557B
);
1813 static int pci_i82557c_init(PCIDevice
*pci_dev
)
1815 return nic_init(pci_dev
, i82557C
);
1818 static int pci_i82558a_init(PCIDevice
*pci_dev
)
1820 return nic_init(pci_dev
, i82558A
);
1823 static int pci_i82558b_init(PCIDevice
*pci_dev
)
1825 return nic_init(pci_dev
, i82558B
);
1828 static int pci_i82559a_init(PCIDevice
*pci_dev
)
1830 return nic_init(pci_dev
, i82559A
);
1833 static int pci_i82559b_init(PCIDevice
*pci_dev
)
1835 return nic_init(pci_dev
, i82559B
);
1838 static int pci_i82559c_init(PCIDevice
*pci_dev
)
1840 return nic_init(pci_dev
, i82559C
);
1843 static int pci_i82559er_init(PCIDevice
*pci_dev
)
1845 return nic_init(pci_dev
, i82559ER
);
1848 static int pci_i82562_init(PCIDevice
*pci_dev
)
1850 return nic_init(pci_dev
, i82562
);
1853 static PCIDeviceInfo eepro100_info
[] = {
1855 .qdev
.name
= "i82550",
1856 .qdev
.size
= sizeof(EEPRO100State
),
1857 .init
= pci_i82550_init
,
1859 .qdev
.name
= "i82551",
1860 .qdev
.size
= sizeof(EEPRO100State
),
1861 .init
= pci_i82551_init
,
1862 .exit
= pci_nic_uninit
,
1864 .qdev
.name
= "i82557a",
1865 .qdev
.size
= sizeof(EEPRO100State
),
1866 .init
= pci_i82557a_init
,
1868 .qdev
.name
= "i82557b",
1869 .qdev
.size
= sizeof(EEPRO100State
),
1870 .init
= pci_i82557b_init
,
1871 .exit
= pci_nic_uninit
,
1873 .qdev
.name
= "i82557c",
1874 .qdev
.size
= sizeof(EEPRO100State
),
1875 .init
= pci_i82557c_init
,
1877 .qdev
.name
= "i82558a",
1878 .qdev
.size
= sizeof(EEPRO100State
),
1879 .init
= pci_i82558a_init
,
1881 .qdev
.name
= "i82558b",
1882 .qdev
.size
= sizeof(EEPRO100State
),
1883 .init
= pci_i82558b_init
,
1885 .qdev
.name
= "i82559a",
1886 .qdev
.size
= sizeof(EEPRO100State
),
1887 .init
= pci_i82559a_init
,
1889 .qdev
.name
= "i82559b",
1890 .qdev
.size
= sizeof(EEPRO100State
),
1891 .init
= pci_i82559b_init
,
1893 .qdev
.name
= "i82559c",
1894 .qdev
.size
= sizeof(EEPRO100State
),
1895 .init
= pci_i82559c_init
,
1897 .qdev
.name
= "i82559er",
1898 .qdev
.size
= sizeof(EEPRO100State
),
1899 .init
= pci_i82559er_init
,
1900 .exit
= pci_nic_uninit
,
1902 .qdev
.name
= "i82562",
1903 .qdev
.size
= sizeof(EEPRO100State
),
1904 .init
= pci_i82562_init
,
1910 static void eepro100_register_devices(void)
1912 pci_qdev_register_many(eepro100_info
);
1915 device_init(eepro100_register_devices
)