include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef EXEC_ALL_H
  21 #define EXEC_ALL_H
  22
  23 #include "cpu.h"
  24 #if defined(CONFIG_USER_ONLY)
  25 #include "exec/abi_ptr.h"
  26 #include "exec/cpu_ldst.h"
  27 #endif
  28 #include "exec/mmu-access-type.h"
  29 #include "exec/translation-block.h"
  30 #include "qemu/clang-tsa.h"
  31
  32 /* Get a backtrace for the guest code. */
  33 const char *qemu_sprint_backtrace(char *buffer, size_t length);
  34
  35 /**
  36  * cpu_loop_exit_requested:
  37  * @cpu: The CPU state to be tested
  38  *
  39  * Indicate if somebody asked for a return of the CPU to the main loop
  40  * (e.g., via cpu_exit() or cpu_interrupt()).
  41  *
  42  * This is helpful for architectures that support interruptible
  43  * instructions. After writing back all state to registers/memory, this
  44  * call can be used to check if it makes sense to return to the main loop
  45  * or to continue executing the interruptible instruction.
  46  */
  47 static inline bool cpu_loop_exit_requested(CPUState *cpu)
  48 {
  49     return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0;
  50 }
  51
  52 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
  53 /* cputlb.c */
  54 /**
  55  * tlb_init - initialize a CPU's TLB
  56  * @cpu: CPU whose TLB should be initialized
  57  */
  58 void tlb_init(CPUState *cpu);
  59 /**
  60  * tlb_destroy - destroy a CPU's TLB
  61  * @cpu: CPU whose TLB should be destroyed
  62  */
  63 void tlb_destroy(CPUState *cpu);
  64 /**
  65  * tlb_flush_page:
  66  * @cpu: CPU whose TLB should be flushed
  67  * @addr: virtual address of page to be flushed
  68  *
  69  * Flush one page from the TLB of the specified CPU, for all
  70  * MMU indexes.
  71  */
  72 void tlb_flush_page(CPUState *cpu, vaddr addr);
  73 /**
  74  * tlb_flush_page_all_cpus_synced:
  75  * @cpu: src CPU of the flush
  76  * @addr: virtual address of page to be flushed
  77  *
  78  * Flush one page from the TLB of all CPUs, for all
  79  * MMU indexes.
  80  *
  81  * When this function returns, no CPUs will subsequently perform
  82  * translations using the flushed TLBs.
  83  */
  84 void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
  85 /**
  86  * tlb_flush:
  87  * @cpu: CPU whose TLB should be flushed
  88  *
  89  * Flush the entire TLB for the specified CPU. Most CPU architectures
  90  * allow the implementation to drop entries from the TLB at any time
  91  * so this is generally safe. If more selective flushing is required
  92  * use one of the other functions for efficiency.
  93  */
  94 void tlb_flush(CPUState *cpu);
  95 /**
  96  * tlb_flush_all_cpus_synced:
  97  * @cpu: src CPU of the flush
  98  *
  99  * Flush the entire TLB for all CPUs, for all MMU indexes.
 100  *
 101  * When this function returns, no CPUs will subsequently perform
 102  * translations using the flushed TLBs.
 103  */
 104 void tlb_flush_all_cpus_synced(CPUState *src_cpu);
 105 /**
 106  * tlb_flush_page_by_mmuidx:
 107  * @cpu: CPU whose TLB should be flushed
 108  * @addr: virtual address of page to be flushed
 109  * @idxmap: bitmap of MMU indexes to flush
 110  *
 111  * Flush one page from the TLB of the specified CPU, for the specified
 112  * MMU indexes.
 113  */
 114 void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
 115                               uint16_t idxmap);
 116 /**
 117  * tlb_flush_page_by_mmuidx_all_cpus_synced:
 118  * @cpu: Originating CPU of the flush
 119  * @addr: virtual address of page to be flushed
 120  * @idxmap: bitmap of MMU indexes to flush
 121  *
 122  * Flush one page from the TLB of all CPUs, for the specified
 123  * MMU indexes.
 124  *
 125  * When this function returns, no CPUs will subsequently perform
 126  * translations using the flushed TLBs.
 127  */
 128 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
 129                                               uint16_t idxmap);
 130 /**
 131  * tlb_flush_by_mmuidx:
 132  * @cpu: CPU whose TLB should be flushed
 133  * @wait: If true ensure synchronisation by exiting the cpu_loop
 134  * @idxmap: bitmap of MMU indexes to flush
 135  *
 136  * Flush all entries from the TLB of the specified CPU, for the specified
 137  * MMU indexes.
 138  */
 139 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
 140 /**
 141  * tlb_flush_by_mmuidx_all_cpus_synced:
 142  * @cpu: Originating CPU of the flush
 143  * @idxmap: bitmap of MMU indexes to flush
 144  *
 145  * Flush all entries from the TLB of all CPUs, for the specified
 146  * MMU indexes.
 147  *
 148  * When this function returns, no CPUs will subsequently perform
 149  * translations using the flushed TLBs.
 150  */
 151 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
 152
 153 /**
 154  * tlb_flush_page_bits_by_mmuidx
 155  * @cpu: CPU whose TLB should be flushed
 156  * @addr: virtual address of page to be flushed
 157  * @idxmap: bitmap of mmu indexes to flush
 158  * @bits: number of significant bits in address
 159  *
 160  * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
 161  */
 162 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
 163                                    uint16_t idxmap, unsigned bits);
 164
 165 /* Similarly, with broadcast and syncing. */
 166 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
 167     (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits);
 168
 169 /**
 170  * tlb_flush_range_by_mmuidx
 171  * @cpu: CPU whose TLB should be flushed
 172  * @addr: virtual address of the start of the range to be flushed
 173  * @len: length of range to be flushed
 174  * @idxmap: bitmap of mmu indexes to flush
 175  * @bits: number of significant bits in address
 176  *
 177  * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
 178  * comparing only the low @bits worth of each virtual page.
 179  */
 180 void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
 181                                vaddr len, uint16_t idxmap,
 182                                unsigned bits);
 183
 184 /* Similarly, with broadcast and syncing. */
 185 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 186                                                vaddr addr,
 187                                                vaddr len,
 188                                                uint16_t idxmap,
 189                                                unsigned bits);
 190
 191 /**
 192  * tlb_set_page_full:
 193  * @cpu: CPU context
 194  * @mmu_idx: mmu index of the tlb to modify
 195  * @addr: virtual address of the entry to add
 196  * @full: the details of the tlb entry
 197  *
 198  * Add an entry to @cpu tlb index @mmu_idx.  All of the fields of
 199  * @full must be filled, except for xlat_section, and constitute
 200  * the complete description of the translated page.
 201  *
 202  * This is generally called by the target tlb_fill function after
 203  * having performed a successful page table walk to find the physical
 204  * address and attributes for the translation.
 205  *
 206  * At most one entry for a given virtual address is permitted. Only a
 207  * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
 208  * used by tlb_flush_page.
 209  */
 210 void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
 211                        CPUTLBEntryFull *full);
 212
 213 /**
 214  * tlb_set_page_with_attrs:
 215  * @cpu: CPU to add this TLB entry for
 216  * @addr: virtual address of page to add entry for
 217  * @paddr: physical address of the page
 218  * @attrs: memory transaction attributes
 219  * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
 220  * @mmu_idx: MMU index to insert TLB entry for
 221  * @size: size of the page in bytes
 222  *
 223  * Add an entry to this CPU's TLB (a mapping from virtual address
 224  * @addr to physical address @paddr) with the specified memory
 225  * transaction attributes. This is generally called by the target CPU
 226  * specific code after it has been called through the tlb_fill()
 227  * entry point and performed a successful page table walk to find
 228  * the physical address and attributes for the virtual address
 229  * which provoked the TLB miss.
 230  *
 231  * At most one entry for a given virtual address is permitted. Only a
 232  * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
 233  * used by tlb_flush_page.
 234  */
 235 void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
 236                              hwaddr paddr, MemTxAttrs attrs,
 237                              int prot, int mmu_idx, vaddr size);
 238 /* tlb_set_page:
 239  *
 240  * This function is equivalent to calling tlb_set_page_with_attrs()
 241  * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
 242  * as a convenience for CPUs which don't use memory transaction attributes.
 243  */
 244 void tlb_set_page(CPUState *cpu, vaddr addr,
 245                   hwaddr paddr, int prot,
 246                   int mmu_idx, vaddr size);
 247 #else
 248 static inline void tlb_init(CPUState *cpu)
 249 {
 250 }
 251 static inline void tlb_destroy(CPUState *cpu)
 252 {
 253 }
 254 static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
 255 {
 256 }
 257 static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
 258 {
 259 }
 260 static inline void tlb_flush(CPUState *cpu)
 261 {
 262 }
 263 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
 264 {
 265 }
 266 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
 267                                             vaddr addr, uint16_t idxmap)
 268 {
 269 }
 270
 271 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
 272 {
 273 }
 274 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
 275                                                             vaddr addr,
 276                                                             uint16_t idxmap)
 277 {
 278 }
 279 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
 280                                                        uint16_t idxmap)
 281 {
 282 }
 283 static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
 284                                                  vaddr addr,
 285                                                  uint16_t idxmap,
 286                                                  unsigned bits)
 287 {
 288 }
 289 static inline void
 290 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
 291                                               uint16_t idxmap, unsigned bits)
 292 {
 293 }
 294 static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
 295                                              vaddr len, uint16_t idxmap,
 296                                              unsigned bits)
 297 {
 298 }
 299 static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
 300                                                              vaddr addr,
 301                                                              vaddr len,
 302                                                              uint16_t idxmap,
 303                                                              unsigned bits)
 304 {
 305 }
 306 #endif
 307 /**
 308  * probe_access:
 309  * @env: CPUArchState
 310  * @addr: guest virtual address to look up
 311  * @size: size of the access
 312  * @access_type: read, write or execute permission
 313  * @mmu_idx: MMU index to use for lookup
 314  * @retaddr: return address for unwinding
 315  *
 316  * Look up the guest virtual address @addr.  Raise an exception if the
 317  * page does not satisfy @access_type.  Raise an exception if the
 318  * access (@addr, @size) hits a watchpoint.  For writes, mark a clean
 319  * page as dirty.
 320  *
 321  * Finally, return the host address for a page that is backed by RAM,
 322  * or NULL if the page requires I/O.
 323  */
 324 void *probe_access(CPUArchState *env, vaddr addr, int size,
 325                    MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
 326
 327 static inline void *probe_write(CPUArchState *env, vaddr addr, int size,
 328                                 int mmu_idx, uintptr_t retaddr)
 329 {
 330     return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr);
 331 }
 332
 333 static inline void *probe_read(CPUArchState *env, vaddr addr, int size,
 334                                int mmu_idx, uintptr_t retaddr)
 335 {
 336     return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
 337 }
 338
 339 /**
 340  * probe_access_flags:
 341  * @env: CPUArchState
 342  * @addr: guest virtual address to look up
 343  * @size: size of the access
 344  * @access_type: read, write or execute permission
 345  * @mmu_idx: MMU index to use for lookup
 346  * @nonfault: suppress the fault
 347  * @phost: return value for host address
 348  * @retaddr: return address for unwinding
 349  *
 350  * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for
 351  * the page, and storing the host address for RAM in @phost.
 352  *
 353  * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK.
 354  * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags.
 355  * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
 356  * For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
 357  */
 358 int probe_access_flags(CPUArchState *env, vaddr addr, int size,
 359                        MMUAccessType access_type, int mmu_idx,
 360                        bool nonfault, void **phost, uintptr_t retaddr);
 361
 362 #ifndef CONFIG_USER_ONLY
 363 /**
 364  * probe_access_full:
 365  * Like probe_access_flags, except also return into @pfull.
 366  *
 367  * The CPUTLBEntryFull structure returned via @pfull is transient
 368  * and must be consumed or copied immediately, before any further
 369  * access or changes to TLB @mmu_idx.
 370  */
 371 int probe_access_full(CPUArchState *env, vaddr addr, int size,
 372                       MMUAccessType access_type, int mmu_idx,
 373                       bool nonfault, void **phost,
 374                       CPUTLBEntryFull **pfull, uintptr_t retaddr);
 375
 376 /**
 377  * probe_access_mmu() - Like probe_access_full except cannot fault and
 378  * doesn't trigger instrumentation.
 379  *
 380  * @env: CPUArchState
 381  * @vaddr: virtual address to probe
 382  * @size: size of the probe
 383  * @access_type: read, write or execute permission
 384  * @mmu_idx: softmmu index
 385  * @phost: ptr to return value host address or NULL
 386  * @pfull: ptr to return value CPUTLBEntryFull structure or NULL
 387  *
 388  * The CPUTLBEntryFull structure returned via @pfull is transient
 389  * and must be consumed or copied immediately, before any further
 390  * access or changes to TLB @mmu_idx.
 391  *
 392  * Returns: TLB flags as per probe_access_flags()
 393  */
 394 int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size,
 395                           MMUAccessType access_type, int mmu_idx,
 396                           void **phost, CPUTLBEntryFull **pfull);
 397
 398 #endif
 399
 400 static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb)
 401 {
 402 #ifdef CONFIG_USER_ONLY
 403     return tb->itree.start;
 404 #else
 405     return tb->page_addr[0];
 406 #endif
 407 }
 408
 409 static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb)
 410 {
 411 #ifdef CONFIG_USER_ONLY
 412     tb_page_addr_t next = tb->itree.last & TARGET_PAGE_MASK;
 413     return next == (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next;
 414 #else
 415     return tb->page_addr[1];
 416 #endif
 417 }
 418
 419 static inline void tb_set_page_addr0(TranslationBlock *tb,
 420                                      tb_page_addr_t addr)
 421 {
 422 #ifdef CONFIG_USER_ONLY
 423     tb->itree.start = addr;
 424     /*
 425      * To begin, we record an interval of one byte.  When the translation
 426      * loop encounters a second page, the interval will be extended to
 427      * include the first byte of the second page, which is sufficient to
 428      * allow tb_page_addr1() above to work properly.  The final corrected
 429      * interval will be set by tb_page_add() from tb->size before the
 430      * node is added to the interval tree.
 431      */
 432     tb->itree.last = addr;
 433 #else
 434     tb->page_addr[0] = addr;
 435 #endif
 436 }
 437
 438 static inline void tb_set_page_addr1(TranslationBlock *tb,
 439                                      tb_page_addr_t addr)
 440 {
 441 #ifdef CONFIG_USER_ONLY
 442     /* Extend the interval to the first byte of the second page.  See above. */
 443     tb->itree.last = addr;
 444 #else
 445     tb->page_addr[1] = addr;
 446 #endif
 447 }
 448
 449 /* TranslationBlock invalidate API */
 450 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 451 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last);
 452 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
 453
 454 /* GETPC is the true target of the return instruction that we'll execute.  */
 455 #if defined(CONFIG_TCG_INTERPRETER)
 456 extern __thread uintptr_t tci_tb_ptr;
 457 # define GETPC() tci_tb_ptr
 458 #else
 459 # define GETPC() \
 460     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 461 #endif
 462
 463 /* The true return address will often point to a host insn that is part of
 464    the next translated guest insn.  Adjust the address backward to point to
 465    the middle of the call insn.  Subtracting one would do the job except for
 466    several compressed mode architectures (arm, mips) which set the low bit
 467    to indicate the compressed mode; subtracting two works around that.  It
 468    is also the case that there are no host isas that contain a call insn
 469    smaller than 4 bytes, so we don't worry about special-casing this.  */
 470 #define GETPC_ADJ   2
 471
 472 #if !defined(CONFIG_USER_ONLY)
 473
 474 /**
 475  * iotlb_to_section:
 476  * @cpu: CPU performing the access
 477  * @index: TCG CPU IOTLB entry
 478  *
 479  * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that
 480  * it refers to. @index will have been initially created and returned
 481  * by memory_region_section_get_iotlb().
 482  */
 483 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
 484                                              hwaddr index, MemTxAttrs attrs);
 485 #endif
 486
 487 /**
 488  * get_page_addr_code_hostp()
 489  * @env: CPUArchState
 490  * @addr: guest virtual address of guest code
 491  *
 492  * See get_page_addr_code() (full-system version) for documentation on the
 493  * return value.
 494  *
 495  * Sets *@hostp (when @hostp is non-NULL) as follows.
 496  * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
 497  * to the host address where @addr's content is kept.
 498  *
 499  * Note: this function can trigger an exception.
 500  */
 501 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr,
 502                                         void **hostp);
 503
 504 /**
 505  * get_page_addr_code()
 506  * @env: CPUArchState
 507  * @addr: guest virtual address of guest code
 508  *
 509  * If we cannot translate and execute from the entire RAM page, or if
 510  * the region is not backed by RAM, returns -1. Otherwise, returns the
 511  * ram_addr_t corresponding to the guest code at @addr.
 512  *
 513  * Note: this function can trigger an exception.
 514  */
 515 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
 516                                                 vaddr addr)
 517 {
 518     return get_page_addr_code_hostp(env, addr, NULL);
 519 }
 520
 521 #if defined(CONFIG_USER_ONLY)
 522 void TSA_NO_TSA mmap_lock(void);
 523 void TSA_NO_TSA mmap_unlock(void);
 524 bool have_mmap_lock(void);
 525
 526 static inline void mmap_unlock_guard(void *unused)
 527 {
 528     mmap_unlock();
 529 }
 530
 531 #define WITH_MMAP_LOCK_GUARD()                                            \
 532     for (int _mmap_lock_iter __attribute__((cleanup(mmap_unlock_guard)))  \
 533          = (mmap_lock(), 0); _mmap_lock_iter == 0; _mmap_lock_iter = 1)
 534
 535 /**
 536  * adjust_signal_pc:
 537  * @pc: raw pc from the host signal ucontext_t.
 538  * @is_write: host memory operation was write, or read-modify-write.
 539  *
 540  * Alter @pc as required for unwinding.  Return the type of the
 541  * guest memory access -- host reads may be for guest execution.
 542  */
 543 MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
 544
 545 /**
 546  * handle_sigsegv_accerr_write:
 547  * @cpu: the cpu context
 548  * @old_set: the sigset_t from the signal ucontext_t
 549  * @host_pc: the host pc, adjusted for the signal
 550  * @host_addr: the host address of the fault
 551  *
 552  * Return true if the write fault has been handled, and should be re-tried.
 553  */
 554 bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
 555                                  uintptr_t host_pc, abi_ptr guest_addr);
 556
 557 /**
 558  * cpu_loop_exit_sigsegv:
 559  * @cpu: the cpu context
 560  * @addr: the guest address of the fault
 561  * @access_type: access was read/write/execute
 562  * @maperr: true for invalid page, false for permission fault
 563  * @ra: host pc for unwinding
 564  *
 565  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 566  * specific things to raise SIGSEGV, and jump to the main cpu loop.
 567  */
 568 G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
 569                                       MMUAccessType access_type,
 570                                       bool maperr, uintptr_t ra);
 571
 572 /**
 573  * cpu_loop_exit_sigbus:
 574  * @cpu: the cpu context
 575  * @addr: the guest address of the alignment fault
 576  * @access_type: access was read/write/execute
 577  * @ra: host pc for unwinding
 578  *
 579  * Use the TCGCPUOps hook to record cpu state, do guest operating system
 580  * specific things to raise SIGBUS, and jump to the main cpu loop.
 581  */
 582 G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
 583                                      MMUAccessType access_type,
 584                                      uintptr_t ra);
 585
 586 #else
 587 static inline void mmap_lock(void) {}
 588 static inline void mmap_unlock(void) {}
 589 #define WITH_MMAP_LOCK_GUARD()
 590
 591 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
 592 void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);
 593
 594 MemoryRegionSection *
 595 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
 596                                   hwaddr *xlat, hwaddr *plen,
 597                                   MemTxAttrs attrs, int *prot);
 598 hwaddr memory_region_section_get_iotlb(CPUState *cpu,
 599                                        MemoryRegionSection *section);
 600 #endif
 601
 602 #endif