4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
24 #include "hw/pci/pci_bridge.h"
25 #include "hw/pci/pcie.h"
26 #include "hw/pci/msix.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/pci/pcie_regs.h"
30 #include "hw/pci/pcie_port.h"
31 #include "qemu/range.h"
35 # define PCIE_DPRINTF(fmt, ...) \
36 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
38 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
40 #define PCIE_DEV_PRINTF(dev, fmt, ...) \
41 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
44 /***************************************************************************
45 * pci express capability helper functions
49 pcie_cap_v1_fill(PCIDevice
*dev
, uint8_t port
, uint8_t type
, uint8_t version
)
51 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
52 uint8_t *cmask
= dev
->cmask
+ dev
->exp
.exp_cap
;
54 /* capability register
55 interrupt message number defaults to 0 */
56 pci_set_word(exp_cap
+ PCI_EXP_FLAGS
,
57 ((type
<< PCI_EXP_FLAGS_TYPE_SHIFT
) & PCI_EXP_FLAGS_TYPE
) |
60 /* device capability register
62 * roll based error reporting bit must be set by all
63 * Functions conforming to the ECN, PCI Express Base
64 * Specification, Revision 1.1., or subsequent PCI Express Base
65 * Specification revisions.
67 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP
, PCI_EXP_DEVCAP_RBER
);
69 pci_set_long(exp_cap
+ PCI_EXP_LNKCAP
,
70 (port
<< PCI_EXP_LNKCAP_PN_SHIFT
) |
71 PCI_EXP_LNKCAP_ASPMS_0S
|
72 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1
) |
73 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT
));
75 pci_set_word(exp_cap
+ PCI_EXP_LNKSTA
,
76 QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1
) |
77 QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT
));
79 if (dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
80 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
81 PCI_EXP_LNKSTA_DLLLA
);
84 /* We changed link status bits over time, and changing them across
85 * migrations is generally fine as hardware changes them too.
86 * Let's not bother checking.
88 pci_set_word(cmask
+ PCI_EXP_LNKSTA
, 0);
91 static void pcie_cap_fill_slot_lnk(PCIDevice
*dev
)
93 PCIESlot
*s
= (PCIESlot
*)object_dynamic_cast(OBJECT(dev
), TYPE_PCIE_SLOT
);
94 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
96 /* Skip anything that isn't a PCIESlot */
101 /* Clear and fill LNKCAP from what was configured above */
102 pci_long_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKCAP
,
103 PCI_EXP_LNKCAP_MLW
| PCI_EXP_LNKCAP_SLS
);
104 pci_long_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCAP
,
105 QEMU_PCI_EXP_LNKCAP_MLW(s
->width
) |
106 QEMU_PCI_EXP_LNKCAP_MLS(s
->speed
));
109 * Link bandwidth notification is required for all root ports and
110 * downstream ports supporting links wider than x1 or multiple link
113 if (s
->width
> QEMU_PCI_EXP_LNK_X1
||
114 s
->speed
> QEMU_PCI_EXP_LNK_2_5GT
) {
115 pci_long_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCAP
,
116 PCI_EXP_LNKCAP_LBNC
);
119 if (s
->speed
> QEMU_PCI_EXP_LNK_2_5GT
) {
121 * Hot-plug capable downstream ports and downstream ports supporting
122 * link speeds greater than 5GT/s must hardwire PCI_EXP_LNKCAP_DLLLARC
123 * to 1b. PCI_EXP_LNKCAP_DLLLARC implies PCI_EXP_LNKSTA_DLLLA, which
124 * we also hardwire to 1b here. 2.5GT/s hot-plug slots should also
125 * technically implement this, but it's not done here for compatibility.
127 pci_long_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCAP
,
128 PCI_EXP_LNKCAP_DLLLARC
);
129 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
130 PCI_EXP_LNKSTA_DLLLA
);
133 * Target Link Speed defaults to the highest link speed supported by
134 * the component. 2.5GT/s devices are permitted to hardwire to zero.
136 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKCTL2
,
137 PCI_EXP_LNKCTL2_TLS
);
138 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCTL2
,
139 QEMU_PCI_EXP_LNKCAP_MLS(s
->speed
) &
140 PCI_EXP_LNKCTL2_TLS
);
144 * 2.5 & 5.0GT/s can be fully described by LNKCAP, but 8.0GT/s is
145 * actually a reference to the highest bit supported in this register.
146 * We assume the device supports all link speeds.
148 if (s
->speed
> QEMU_PCI_EXP_LNK_5GT
) {
149 pci_long_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKCAP2
, ~0U);
150 pci_long_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCAP2
,
151 PCI_EXP_LNKCAP2_SLS_2_5GB
|
152 PCI_EXP_LNKCAP2_SLS_5_0GB
|
153 PCI_EXP_LNKCAP2_SLS_8_0GB
);
154 if (s
->speed
> QEMU_PCI_EXP_LNK_8GT
) {
155 pci_long_test_and_set_mask(exp_cap
+ PCI_EXP_LNKCAP2
,
156 PCI_EXP_LNKCAP2_SLS_16_0GB
);
161 int pcie_cap_init(PCIDevice
*dev
, uint8_t offset
,
162 uint8_t type
, uint8_t port
,
165 /* PCIe cap v2 init */
169 assert(pci_is_express(dev
));
171 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
,
172 PCI_EXP_VER2_SIZEOF
, errp
);
176 dev
->exp
.exp_cap
= pos
;
177 exp_cap
= dev
->config
+ pos
;
179 /* Filling values common with v1 */
180 pcie_cap_v1_fill(dev
, port
, type
, PCI_EXP_FLAGS_VER2
);
182 /* Fill link speed and width options */
183 pcie_cap_fill_slot_lnk(dev
);
185 /* Filling v2 specific values */
186 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP2
,
187 PCI_EXP_DEVCAP2_EFF
| PCI_EXP_DEVCAP2_EETLPP
);
189 pci_set_word(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
, PCI_EXP_DEVCTL2_EETLPPB
);
191 if (dev
->cap_present
& QEMU_PCIE_EXTCAP_INIT
) {
192 /* read-only to behave like a 'NULL' Extended Capability Header */
193 pci_set_long(dev
->wmask
+ PCI_CONFIG_SPACE_SIZE
, 0);
199 int pcie_cap_v1_init(PCIDevice
*dev
, uint8_t offset
, uint8_t type
,
202 /* PCIe cap v1 init */
204 Error
*local_err
= NULL
;
206 assert(pci_is_express(dev
));
208 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
,
209 PCI_EXP_VER1_SIZEOF
, &local_err
);
211 error_report_err(local_err
);
214 dev
->exp
.exp_cap
= pos
;
216 pcie_cap_v1_fill(dev
, port
, type
, PCI_EXP_FLAGS_VER1
);
222 pcie_endpoint_cap_common_init(PCIDevice
*dev
, uint8_t offset
, uint8_t cap_size
)
224 uint8_t type
= PCI_EXP_TYPE_ENDPOINT
;
225 Error
*local_err
= NULL
;
229 * Windows guests will report Code 10, device cannot start, if
230 * a regular Endpoint type is exposed on a root complex. These
231 * should instead be Root Complex Integrated Endpoints.
233 if (pci_bus_is_express(pci_get_bus(dev
))
234 && pci_bus_is_root(pci_get_bus(dev
))) {
235 type
= PCI_EXP_TYPE_RC_END
;
238 if (cap_size
== PCI_EXP_VER1_SIZEOF
) {
239 return pcie_cap_v1_init(dev
, offset
, type
, 0);
241 ret
= pcie_cap_init(dev
, offset
, type
, 0, &local_err
);
244 error_report_err(local_err
);
251 int pcie_endpoint_cap_init(PCIDevice
*dev
, uint8_t offset
)
253 return pcie_endpoint_cap_common_init(dev
, offset
, PCI_EXP_VER2_SIZEOF
);
256 int pcie_endpoint_cap_v1_init(PCIDevice
*dev
, uint8_t offset
)
258 return pcie_endpoint_cap_common_init(dev
, offset
, PCI_EXP_VER1_SIZEOF
);
261 void pcie_cap_exit(PCIDevice
*dev
)
263 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER2_SIZEOF
);
266 void pcie_cap_v1_exit(PCIDevice
*dev
)
268 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER1_SIZEOF
);
271 uint8_t pcie_cap_get_type(const PCIDevice
*dev
)
273 uint32_t pos
= dev
->exp
.exp_cap
;
275 return (pci_get_word(dev
->config
+ pos
+ PCI_EXP_FLAGS
) &
276 PCI_EXP_FLAGS_TYPE
) >> PCI_EXP_FLAGS_TYPE_SHIFT
;
280 /* pci express interrupt message number */
281 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
282 void pcie_cap_flags_set_vector(PCIDevice
*dev
, uint8_t vector
)
284 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
286 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_FLAGS
, PCI_EXP_FLAGS_IRQ
);
287 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_FLAGS
,
288 vector
<< PCI_EXP_FLAGS_IRQ_SHIFT
);
291 uint8_t pcie_cap_flags_get_vector(PCIDevice
*dev
)
293 return (pci_get_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_FLAGS
) &
294 PCI_EXP_FLAGS_IRQ
) >> PCI_EXP_FLAGS_IRQ_SHIFT
;
297 void pcie_cap_deverr_init(PCIDevice
*dev
)
299 uint32_t pos
= dev
->exp
.exp_cap
;
300 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP
,
301 PCI_EXP_DEVCAP_RBER
);
302 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL
,
303 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
304 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
305 pci_long_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_DEVSTA
,
306 PCI_EXP_DEVSTA_CED
| PCI_EXP_DEVSTA_NFED
|
307 PCI_EXP_DEVSTA_FED
| PCI_EXP_DEVSTA_URD
);
310 void pcie_cap_deverr_reset(PCIDevice
*dev
)
312 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
313 pci_long_test_and_clear_mask(devctl
,
314 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
315 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
318 void pcie_cap_lnkctl_init(PCIDevice
*dev
)
320 uint32_t pos
= dev
->exp
.exp_cap
;
321 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_LNKCTL
,
322 PCI_EXP_LNKCTL_CCC
| PCI_EXP_LNKCTL_ES
);
325 void pcie_cap_lnkctl_reset(PCIDevice
*dev
)
327 uint8_t *lnkctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_LNKCTL
;
328 pci_long_test_and_clear_mask(lnkctl
,
329 PCI_EXP_LNKCTL_CCC
| PCI_EXP_LNKCTL_ES
);
332 static void hotplug_event_update_event_status(PCIDevice
*dev
)
334 uint32_t pos
= dev
->exp
.exp_cap
;
335 uint8_t *exp_cap
= dev
->config
+ pos
;
336 uint16_t sltctl
= pci_get_word(exp_cap
+ PCI_EXP_SLTCTL
);
337 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
339 dev
->exp
.hpev_notified
= (sltctl
& PCI_EXP_SLTCTL_HPIE
) &&
340 (sltsta
& sltctl
& PCI_EXP_HP_EV_SUPPORTED
);
343 static void hotplug_event_notify(PCIDevice
*dev
)
345 bool prev
= dev
->exp
.hpev_notified
;
347 hotplug_event_update_event_status(dev
);
349 if (prev
== dev
->exp
.hpev_notified
) {
353 /* Note: the logic above does not take into account whether interrupts
354 * are masked. The result is that interrupt will be sent when it is
355 * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
356 * The Port may optionally send an MSI when there are hot-plug events that
357 * occur while interrupt generation is disabled, and interrupt generation is
358 * subsequently enabled. */
359 if (msix_enabled(dev
)) {
360 msix_notify(dev
, pcie_cap_flags_get_vector(dev
));
361 } else if (msi_enabled(dev
)) {
362 msi_notify(dev
, pcie_cap_flags_get_vector(dev
));
364 pci_set_irq(dev
, dev
->exp
.hpev_notified
);
368 static void hotplug_event_clear(PCIDevice
*dev
)
370 hotplug_event_update_event_status(dev
);
371 if (!msix_enabled(dev
) && !msi_enabled(dev
) && !dev
->exp
.hpev_notified
) {
372 pci_irq_deassert(dev
);
377 * A PCI Express Hot-Plug Event has occurred, so update slot status register
378 * and notify OS of the event if necessary.
380 * 6.7.3 PCI Express Hot-Plug Events
381 * 6.7.3.4 Software Notification of Hot-Plug Events
383 static void pcie_cap_slot_event(PCIDevice
*dev
, PCIExpressHotPlugEvent event
)
385 /* Minor optimization: if nothing changed - no event is needed. */
386 if (pci_word_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+
387 PCI_EXP_SLTSTA
, event
)) {
390 hotplug_event_notify(dev
);
393 static void pcie_cap_slot_plug_common(PCIDevice
*hotplug_dev
, DeviceState
*dev
,
394 uint8_t **exp_cap
, Error
**errp
)
396 *exp_cap
= hotplug_dev
->config
+ hotplug_dev
->exp
.exp_cap
;
397 uint16_t sltsta
= pci_get_word(*exp_cap
+ PCI_EXP_SLTSTA
);
399 PCIE_DEV_PRINTF(PCI_DEVICE(dev
), "hotplug state: 0x%x\n", sltsta
);
400 if (sltsta
& PCI_EXP_SLTSTA_EIS
) {
401 /* the slot is electromechanically locked.
402 * This error is propagated up to qdev and then to HMP/QMP.
404 error_setg_errno(errp
, EBUSY
, "slot is electromechanically locked");
408 void pcie_cap_slot_plug_cb(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
412 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
414 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev
), dev
, &exp_cap
, errp
);
416 /* Don't send event when device is enabled during qemu machine creation:
417 * it is present on boot, no hotplug event is necessary. We do send an
418 * event when the device is disabled later. */
419 if (!dev
->hotplugged
) {
420 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
422 if (pci_dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
423 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
424 PCI_EXP_LNKSTA_DLLLA
);
429 /* To enable multifunction hot-plug, we just ensure the function
430 * 0 added last. When function 0 is added, we set the sltsta and
431 * inform OS via event notification.
433 if (pci_get_function_0(pci_dev
)) {
434 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
436 if (pci_dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
437 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
,
438 PCI_EXP_LNKSTA_DLLLA
);
440 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev
),
441 PCI_EXP_HP_EV_PDC
| PCI_EXP_HP_EV_ABP
);
445 void pcie_cap_slot_unplug_cb(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
448 object_unparent(OBJECT(dev
));
451 static void pcie_unplug_device(PCIBus
*bus
, PCIDevice
*dev
, void *opaque
)
453 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(DEVICE(dev
));
455 hotplug_handler_unplug(hotplug_ctrl
, DEVICE(dev
), &error_abort
);
458 void pcie_cap_slot_unplug_request_cb(HotplugHandler
*hotplug_dev
,
459 DeviceState
*dev
, Error
**errp
)
462 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
463 PCIBus
*bus
= pci_get_bus(pci_dev
);
465 pcie_cap_slot_plug_common(PCI_DEVICE(hotplug_dev
), dev
, &exp_cap
, errp
);
467 /* In case user cancel the operation of multi-function hot-add,
468 * remove the function that is unexposed to guest individually,
469 * without interaction with guest.
471 if (pci_dev
->devfn
&&
473 pcie_unplug_device(bus
, pci_dev
, NULL
);
478 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev
));
481 /* pci express slot for pci express root/downstream port
482 PCI express capability slot registers */
483 void pcie_cap_slot_init(PCIDevice
*dev
, uint16_t slot
)
485 uint32_t pos
= dev
->exp
.exp_cap
;
487 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_FLAGS
,
490 pci_long_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
491 ~PCI_EXP_SLTCAP_PSN
);
492 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
493 (slot
<< PCI_EXP_SLTCAP_PSN_SHIFT
) |
501 if (dev
->cap_present
& QEMU_PCIE_SLTCAP_PCP
) {
502 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
504 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
506 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
510 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
513 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
514 PCI_EXP_SLTCTL_PIC_OFF
|
515 PCI_EXP_SLTCTL_AIC_OFF
);
516 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
519 PCI_EXP_SLTCTL_HPIE
|
520 PCI_EXP_SLTCTL_CCIE
|
521 PCI_EXP_SLTCTL_PDCE
|
522 PCI_EXP_SLTCTL_ABPE
);
523 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
524 * make the bit writable here in order to detect 1b is written.
525 * pcie_cap_slot_write_config() test-and-clear the bit, so
526 * this bit always returns 0 to the guest.
528 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
531 pci_word_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_SLTSTA
,
532 PCI_EXP_HP_EV_SUPPORTED
);
534 dev
->exp
.hpev_notified
= false;
536 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev
))),
540 void pcie_cap_slot_reset(PCIDevice
*dev
)
542 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
543 uint8_t port_type
= pcie_cap_get_type(dev
);
545 assert(port_type
== PCI_EXP_TYPE_DOWNSTREAM
||
546 port_type
== PCI_EXP_TYPE_ROOT_PORT
);
548 PCIE_DEV_PRINTF(dev
, "reset\n");
550 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
554 PCI_EXP_SLTCTL_HPIE
|
555 PCI_EXP_SLTCTL_CCIE
|
556 PCI_EXP_SLTCTL_PDCE
|
557 PCI_EXP_SLTCTL_ABPE
);
558 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
559 PCI_EXP_SLTCTL_AIC_OFF
);
561 if (dev
->cap_present
& QEMU_PCIE_SLTCAP_PCP
) {
562 /* Downstream ports enforce device number 0. */
563 bool populated
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
))->devices
[0];
567 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
570 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
574 pic
= populated
? PCI_EXP_SLTCTL_PIC_ON
: PCI_EXP_SLTCTL_PIC_OFF
;
575 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
, pic
);
578 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
579 PCI_EXP_SLTSTA_EIS
|/* on reset,
580 the lock is released */
585 hotplug_event_update_event_status(dev
);
588 void pcie_cap_slot_write_config(PCIDevice
*dev
,
589 uint32_t addr
, uint32_t val
, int len
)
591 uint32_t pos
= dev
->exp
.exp_cap
;
592 uint8_t *exp_cap
= dev
->config
+ pos
;
593 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
595 if (ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTSTA
, 2)) {
596 hotplug_event_clear(dev
);
599 if (!ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTCTL
, 2)) {
603 if (pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
604 PCI_EXP_SLTCTL_EIC
)) {
605 sltsta
^= PCI_EXP_SLTSTA_EIS
; /* toggle PCI_EXP_SLTSTA_EIS bit */
606 pci_set_word(exp_cap
+ PCI_EXP_SLTSTA
, sltsta
);
607 PCIE_DEV_PRINTF(dev
, "PCI_EXP_SLTCTL_EIC: "
608 "sltsta -> 0x%02"PRIx16
"\n",
613 * If the slot is polulated, power indicator is off and power
614 * controller is off, it is safe to detach the devices.
616 if ((sltsta
& PCI_EXP_SLTSTA_PDS
) && (val
& PCI_EXP_SLTCTL_PCC
) &&
617 ((val
& PCI_EXP_SLTCTL_PIC_OFF
) == PCI_EXP_SLTCTL_PIC_OFF
)) {
618 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
619 pci_for_each_device(sec_bus
, pci_bus_num(sec_bus
),
620 pcie_unplug_device
, NULL
);
622 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
624 if (dev
->cap_present
& QEMU_PCIE_LNKSTA_DLLLA
) {
625 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKSTA
,
626 PCI_EXP_LNKSTA_DLLLA
);
628 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
632 hotplug_event_notify(dev
);
635 * 6.7.3.2 Command Completed Events
637 * Software issues a command to a hot-plug capable Downstream Port by
638 * issuing a write transaction that targets any portion of the Port’s Slot
639 * Control register. A single write to the Slot Control register is
640 * considered to be a single command, even if the write affects more than
641 * one field in the Slot Control register. In response to this transaction,
642 * the Port must carry out the requested actions and then set the
643 * associated status field for the command completed event. */
645 /* Real hardware might take a while to complete requested command because
646 * physical movement would be involved like locking the electromechanical
647 * lock. However in our case, command is completed instantaneously above,
648 * so send a command completion event right now.
650 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_CCI
);
653 int pcie_cap_slot_post_load(void *opaque
, int version_id
)
655 PCIDevice
*dev
= opaque
;
656 hotplug_event_update_event_status(dev
);
660 void pcie_cap_slot_push_attention_button(PCIDevice
*dev
)
662 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_ABP
);
665 /* root control/capabilities/status. PME isn't emulated for now */
666 void pcie_cap_root_init(PCIDevice
*dev
)
668 pci_set_word(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
,
669 PCI_EXP_RTCTL_SECEE
| PCI_EXP_RTCTL_SENFEE
|
670 PCI_EXP_RTCTL_SEFEE
);
673 void pcie_cap_root_reset(PCIDevice
*dev
)
675 pci_set_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
, 0);
678 /* function level reset(FLR) */
679 void pcie_cap_flr_init(PCIDevice
*dev
)
681 pci_long_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCAP
,
684 /* Although reading BCR_FLR returns always 0,
685 * the bit is made writable here in order to detect the 1b is written
686 * pcie_cap_flr_write_config() test-and-clear the bit, so
687 * this bit always returns 0 to the guest.
689 pci_word_test_and_set_mask(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
,
690 PCI_EXP_DEVCTL_BCR_FLR
);
693 void pcie_cap_flr_write_config(PCIDevice
*dev
,
694 uint32_t addr
, uint32_t val
, int len
)
696 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
697 if (pci_get_word(devctl
) & PCI_EXP_DEVCTL_BCR_FLR
) {
698 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
699 so the handler can detect FLR by looking at this bit. */
700 pci_device_reset(dev
);
701 pci_word_test_and_clear_mask(devctl
, PCI_EXP_DEVCTL_BCR_FLR
);
705 /* Alternative Routing-ID Interpretation (ARI)
706 * forwarding support for root and downstream ports
708 void pcie_cap_arifwd_init(PCIDevice
*dev
)
710 uint32_t pos
= dev
->exp
.exp_cap
;
711 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP2
,
712 PCI_EXP_DEVCAP2_ARI
);
713 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
,
714 PCI_EXP_DEVCTL2_ARI
);
717 void pcie_cap_arifwd_reset(PCIDevice
*dev
)
719 uint8_t *devctl2
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
;
720 pci_long_test_and_clear_mask(devctl2
, PCI_EXP_DEVCTL2_ARI
);
723 bool pcie_cap_is_arifwd_enabled(const PCIDevice
*dev
)
725 if (!pci_is_express(dev
)) {
728 if (!dev
->exp
.exp_cap
) {
732 return pci_get_long(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
) &
736 /**************************************************************************
737 * pci express extended capability list management functions
738 * uint16_t ext_cap_id (16 bit)
739 * uint8_t cap_ver (4 bit)
740 * uint16_t cap_offset (12 bit)
741 * uint16_t ext_cap_size
744 /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */
745 static uint16_t pcie_find_capability_list(PCIDevice
*dev
, uint32_t cap_id
,
750 uint32_t header
= pci_get_long(dev
->config
+ PCI_CONFIG_SPACE_SIZE
);
753 /* no extended capability */
757 for (next
= PCI_CONFIG_SPACE_SIZE
; next
;
758 prev
= next
, next
= PCI_EXT_CAP_NEXT(header
)) {
760 assert(next
>= PCI_CONFIG_SPACE_SIZE
);
761 assert(next
<= PCIE_CONFIG_SPACE_SIZE
- 8);
763 header
= pci_get_long(dev
->config
+ next
);
764 if (PCI_EXT_CAP_ID(header
) == cap_id
) {
776 uint16_t pcie_find_capability(PCIDevice
*dev
, uint16_t cap_id
)
778 return pcie_find_capability_list(dev
, cap_id
, NULL
);
781 static void pcie_ext_cap_set_next(PCIDevice
*dev
, uint16_t pos
, uint16_t next
)
783 uint32_t header
= pci_get_long(dev
->config
+ pos
);
784 assert(!(next
& (PCI_EXT_CAP_ALIGN
- 1)));
785 header
= (header
& ~PCI_EXT_CAP_NEXT_MASK
) |
786 ((next
<< PCI_EXT_CAP_NEXT_SHIFT
) & PCI_EXT_CAP_NEXT_MASK
);
787 pci_set_long(dev
->config
+ pos
, header
);
791 * Caller must supply valid (offset, size) such that the range wouldn't
792 * overlap with other capability or other registers.
793 * This function doesn't check it.
795 void pcie_add_capability(PCIDevice
*dev
,
796 uint16_t cap_id
, uint8_t cap_ver
,
797 uint16_t offset
, uint16_t size
)
799 assert(offset
>= PCI_CONFIG_SPACE_SIZE
);
800 assert(offset
< offset
+ size
);
801 assert(offset
+ size
<= PCIE_CONFIG_SPACE_SIZE
);
803 assert(pci_is_express(dev
));
805 if (offset
!= PCI_CONFIG_SPACE_SIZE
) {
809 * 0xffffffff is not a valid cap id (it's a 16 bit field). use
810 * internally to find the last capability in the linked list.
812 pcie_find_capability_list(dev
, 0xffffffff, &prev
);
813 assert(prev
>= PCI_CONFIG_SPACE_SIZE
);
814 pcie_ext_cap_set_next(dev
, prev
, offset
);
816 pci_set_long(dev
->config
+ offset
, PCI_EXT_CAP(cap_id
, cap_ver
, 0));
818 /* Make capability read-only by default */
819 memset(dev
->wmask
+ offset
, 0, size
);
820 memset(dev
->w1cmask
+ offset
, 0, size
);
821 /* Check capability by default */
822 memset(dev
->cmask
+ offset
, 0xFF, size
);
826 * Sync the PCIe Link Status negotiated speed and width of a bridge with the
827 * downstream device. If downstream device is not present, re-write with the
828 * Link Capability fields. Limit width and speed to bridge capabilities for
829 * compatibility. Use config_read to access the downstream device since it
830 * could be an assigned device with volatile link information.
832 void pcie_sync_bridge_lnk(PCIDevice
*bridge_dev
)
834 PCIBridge
*br
= PCI_BRIDGE(bridge_dev
);
835 PCIBus
*bus
= pci_bridge_get_sec_bus(br
);
836 PCIDevice
*target
= bus
->devices
[0];
837 uint8_t *exp_cap
= bridge_dev
->config
+ bridge_dev
->exp
.exp_cap
;
838 uint16_t lnksta
, lnkcap
= pci_get_word(exp_cap
+ PCI_EXP_LNKCAP
);
840 if (!target
|| !target
->exp
.exp_cap
) {
843 lnksta
= target
->config_read(target
,
844 target
->exp
.exp_cap
+ PCI_EXP_LNKSTA
,
847 if ((lnksta
& PCI_EXP_LNKSTA_NLW
) > (lnkcap
& PCI_EXP_LNKCAP_MLW
)) {
848 lnksta
&= ~PCI_EXP_LNKSTA_NLW
;
849 lnksta
|= lnkcap
& PCI_EXP_LNKCAP_MLW
;
852 if ((lnksta
& PCI_EXP_LNKSTA_CLS
) > (lnkcap
& PCI_EXP_LNKCAP_SLS
)) {
853 lnksta
&= ~PCI_EXP_LNKSTA_CLS
;
854 lnksta
|= lnkcap
& PCI_EXP_LNKCAP_SLS
;
858 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_LNKSTA
,
859 PCI_EXP_LNKSTA_CLS
| PCI_EXP_LNKSTA_NLW
);
860 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_LNKSTA
, lnksta
&
861 (PCI_EXP_LNKSTA_CLS
| PCI_EXP_LNKSTA_NLW
));
864 /**************************************************************************
865 * pci express extended capability helper functions
869 void pcie_ari_init(PCIDevice
*dev
, uint16_t offset
, uint16_t nextfn
)
871 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ARI
, PCI_ARI_VER
,
872 offset
, PCI_ARI_SIZEOF
);
873 pci_set_long(dev
->config
+ offset
+ PCI_ARI_CAP
, (nextfn
& 0xff) << 8);
876 void pcie_dev_ser_num_init(PCIDevice
*dev
, uint16_t offset
, uint64_t ser_num
)
878 static const int pci_dsn_ver
= 1;
879 static const int pci_dsn_cap
= 4;
881 pcie_add_capability(dev
, PCI_EXT_CAP_ID_DSN
, pci_dsn_ver
, offset
,
882 PCI_EXT_CAP_DSN_SIZEOF
);
883 pci_set_quad(dev
->config
+ offset
+ pci_dsn_cap
, ser_num
);
886 void pcie_ats_init(PCIDevice
*dev
, uint16_t offset
)
888 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ATS
, 0x1,
889 offset
, PCI_EXT_CAP_ATS_SIZEOF
);
891 dev
->exp
.ats_cap
= offset
;
893 /* Invalidate Queue Depth 0, Page Aligned Request 0 */
894 pci_set_word(dev
->config
+ offset
+ PCI_ATS_CAP
, 0);
895 /* STU 0, Disabled by default */
896 pci_set_word(dev
->config
+ offset
+ PCI_ATS_CTRL
, 0);
898 pci_set_word(dev
->wmask
+ dev
->exp
.ats_cap
+ PCI_ATS_CTRL
, 0x800f);