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target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree
[qemu/ar7.git] / hw / display / tc6393xb.c
blob49a676d1b0eb3475d9f0916c266032d9ceb5b930
1 /*
2 * Toshiba TC6393XB I/O Controller.
3 * Found in Sharp Zaurus SL-6000 (tosa) or some
4 * Toshiba e-Series PDAs.
5 *
6 * Most features are currently unsupported!!!
7 *
8 * This code is licensed under the GNU GPL v2.
9 *
10 * Contributions after 2012-01-13 are licensed under the terms of the
11 * GNU GPL, version 2 or (at your option) any later version.
12 */
13
14 #include "qemu/osdep.h"
15 #include "qapi/error.h"
16 #include "qemu/host-utils.h"
17 #include "hw/irq.h"
18 #include "hw/display/tc6393xb.h"
19 #include "exec/memory.h"
20 #include "hw/block/flash.h"
21 #include "ui/console.h"
22 #include "ui/pixel_ops.h"
23 #include "sysemu/blockdev.h"
24
25 #define IRQ_TC6393_NAND 0
26 #define IRQ_TC6393_MMC 1
27 #define IRQ_TC6393_OHCI 2
28 #define IRQ_TC6393_SERIAL 3
29 #define IRQ_TC6393_FB 4
30
31 #define TC6393XB_NR_IRQS 8
32
33 #define TC6393XB_GPIOS 16
34
35 #define SCR_REVID 0x08 /* b Revision ID */
36 #define SCR_ISR 0x50 /* b Interrupt Status */
37 #define SCR_IMR 0x52 /* b Interrupt Mask */
38 #define SCR_IRR 0x54 /* b Interrupt Routing */
39 #define SCR_GPER 0x60 /* w GP Enable */
40 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
41 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
42 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
43 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
44 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
45 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
46 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
47 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
48 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
49 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
50 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
51 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
52 #define SCR_CCR 0x98 /* w Clock Control */
53 #define SCR_PLL2CR 0x9a /* w PLL2 Control */
54 #define SCR_PLL1CR 0x9c /* l PLL1 Control */
55 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
56 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
57 #define SCR_FER 0xe0 /* b Function Enable */
58 #define SCR_MCR 0xe4 /* w Mode Control */
59 #define SCR_CONFIG 0xfc /* b Configuration Control */
60 #define SCR_DEBUG 0xff /* b Debug */
61
62 #define NAND_CFG_COMMAND 0x04 /* w Command */
63 #define NAND_CFG_BASE 0x10 /* l Control Base Address */
64 #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */
65 #define NAND_CFG_INTE 0x48 /* b Int Enable */
66 #define NAND_CFG_EC 0x4a /* b Event Control */
67 #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */
68 #define NAND_CFG_ECCC 0x5b /* b ECC Control */
69 #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */
70 #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */
71 #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */
72 #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */
73
74 #define NAND_DATA 0x00 /* l Data */
75 #define NAND_MODE 0x04 /* b Mode */
76 #define NAND_STATUS 0x05 /* b Status */
77 #define NAND_ISR 0x06 /* b Interrupt Status */
78 #define NAND_IMR 0x07 /* b Interrupt Mask */
79
80 #define NAND_MODE_WP 0x80
81 #define NAND_MODE_CE 0x10
82 #define NAND_MODE_ALE 0x02
83 #define NAND_MODE_CLE 0x01
84 #define NAND_MODE_ECC_MASK 0x60
85 #define NAND_MODE_ECC_EN 0x20
86 #define NAND_MODE_ECC_READ 0x40
87 #define NAND_MODE_ECC_RST 0x60
88
89 struct TC6393xbState {
90 MemoryRegion iomem;
91 qemu_irq irq;
92 qemu_irq *sub_irqs;
93 struct {
94 uint8_t ISR;
95 uint8_t IMR;
96 uint8_t IRR;
97 uint16_t GPER;
98 uint8_t GPI_SR[3];
99 uint8_t GPI_IMR[3];
100 uint8_t GPI_EDER[3];
101 uint8_t GPI_LIR[3];
102 uint8_t GP_IARCR[3];
103 uint8_t GP_IARLCR[3];
104 uint8_t GPI_BCR[3];
105 uint16_t GPA_IARCR;
106 uint16_t GPA_IARLCR;
107 uint16_t CCR;
108 uint16_t PLL2CR;
109 uint32_t PLL1CR;
110 uint8_t DIARCR;
111 uint8_t DBOCR;
112 uint8_t FER;
113 uint16_t MCR;
114 uint8_t CONFIG;
115 uint8_t DEBUG;
116 } scr;
117 uint32_t gpio_dir;
118 uint32_t gpio_level;
119 uint32_t prev_level;
120 qemu_irq handler[TC6393XB_GPIOS];
121 qemu_irq *gpio_in;
122
123 struct {
124 uint8_t mode;
125 uint8_t isr;
126 uint8_t imr;
127 } nand;
128 int nand_enable;
129 uint32_t nand_phys;
130 DeviceState *flash;
131 ECCState ecc;
132
133 QemuConsole *con;
134 MemoryRegion vram;
135 uint16_t *vram_ptr;
136 uint32_t scr_width, scr_height; /* in pixels */
137 qemu_irq l3v;
138 unsigned blank : 1,
139 blanked : 1;
140 };
141
142 static void tc6393xb_gpio_set(void *opaque, int line, int level)
143 {
144 // TC6393xbState *s = opaque;
145
146 if (line > TC6393XB_GPIOS) {
147 printf("%s: No GPIO pin %i\n", __func__, line);
148 return;
149 }
150
151 // FIXME: how does the chip reflect the GPIO input level change?
152 }
153
154 static void tc6393xb_gpio_handler_update(TC6393xbState *s)
155 {
156 uint32_t level, diff;
157 int bit;
158
159 level = s->gpio_level & s->gpio_dir;
160 level &= MAKE_64BIT_MASK(0, TC6393XB_GPIOS);
161
162 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
163 bit = ctz32(diff);
164 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
165 }
166
167 s->prev_level = level;
168 }
169
170 qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
171 {
172 return s->l3v;
173 }
174
175 static void tc6393xb_l3v(void *opaque, int line, int level)
176 {
177 TC6393xbState *s = opaque;
178 s->blank = !level;
179 fprintf(stderr, "L3V: %d\n", level);
180 }
181
182 static void tc6393xb_sub_irq(void *opaque, int line, int level) {
183 TC6393xbState *s = opaque;
184 uint8_t isr = s->scr.ISR;
185 if (level)
186 isr |= 1 << line;
187 else
188 isr &= ~(1 << line);
189 s->scr.ISR = isr;
190 qemu_set_irq(s->irq, isr & s->scr.IMR);
191 }
192
193 #define SCR_REG_B(N) \
194 case SCR_ ##N: return s->scr.N
195 #define SCR_REG_W(N) \
196 case SCR_ ##N: return s->scr.N; \
197 case SCR_ ##N + 1: return s->scr.N >> 8;
198 #define SCR_REG_L(N) \
199 case SCR_ ##N: return s->scr.N; \
200 case SCR_ ##N + 1: return s->scr.N >> 8; \
201 case SCR_ ##N + 2: return s->scr.N >> 16; \
202 case SCR_ ##N + 3: return s->scr.N >> 24;
203 #define SCR_REG_A(N) \
204 case SCR_ ##N(0): return s->scr.N[0]; \
205 case SCR_ ##N(1): return s->scr.N[1]; \
206 case SCR_ ##N(2): return s->scr.N[2]
207
208 static uint32_t tc6393xb_scr_readb(TC6393xbState *s, hwaddr addr)
209 {
210 switch (addr) {
211 case SCR_REVID:
212 return 3;
213 case SCR_REVID+1:
214 return 0;
215 SCR_REG_B(ISR);
216 SCR_REG_B(IMR);
217 SCR_REG_B(IRR);
218 SCR_REG_W(GPER);
219 SCR_REG_A(GPI_SR);
220 SCR_REG_A(GPI_IMR);
221 SCR_REG_A(GPI_EDER);
222 SCR_REG_A(GPI_LIR);
223 case SCR_GPO_DSR(0):
224 case SCR_GPO_DSR(1):
225 case SCR_GPO_DSR(2):
226 return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
227 case SCR_GPO_DOECR(0):
228 case SCR_GPO_DOECR(1):
229 case SCR_GPO_DOECR(2):
230 return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
231 SCR_REG_A(GP_IARCR);
232 SCR_REG_A(GP_IARLCR);
233 SCR_REG_A(GPI_BCR);
234 SCR_REG_W(GPA_IARCR);
235 SCR_REG_W(GPA_IARLCR);
236 SCR_REG_W(CCR);
237 SCR_REG_W(PLL2CR);
238 SCR_REG_L(PLL1CR);
239 SCR_REG_B(DIARCR);
240 SCR_REG_B(DBOCR);
241 SCR_REG_B(FER);
242 SCR_REG_W(MCR);
243 SCR_REG_B(CONFIG);
244 SCR_REG_B(DEBUG);
245 }
246 fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
247 return 0;
248 }
249 #undef SCR_REG_B
250 #undef SCR_REG_W
251 #undef SCR_REG_L
252 #undef SCR_REG_A
253
254 #define SCR_REG_B(N) \
255 case SCR_ ##N: s->scr.N = value; return;
256 #define SCR_REG_W(N) \
257 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
258 case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return
259 #define SCR_REG_L(N) \
260 case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \
261 case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \
262 case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \
263 case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return;
264 #define SCR_REG_A(N) \
265 case SCR_ ##N(0): s->scr.N[0] = value; return; \
266 case SCR_ ##N(1): s->scr.N[1] = value; return; \
267 case SCR_ ##N(2): s->scr.N[2] = value; return
268
269 static void tc6393xb_scr_writeb(TC6393xbState *s, hwaddr addr, uint32_t value)
270 {
271 switch (addr) {
272 SCR_REG_B(ISR);
273 SCR_REG_B(IMR);
274 SCR_REG_B(IRR);
275 SCR_REG_W(GPER);
276 SCR_REG_A(GPI_SR);
277 SCR_REG_A(GPI_IMR);
278 SCR_REG_A(GPI_EDER);
279 SCR_REG_A(GPI_LIR);
280 case SCR_GPO_DSR(0):
281 case SCR_GPO_DSR(1):
282 case SCR_GPO_DSR(2):
283 s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
284 tc6393xb_gpio_handler_update(s);
285 return;
286 case SCR_GPO_DOECR(0):
287 case SCR_GPO_DOECR(1):
288 case SCR_GPO_DOECR(2):
289 s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
290 tc6393xb_gpio_handler_update(s);
291 return;
292 SCR_REG_A(GP_IARCR);
293 SCR_REG_A(GP_IARLCR);
294 SCR_REG_A(GPI_BCR);
295 SCR_REG_W(GPA_IARCR);
296 SCR_REG_W(GPA_IARLCR);
297 SCR_REG_W(CCR);
298 SCR_REG_W(PLL2CR);
299 SCR_REG_L(PLL1CR);
300 SCR_REG_B(DIARCR);
301 SCR_REG_B(DBOCR);
302 SCR_REG_B(FER);
303 SCR_REG_W(MCR);
304 SCR_REG_B(CONFIG);
305 SCR_REG_B(DEBUG);
306 }
307 fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
308 (uint32_t) addr, value & 0xff);
309 }
310 #undef SCR_REG_B
311 #undef SCR_REG_W
312 #undef SCR_REG_L
313 #undef SCR_REG_A
314
315 static void tc6393xb_nand_irq(TC6393xbState *s) {
316 qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
317 (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
318 }
319
320 static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, hwaddr addr) {
321 switch (addr) {
322 case NAND_CFG_COMMAND:
323 return s->nand_enable ? 2 : 0;
324 case NAND_CFG_BASE:
325 case NAND_CFG_BASE + 1:
326 case NAND_CFG_BASE + 2:
327 case NAND_CFG_BASE + 3:
328 return s->nand_phys >> (addr - NAND_CFG_BASE);
329 }
330 fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
331 return 0;
332 }
333 static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
334 switch (addr) {
335 case NAND_CFG_COMMAND:
336 s->nand_enable = (value & 0x2);
337 return;
338 case NAND_CFG_BASE:
339 case NAND_CFG_BASE + 1:
340 case NAND_CFG_BASE + 2:
341 case NAND_CFG_BASE + 3:
342 s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8));
343 s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8);
344 return;
345 }
346 fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
347 (uint32_t) addr, value & 0xff);
348 }
349
350 static uint32_t tc6393xb_nand_readb(TC6393xbState *s, hwaddr addr) {
351 switch (addr) {
352 case NAND_DATA + 0:
353 case NAND_DATA + 1:
354 case NAND_DATA + 2:
355 case NAND_DATA + 3:
356 return nand_getio(s->flash);
357 case NAND_MODE:
358 return s->nand.mode;
359 case NAND_STATUS:
360 return 0x14;
361 case NAND_ISR:
362 return s->nand.isr;
363 case NAND_IMR:
364 return s->nand.imr;
365 }
366 fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
367 return 0;
368 }
369 static void tc6393xb_nand_writeb(TC6393xbState *s, hwaddr addr, uint32_t value) {
370 // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
371 // (uint32_t) addr, value & 0xff);
372 switch (addr) {
373 case NAND_DATA + 0:
374 case NAND_DATA + 1:
375 case NAND_DATA + 2:
376 case NAND_DATA + 3:
377 nand_setio(s->flash, value);
378 s->nand.isr |= 1;
379 tc6393xb_nand_irq(s);
380 return;
381 case NAND_MODE:
382 s->nand.mode = value;
383 nand_setpins(s->flash,
384 value & NAND_MODE_CLE,
385 value & NAND_MODE_ALE,
386 !(value & NAND_MODE_CE),
387 value & NAND_MODE_WP,
388 0); // FIXME: gnd
389 switch (value & NAND_MODE_ECC_MASK) {
390 case NAND_MODE_ECC_RST:
391 ecc_reset(&s->ecc);
392 break;
393 case NAND_MODE_ECC_READ:
394 // FIXME
395 break;
396 case NAND_MODE_ECC_EN:
397 ecc_reset(&s->ecc);
398 }
399 return;
400 case NAND_ISR:
401 s->nand.isr = value;
402 tc6393xb_nand_irq(s);
403 return;
404 case NAND_IMR:
405 s->nand.imr = value;
406 tc6393xb_nand_irq(s);
407 return;
408 }
409 fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
410 (uint32_t) addr, value & 0xff);
411 }
412
413 #define BITS 8
414 #include "tc6393xb_template.h"
415 #define BITS 15
416 #include "tc6393xb_template.h"
417 #define BITS 16
418 #include "tc6393xb_template.h"
419 #define BITS 24
420 #include "tc6393xb_template.h"
421 #define BITS 32
422 #include "tc6393xb_template.h"
423
424 static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
425 {
426 DisplaySurface *surface = qemu_console_surface(s->con);
427
428 switch (surface_bits_per_pixel(surface)) {
429 case 8:
430 tc6393xb_draw_graphic8(s);
431 break;
432 case 15:
433 tc6393xb_draw_graphic15(s);
434 break;
435 case 16:
436 tc6393xb_draw_graphic16(s);
437 break;
438 case 24:
439 tc6393xb_draw_graphic24(s);
440 break;
441 case 32:
442 tc6393xb_draw_graphic32(s);
443 break;
444 default:
445 printf("tc6393xb: unknown depth %d\n",
446 surface_bits_per_pixel(surface));
447 return;
448 }
449
450 dpy_gfx_update_full(s->con);
451 }
452
453 static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
454 {
455 DisplaySurface *surface = qemu_console_surface(s->con);
456 int i, w;
457 uint8_t *d;
458
459 if (!full_update)
460 return;
461
462 w = s->scr_width * surface_bytes_per_pixel(surface);
463 d = surface_data(surface);
464 for(i = 0; i < s->scr_height; i++) {
465 memset(d, 0, w);
466 d += surface_stride(surface);
467 }
468
469 dpy_gfx_update_full(s->con);
470 }
471
472 static void tc6393xb_update_display(void *opaque)
473 {
474 TC6393xbState *s = opaque;
475 DisplaySurface *surface = qemu_console_surface(s->con);
476 int full_update;
477
478 if (s->scr_width == 0 || s->scr_height == 0)
479 return;
480
481 full_update = 0;
482 if (s->blanked != s->blank) {
483 s->blanked = s->blank;
484 full_update = 1;
485 }
486 if (s->scr_width != surface_width(surface) ||
487 s->scr_height != surface_height(surface)) {
488 qemu_console_resize(s->con, s->scr_width, s->scr_height);
489 full_update = 1;
490 }
491 if (s->blanked)
492 tc6393xb_draw_blank(s, full_update);
493 else
494 tc6393xb_draw_graphic(s, full_update);
495 }
496
497
498 static uint64_t tc6393xb_readb(void *opaque, hwaddr addr,
499 unsigned size)
500 {
501 TC6393xbState *s = opaque;
502
503 switch (addr >> 8) {
504 case 0:
505 return tc6393xb_scr_readb(s, addr & 0xff);
506 case 1:
507 return tc6393xb_nand_cfg_readb(s, addr & 0xff);
508 };
509
510 if ((addr &~0xff) == s->nand_phys && s->nand_enable) {
511 // return tc6393xb_nand_readb(s, addr & 0xff);
512 uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
513 // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
514 return d;
515 }
516
517 // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
518 return 0;
519 }
520
521 static void tc6393xb_writeb(void *opaque, hwaddr addr,
522 uint64_t value, unsigned size) {
523 TC6393xbState *s = opaque;
524
525 switch (addr >> 8) {
526 case 0:
527 tc6393xb_scr_writeb(s, addr & 0xff, value);
528 return;
529 case 1:
530 tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
531 return;
532 };
533
534 if ((addr &~0xff) == s->nand_phys && s->nand_enable)
535 tc6393xb_nand_writeb(s, addr & 0xff, value);
536 else
537 fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
538 (uint32_t) addr, (int)value & 0xff);
539 }
540
541 static const GraphicHwOps tc6393xb_gfx_ops = {
542 .gfx_update = tc6393xb_update_display,
543 };
544
545 TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
546 {
547 TC6393xbState *s;
548 DriveInfo *nand;
549 static const MemoryRegionOps tc6393xb_ops = {
550 .read = tc6393xb_readb,
551 .write = tc6393xb_writeb,
552 .endianness = DEVICE_NATIVE_ENDIAN,
553 .impl = {
554 .min_access_size = 1,
555 .max_access_size = 1,
556 },
557 };
558
559 s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
560 s->irq = irq;
561 s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
562
563 s->l3v = qemu_allocate_irq(tc6393xb_l3v, s, 0);
564 s->blanked = 1;
565
566 s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS);
567
568 nand = drive_get(IF_MTD, 0, 0);
569 s->flash = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
570 NAND_MFR_TOSHIBA, 0x76);
571
572 memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000);
573 memory_region_add_subregion(sysmem, base, &s->iomem);
574
575 memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000,
576 &error_fatal);
577 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
578 memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
579 s->scr_width = 480;
580 s->scr_height = 640;
581 s->con = graphic_console_init(NULL, 0, &tc6393xb_gfx_ops, s);
582
583 return s;
584 }
AR7 emulation for QEMU