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AHCI: Do not (re)map FB/CLB buffers while not running
[qemu/ar7.git] / hw / ide / ahci.c
blob4ccfcf33114233ee86789fd200d33f9c5c2d7123
1 /*
2 * QEMU AHCI Emulation
3 *
4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
24 #include <hw/hw.h>
25 #include <hw/pci/msi.h>
26 #include <hw/i386/pc.h>
27 #include <hw/pci/pci.h>
28 #include <hw/sysbus.h>
29
30 #include "monitor/monitor.h"
31 #include "sysemu/block-backend.h"
32 #include "sysemu/dma.h"
33 #include "internal.h"
34 #include <hw/ide/pci.h>
35 #include <hw/ide/ahci.h>
36
37 #define DEBUG_AHCI 0
38
39 #define DPRINTF(port, fmt, ...) \
40 do { \
41 if (DEBUG_AHCI) { \
42 fprintf(stderr, "ahci: %s: [%d] ", __func__, port); \
43 fprintf(stderr, fmt, ## __VA_ARGS__); \
44 } \
45 } while (0)
46
47 static void check_cmd(AHCIState *s, int port);
48 static int handle_cmd(AHCIState *s,int port,int slot);
49 static void ahci_reset_port(AHCIState *s, int port);
50 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis);
51 static void ahci_init_d2h(AHCIDevice *ad);
52 static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write);
53 static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes);
54 static bool ahci_map_clb_address(AHCIDevice *ad);
55 static bool ahci_map_fis_address(AHCIDevice *ad);
56
57
58 static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
59 {
60 uint32_t val;
61 AHCIPortRegs *pr;
62 pr = &s->dev[port].port_regs;
63
64 switch (offset) {
65 case PORT_LST_ADDR:
66 val = pr->lst_addr;
67 break;
68 case PORT_LST_ADDR_HI:
69 val = pr->lst_addr_hi;
70 break;
71 case PORT_FIS_ADDR:
72 val = pr->fis_addr;
73 break;
74 case PORT_FIS_ADDR_HI:
75 val = pr->fis_addr_hi;
76 break;
77 case PORT_IRQ_STAT:
78 val = pr->irq_stat;
79 break;
80 case PORT_IRQ_MASK:
81 val = pr->irq_mask;
82 break;
83 case PORT_CMD:
84 val = pr->cmd;
85 break;
86 case PORT_TFDATA:
87 val = pr->tfdata;
88 break;
89 case PORT_SIG:
90 val = pr->sig;
91 break;
92 case PORT_SCR_STAT:
93 if (s->dev[port].port.ifs[0].blk) {
94 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP |
95 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE;
96 } else {
97 val = SATA_SCR_SSTATUS_DET_NODEV;
98 }
99 break;
100 case PORT_SCR_CTL:
101 val = pr->scr_ctl;
102 break;
103 case PORT_SCR_ERR:
104 val = pr->scr_err;
105 break;
106 case PORT_SCR_ACT:
107 pr->scr_act &= ~s->dev[port].finished;
108 s->dev[port].finished = 0;
109 val = pr->scr_act;
110 break;
111 case PORT_CMD_ISSUE:
112 val = pr->cmd_issue;
113 break;
114 case PORT_RESERVED:
115 default:
116 val = 0;
117 }
118 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
119 return val;
120
121 }
122
123 static void ahci_irq_raise(AHCIState *s, AHCIDevice *dev)
124 {
125 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
126 PCIDevice *pci_dev =
127 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE);
128
129 DPRINTF(0, "raise irq\n");
130
131 if (pci_dev && msi_enabled(pci_dev)) {
132 msi_notify(pci_dev, 0);
133 } else {
134 qemu_irq_raise(s->irq);
135 }
136 }
137
138 static void ahci_irq_lower(AHCIState *s, AHCIDevice *dev)
139 {
140 AHCIPCIState *d = container_of(s, AHCIPCIState, ahci);
141 PCIDevice *pci_dev =
142 (PCIDevice *)object_dynamic_cast(OBJECT(d), TYPE_PCI_DEVICE);
143
144 DPRINTF(0, "lower irq\n");
145
146 if (!pci_dev || !msi_enabled(pci_dev)) {
147 qemu_irq_lower(s->irq);
148 }
149 }
150
151 static void ahci_check_irq(AHCIState *s)
152 {
153 int i;
154
155 DPRINTF(-1, "check irq %#x\n", s->control_regs.irqstatus);
156
157 s->control_regs.irqstatus = 0;
158 for (i = 0; i < s->ports; i++) {
159 AHCIPortRegs *pr = &s->dev[i].port_regs;
160 if (pr->irq_stat & pr->irq_mask) {
161 s->control_regs.irqstatus |= (1 << i);
162 }
163 }
164
165 if (s->control_regs.irqstatus &&
166 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
167 ahci_irq_raise(s, NULL);
168 } else {
169 ahci_irq_lower(s, NULL);
170 }
171 }
172
173 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
174 int irq_type)
175 {
176 DPRINTF(d->port_no, "trigger irq %#x -> %x\n",
177 irq_type, d->port_regs.irq_mask & irq_type);
178
179 d->port_regs.irq_stat |= irq_type;
180 ahci_check_irq(s);
181 }
182
183 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr,
184 uint32_t wanted)
185 {
186 hwaddr len = wanted;
187
188 if (*ptr) {
189 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len);
190 }
191
192 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE);
193 if (len < wanted) {
194 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len);
195 *ptr = NULL;
196 }
197 }
198
199 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
200 {
201 AHCIPortRegs *pr = &s->dev[port].port_regs;
202
203 DPRINTF(port, "offset: 0x%x val: 0x%x\n", offset, val);
204 switch (offset) {
205 case PORT_LST_ADDR:
206 pr->lst_addr = val;
207 break;
208 case PORT_LST_ADDR_HI:
209 pr->lst_addr_hi = val;
210 break;
211 case PORT_FIS_ADDR:
212 pr->fis_addr = val;
213 break;
214 case PORT_FIS_ADDR_HI:
215 pr->fis_addr_hi = val;
216 break;
217 case PORT_IRQ_STAT:
218 pr->irq_stat &= ~val;
219 ahci_check_irq(s);
220 break;
221 case PORT_IRQ_MASK:
222 pr->irq_mask = val & 0xfdc000ff;
223 ahci_check_irq(s);
224 break;
225 case PORT_CMD:
226 pr->cmd = val & ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);
227
228 if (pr->cmd & PORT_CMD_START) {
229 if (ahci_map_clb_address(&s->dev[port])) {
230 pr->cmd |= PORT_CMD_LIST_ON;
231 } else {
232 error_report("AHCI: Failed to start DMA engine: "
233 "bad command list buffer address");
234 }
235 }
236
237 if (pr->cmd & PORT_CMD_FIS_RX) {
238 if (ahci_map_fis_address(&s->dev[port])) {
239 pr->cmd |= PORT_CMD_FIS_ON;
240 } else {
241 error_report("AHCI: Failed to start FIS receive engine: "
242 "bad FIS receive buffer address");
243 }
244 }
245
246 /* XXX usually the FIS would be pending on the bus here and
247 issuing deferred until the OS enables FIS receival.
248 Instead, we only submit it once - which works in most
249 cases, but is a hack. */
250 if ((pr->cmd & PORT_CMD_FIS_ON) &&
251 !s->dev[port].init_d2h_sent) {
252 ahci_init_d2h(&s->dev[port]);
253 s->dev[port].init_d2h_sent = true;
254 }
255
256 check_cmd(s, port);
257 break;
258 case PORT_TFDATA:
259 /* Read Only. */
260 break;
261 case PORT_SIG:
262 /* Read Only */
263 break;
264 case PORT_SCR_STAT:
265 /* Read Only */
266 break;
267 case PORT_SCR_CTL:
268 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
269 ((val & AHCI_SCR_SCTL_DET) == 0)) {
270 ahci_reset_port(s, port);
271 }
272 pr->scr_ctl = val;
273 break;
274 case PORT_SCR_ERR:
275 pr->scr_err &= ~val;
276 break;
277 case PORT_SCR_ACT:
278 /* RW1 */
279 pr->scr_act |= val;
280 break;
281 case PORT_CMD_ISSUE:
282 pr->cmd_issue |= val;
283 check_cmd(s, port);
284 break;
285 default:
286 break;
287 }
288 }
289
290 static uint64_t ahci_mem_read(void *opaque, hwaddr addr,
291 unsigned size)
292 {
293 AHCIState *s = opaque;
294 uint32_t val = 0;
295
296 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
297 switch (addr) {
298 case HOST_CAP:
299 val = s->control_regs.cap;
300 break;
301 case HOST_CTL:
302 val = s->control_regs.ghc;
303 break;
304 case HOST_IRQ_STAT:
305 val = s->control_regs.irqstatus;
306 break;
307 case HOST_PORTS_IMPL:
308 val = s->control_regs.impl;
309 break;
310 case HOST_VERSION:
311 val = s->control_regs.version;
312 break;
313 }
314
315 DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val);
316 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
317 (addr < (AHCI_PORT_REGS_START_ADDR +
318 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
319 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
320 addr & AHCI_PORT_ADDR_OFFSET_MASK);
321 }
322
323 return val;
324 }
325
326
327
328 static void ahci_mem_write(void *opaque, hwaddr addr,
329 uint64_t val, unsigned size)
330 {
331 AHCIState *s = opaque;
332
333 /* Only aligned reads are allowed on AHCI */
334 if (addr & 3) {
335 fprintf(stderr, "ahci: Mis-aligned write to addr 0x"
336 TARGET_FMT_plx "\n", addr);
337 return;
338 }
339
340 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
341 DPRINTF(-1, "(addr 0x%08X), val 0x%08"PRIX64"\n", (unsigned) addr, val);
342
343 switch (addr) {
344 case HOST_CAP: /* R/WO, RO */
345 /* FIXME handle R/WO */
346 break;
347 case HOST_CTL: /* R/W */
348 if (val & HOST_CTL_RESET) {
349 DPRINTF(-1, "HBA Reset\n");
350 ahci_reset(s);
351 } else {
352 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
353 ahci_check_irq(s);
354 }
355 break;
356 case HOST_IRQ_STAT: /* R/WC, RO */
357 s->control_regs.irqstatus &= ~val;
358 ahci_check_irq(s);
359 break;
360 case HOST_PORTS_IMPL: /* R/WO, RO */
361 /* FIXME handle R/WO */
362 break;
363 case HOST_VERSION: /* RO */
364 /* FIXME report write? */
365 break;
366 default:
367 DPRINTF(-1, "write to unknown register 0x%x\n", (unsigned)addr);
368 }
369 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
370 (addr < (AHCI_PORT_REGS_START_ADDR +
371 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
372 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
373 addr & AHCI_PORT_ADDR_OFFSET_MASK, val);
374 }
375
376 }
377
378 static const MemoryRegionOps ahci_mem_ops = {
379 .read = ahci_mem_read,
380 .write = ahci_mem_write,
381 .endianness = DEVICE_LITTLE_ENDIAN,
382 };
383
384 static uint64_t ahci_idp_read(void *opaque, hwaddr addr,
385 unsigned size)
386 {
387 AHCIState *s = opaque;
388
389 if (addr == s->idp_offset) {
390 /* index register */
391 return s->idp_index;
392 } else if (addr == s->idp_offset + 4) {
393 /* data register - do memory read at location selected by index */
394 return ahci_mem_read(opaque, s->idp_index, size);
395 } else {
396 return 0;
397 }
398 }
399
400 static void ahci_idp_write(void *opaque, hwaddr addr,
401 uint64_t val, unsigned size)
402 {
403 AHCIState *s = opaque;
404
405 if (addr == s->idp_offset) {
406 /* index register - mask off reserved bits */
407 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3);
408 } else if (addr == s->idp_offset + 4) {
409 /* data register - do memory write at location selected by index */
410 ahci_mem_write(opaque, s->idp_index, val, size);
411 }
412 }
413
414 static const MemoryRegionOps ahci_idp_ops = {
415 .read = ahci_idp_read,
416 .write = ahci_idp_write,
417 .endianness = DEVICE_LITTLE_ENDIAN,
418 };
419
420
421 static void ahci_reg_init(AHCIState *s)
422 {
423 int i;
424
425 s->control_regs.cap = (s->ports - 1) |
426 (AHCI_NUM_COMMAND_SLOTS << 8) |
427 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) |
428 HOST_CAP_NCQ | HOST_CAP_AHCI;
429
430 s->control_regs.impl = (1 << s->ports) - 1;
431
432 s->control_regs.version = AHCI_VERSION_1_0;
433
434 for (i = 0; i < s->ports; i++) {
435 s->dev[i].port_state = STATE_RUN;
436 }
437 }
438
439 static void check_cmd(AHCIState *s, int port)
440 {
441 AHCIPortRegs *pr = &s->dev[port].port_regs;
442 int slot;
443
444 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {
445 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {
446 if ((pr->cmd_issue & (1U << slot)) &&
447 !handle_cmd(s, port, slot)) {
448 pr->cmd_issue &= ~(1U << slot);
449 }
450 }
451 }
452 }
453
454 static void ahci_check_cmd_bh(void *opaque)
455 {
456 AHCIDevice *ad = opaque;
457
458 qemu_bh_delete(ad->check_bh);
459 ad->check_bh = NULL;
460
461 if ((ad->busy_slot != -1) &&
462 !(ad->port.ifs[0].status & (BUSY_STAT|DRQ_STAT))) {
463 /* no longer busy */
464 ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot);
465 ad->busy_slot = -1;
466 }
467
468 check_cmd(ad->hba, ad->port_no);
469 }
470
471 static void ahci_init_d2h(AHCIDevice *ad)
472 {
473 uint8_t init_fis[20];
474 IDEState *ide_state = &ad->port.ifs[0];
475
476 memset(init_fis, 0, sizeof(init_fis));
477
478 init_fis[4] = 1;
479 init_fis[12] = 1;
480
481 if (ide_state->drive_kind == IDE_CD) {
482 init_fis[5] = ide_state->lcyl;
483 init_fis[6] = ide_state->hcyl;
484 }
485
486 ahci_write_fis_d2h(ad, init_fis);
487 }
488
489 static void ahci_reset_port(AHCIState *s, int port)
490 {
491 AHCIDevice *d = &s->dev[port];
492 AHCIPortRegs *pr = &d->port_regs;
493 IDEState *ide_state = &d->port.ifs[0];
494 int i;
495
496 DPRINTF(port, "reset port\n");
497
498 ide_bus_reset(&d->port);
499 ide_state->ncq_queues = AHCI_MAX_CMDS;
500
501 pr->scr_stat = 0;
502 pr->scr_err = 0;
503 pr->scr_act = 0;
504 pr->tfdata = 0x7F;
505 pr->sig = 0xFFFFFFFF;
506 d->busy_slot = -1;
507 d->init_d2h_sent = false;
508
509 ide_state = &s->dev[port].port.ifs[0];
510 if (!ide_state->blk) {
511 return;
512 }
513
514 /* reset ncq queue */
515 for (i = 0; i < AHCI_MAX_CMDS; i++) {
516 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i];
517 if (!ncq_tfs->used) {
518 continue;
519 }
520
521 if (ncq_tfs->aiocb) {
522 blk_aio_cancel(ncq_tfs->aiocb);
523 ncq_tfs->aiocb = NULL;
524 }
525
526 /* Maybe we just finished the request thanks to blk_aio_cancel() */
527 if (!ncq_tfs->used) {
528 continue;
529 }
530
531 qemu_sglist_destroy(&ncq_tfs->sglist);
532 ncq_tfs->used = 0;
533 }
534
535 s->dev[port].port_state = STATE_RUN;
536 if (!ide_state->blk) {
537 pr->sig = 0;
538 ide_state->status = SEEK_STAT | WRERR_STAT;
539 } else if (ide_state->drive_kind == IDE_CD) {
540 pr->sig = SATA_SIGNATURE_CDROM;
541 ide_state->lcyl = 0x14;
542 ide_state->hcyl = 0xeb;
543 DPRINTF(port, "set lcyl = %d\n", ide_state->lcyl);
544 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT;
545 } else {
546 pr->sig = SATA_SIGNATURE_DISK;
547 ide_state->status = SEEK_STAT | WRERR_STAT;
548 }
549
550 ide_state->error = 1;
551 ahci_init_d2h(d);
552 }
553
554 static void debug_print_fis(uint8_t *fis, int cmd_len)
555 {
556 #if DEBUG_AHCI
557 int i;
558
559 fprintf(stderr, "fis:");
560 for (i = 0; i < cmd_len; i++) {
561 if ((i & 0xf) == 0) {
562 fprintf(stderr, "\n%02x:",i);
563 }
564 fprintf(stderr, "%02x ",fis[i]);
565 }
566 fprintf(stderr, "\n");
567 #endif
568 }
569
570 static bool ahci_map_fis_address(AHCIDevice *ad)
571 {
572 AHCIPortRegs *pr = &ad->port_regs;
573 map_page(ad->hba->as, &ad->res_fis,
574 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
575 return ad->res_fis != NULL;
576 }
577
578 static bool ahci_map_clb_address(AHCIDevice *ad)
579 {
580 AHCIPortRegs *pr = &ad->port_regs;
581 ad->cur_cmd = NULL;
582 map_page(ad->hba->as, &ad->lst,
583 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
584 return ad->lst != NULL;
585 }
586
587 static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)
588 {
589 AHCIDevice *ad = &s->dev[port];
590 AHCIPortRegs *pr = &ad->port_regs;
591 IDEState *ide_state;
592 SDBFIS *sdb_fis;
593
594 if (!s->dev[port].res_fis ||
595 !(pr->cmd & PORT_CMD_FIS_RX)) {
596 return;
597 }
598
599 sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS];
600 ide_state = &ad->port.ifs[0];
601
602 sdb_fis->type = SATA_FIS_TYPE_SDB;
603 /* Interrupt pending & Notification bit */
604 sdb_fis->flags = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
605 sdb_fis->status = ide_state->status & 0x77;
606 sdb_fis->error = ide_state->error;
607 /* update SAct field in SDB_FIS */
608 s->dev[port].finished |= finished;
609 sdb_fis->payload = cpu_to_le32(ad->finished);
610
611 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */
612 pr->tfdata = (ad->port.ifs[0].error << 8) |
613 (ad->port.ifs[0].status & 0x77) |
614 (pr->tfdata & 0x88);
615
616 ahci_trigger_irq(s, ad, PORT_IRQ_SDB_FIS);
617 }
618
619 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len)
620 {
621 AHCIPortRegs *pr = &ad->port_regs;
622 uint8_t *pio_fis, *cmd_fis;
623 uint64_t tbl_addr;
624 dma_addr_t cmd_len = 0x80;
625 IDEState *s = &ad->port.ifs[0];
626
627 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
628 return;
629 }
630
631 /* map cmd_fis */
632 tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr);
633 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len,
634 DMA_DIRECTION_TO_DEVICE);
635
636 if (cmd_fis == NULL) {
637 DPRINTF(ad->port_no, "dma_memory_map failed in ahci_write_fis_pio");
638 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_HBUS_ERR);
639 return;
640 }
641
642 if (cmd_len != 0x80) {
643 DPRINTF(ad->port_no,
644 "dma_memory_map mapped too few bytes in ahci_write_fis_pio");
645 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len,
646 DMA_DIRECTION_TO_DEVICE, cmd_len);
647 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_HBUS_ERR);
648 return;
649 }
650
651 pio_fis = &ad->res_fis[RES_FIS_PSFIS];
652
653 pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP;
654 pio_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
655 pio_fis[2] = s->status;
656 pio_fis[3] = s->error;
657
658 pio_fis[4] = s->sector;
659 pio_fis[5] = s->lcyl;
660 pio_fis[6] = s->hcyl;
661 pio_fis[7] = s->select;
662 pio_fis[8] = s->hob_sector;
663 pio_fis[9] = s->hob_lcyl;
664 pio_fis[10] = s->hob_hcyl;
665 pio_fis[11] = 0;
666 pio_fis[12] = cmd_fis[12];
667 pio_fis[13] = cmd_fis[13];
668 pio_fis[14] = 0;
669 pio_fis[15] = s->status;
670 pio_fis[16] = len & 255;
671 pio_fis[17] = len >> 8;
672 pio_fis[18] = 0;
673 pio_fis[19] = 0;
674
675 /* Update shadow registers: */
676 pr->tfdata = (ad->port.ifs[0].error << 8) |
677 ad->port.ifs[0].status;
678
679 if (pio_fis[2] & ERR_STAT) {
680 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);
681 }
682
683 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS);
684
685 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len,
686 DMA_DIRECTION_TO_DEVICE, cmd_len);
687 }
688
689 static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis)
690 {
691 AHCIPortRegs *pr = &ad->port_regs;
692 uint8_t *d2h_fis;
693 int i;
694 dma_addr_t cmd_len = 0x80;
695 int cmd_mapped = 0;
696 IDEState *s = &ad->port.ifs[0];
697
698 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
699 return;
700 }
701
702 if (!cmd_fis) {
703 /* map cmd_fis */
704 uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr);
705 cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len,
706 DMA_DIRECTION_TO_DEVICE);
707 cmd_mapped = 1;
708 }
709
710 d2h_fis = &ad->res_fis[RES_FIS_RFIS];
711
712 d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H;
713 d2h_fis[1] = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);
714 d2h_fis[2] = s->status;
715 d2h_fis[3] = s->error;
716
717 d2h_fis[4] = s->sector;
718 d2h_fis[5] = s->lcyl;
719 d2h_fis[6] = s->hcyl;
720 d2h_fis[7] = s->select;
721 d2h_fis[8] = s->hob_sector;
722 d2h_fis[9] = s->hob_lcyl;
723 d2h_fis[10] = s->hob_hcyl;
724 d2h_fis[11] = 0;
725 d2h_fis[12] = cmd_fis[12];
726 d2h_fis[13] = cmd_fis[13];
727 for (i = 14; i < 20; i++) {
728 d2h_fis[i] = 0;
729 }
730
731 /* Update shadow registers: */
732 pr->tfdata = (ad->port.ifs[0].error << 8) |
733 ad->port.ifs[0].status;
734
735 if (d2h_fis[2] & ERR_STAT) {
736 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);
737 }
738
739 ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);
740
741 if (cmd_mapped) {
742 dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len,
743 DMA_DIRECTION_TO_DEVICE, cmd_len);
744 }
745 }
746
747 static int prdt_tbl_entry_size(const AHCI_SG *tbl)
748 {
749 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1;
750 }
751
752 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,
753 int32_t offset)
754 {
755 AHCICmdHdr *cmd = ad->cur_cmd;
756 uint32_t opts = le32_to_cpu(cmd->opts);
757 uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80;
758 int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN;
759 dma_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG));
760 dma_addr_t real_prdt_len = prdt_len;
761 uint8_t *prdt;
762 int i;
763 int r = 0;
764 uint64_t sum = 0;
765 int off_idx = -1;
766 int64_t off_pos = -1;
767 int tbl_entry_size;
768 IDEBus *bus = &ad->port;
769 BusState *qbus = BUS(bus);
770
771 /*
772 * Note: AHCI PRDT can describe up to 256GiB. SATA/ATA only support
773 * transactions of up to 32MiB as of ATA8-ACS3 rev 1b, assuming a
774 * 512 byte sector size. We limit the PRDT in this implementation to
775 * a reasonably large 2GiB, which can accommodate the maximum transfer
776 * request for sector sizes up to 32K.
777 */
778
779 if (!sglist_alloc_hint) {
780 DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts);
781 return -1;
782 }
783
784 /* map PRDT */
785 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len,
786 DMA_DIRECTION_TO_DEVICE))){
787 DPRINTF(ad->port_no, "map failed\n");
788 return -1;
789 }
790
791 if (prdt_len < real_prdt_len) {
792 DPRINTF(ad->port_no, "mapped less than expected\n");
793 r = -1;
794 goto out;
795 }
796
797 /* Get entries in the PRDT, init a qemu sglist accordingly */
798 if (sglist_alloc_hint > 0) {
799 AHCI_SG *tbl = (AHCI_SG *)prdt;
800 sum = 0;
801 for (i = 0; i < sglist_alloc_hint; i++) {
802 /* flags_size is zero-based */
803 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]);
804 if (offset <= (sum + tbl_entry_size)) {
805 off_idx = i;
806 off_pos = offset - sum;
807 break;
808 }
809 sum += tbl_entry_size;
810 }
811 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) {
812 DPRINTF(ad->port_no, "%s: Incorrect offset! "
813 "off_idx: %d, off_pos: %"PRId64"\n",
814 __func__, off_idx, off_pos);
815 r = -1;
816 goto out;
817 }
818
819 qemu_sglist_init(sglist, qbus->parent, (sglist_alloc_hint - off_idx),
820 ad->hba->as);
821 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos,
822 prdt_tbl_entry_size(&tbl[off_idx]) - off_pos);
823
824 for (i = off_idx + 1; i < sglist_alloc_hint; i++) {
825 /* flags_size is zero-based */
826 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
827 prdt_tbl_entry_size(&tbl[i]));
828 if (sglist->size > INT32_MAX) {
829 error_report("AHCI Physical Region Descriptor Table describes "
830 "more than 2 GiB.\n");
831 qemu_sglist_destroy(sglist);
832 r = -1;
833 goto out;
834 }
835 }
836 }
837
838 out:
839 dma_memory_unmap(ad->hba->as, prdt, prdt_len,
840 DMA_DIRECTION_TO_DEVICE, prdt_len);
841 return r;
842 }
843
844 static void ncq_cb(void *opaque, int ret)
845 {
846 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;
847 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];
848
849 if (ret == -ECANCELED) {
850 return;
851 }
852 /* Clear bit for this tag in SActive */
853 ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag);
854
855 if (ret < 0) {
856 /* error */
857 ide_state->error = ABRT_ERR;
858 ide_state->status = READY_STAT | ERR_STAT;
859 ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag);
860 } else {
861 ide_state->status = READY_STAT | SEEK_STAT;
862 }
863
864 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,
865 (1 << ncq_tfs->tag));
866
867 DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n",
868 ncq_tfs->tag);
869
870 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk),
871 &ncq_tfs->acct);
872 qemu_sglist_destroy(&ncq_tfs->sglist);
873 ncq_tfs->used = 0;
874 }
875
876 static int is_ncq(uint8_t ata_cmd)
877 {
878 /* Based on SATA 3.2 section 13.6.3.2 */
879 switch (ata_cmd) {
880 case READ_FPDMA_QUEUED:
881 case WRITE_FPDMA_QUEUED:
882 case NCQ_NON_DATA:
883 case RECEIVE_FPDMA_QUEUED:
884 case SEND_FPDMA_QUEUED:
885 return 1;
886 default:
887 return 0;
888 }
889 }
890
891 static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,
892 int slot)
893 {
894 NCQFrame *ncq_fis = (NCQFrame*)cmd_fis;
895 uint8_t tag = ncq_fis->tag >> 3;
896 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag];
897
898 if (ncq_tfs->used) {
899 /* error - already in use */
900 fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag);
901 return;
902 }
903
904 ncq_tfs->used = 1;
905 ncq_tfs->drive = &s->dev[port];
906 ncq_tfs->slot = slot;
907 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) |
908 ((uint64_t)ncq_fis->lba4 << 32) |
909 ((uint64_t)ncq_fis->lba3 << 24) |
910 ((uint64_t)ncq_fis->lba2 << 16) |
911 ((uint64_t)ncq_fis->lba1 << 8) |
912 (uint64_t)ncq_fis->lba0;
913
914 /* Note: We calculate the sector count, but don't currently rely on it.
915 * The total size of the DMA buffer tells us the transfer size instead. */
916 ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) |
917 ncq_fis->sector_count_low;
918
919 DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", "
920 "drive max %"PRId64"\n",
921 ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2,
922 s->dev[port].port.ifs[0].nb_sectors - 1);
923
924 ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist, 0);
925 ncq_tfs->tag = tag;
926
927 switch(ncq_fis->command) {
928 case READ_FPDMA_QUEUED:
929 DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", "
930 "tag %d\n",
931 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);
932
933 DPRINTF(port, "tag %d aio read %"PRId64"\n",
934 ncq_tfs->tag, ncq_tfs->lba);
935
936 dma_acct_start(ncq_tfs->drive->port.ifs[0].blk, &ncq_tfs->acct,
937 &ncq_tfs->sglist, BLOCK_ACCT_READ);
938 ncq_tfs->aiocb = dma_blk_read(ncq_tfs->drive->port.ifs[0].blk,
939 &ncq_tfs->sglist, ncq_tfs->lba,
940 ncq_cb, ncq_tfs);
941 break;
942 case WRITE_FPDMA_QUEUED:
943 DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n",
944 ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);
945
946 DPRINTF(port, "tag %d aio write %"PRId64"\n",
947 ncq_tfs->tag, ncq_tfs->lba);
948
949 dma_acct_start(ncq_tfs->drive->port.ifs[0].blk, &ncq_tfs->acct,
950 &ncq_tfs->sglist, BLOCK_ACCT_WRITE);
951 ncq_tfs->aiocb = dma_blk_write(ncq_tfs->drive->port.ifs[0].blk,
952 &ncq_tfs->sglist, ncq_tfs->lba,
953 ncq_cb, ncq_tfs);
954 break;
955 default:
956 if (is_ncq(cmd_fis[2])) {
957 DPRINTF(port,
958 "error: unsupported NCQ command (0x%02x) received\n",
959 cmd_fis[2]);
960 } else {
961 DPRINTF(port,
962 "error: tried to process non-NCQ command as NCQ\n");
963 }
964 qemu_sglist_destroy(&ncq_tfs->sglist);
965 }
966 }
967
968 static void handle_reg_h2d_fis(AHCIState *s, int port,
969 int slot, uint8_t *cmd_fis)
970 {
971 IDEState *ide_state = &s->dev[port].port.ifs[0];
972 AHCICmdHdr *cmd = s->dev[port].cur_cmd;
973 uint32_t opts = le32_to_cpu(cmd->opts);
974
975 if (cmd_fis[1] & 0x0F) {
976 DPRINTF(port, "Port Multiplier not supported."
977 " cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n",
978 cmd_fis[0], cmd_fis[1], cmd_fis[2]);
979 return;
980 }
981
982 if (cmd_fis[1] & 0x70) {
983 DPRINTF(port, "Reserved flags set in H2D Register FIS."
984 " cmd_fis[0]=%02x cmd_fis[1]=%02x cmd_fis[2]=%02x\n",
985 cmd_fis[0], cmd_fis[1], cmd_fis[2]);
986 return;
987 }
988
989 if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) {
990 switch (s->dev[port].port_state) {
991 case STATE_RUN:
992 if (cmd_fis[15] & ATA_SRST) {
993 s->dev[port].port_state = STATE_RESET;
994 }
995 break;
996 case STATE_RESET:
997 if (!(cmd_fis[15] & ATA_SRST)) {
998 ahci_reset_port(s, port);
999 }
1000 break;
1001 }
1002 return;
1003 }
1004
1005 /* Check for NCQ command */
1006 if (is_ncq(cmd_fis[2])) {
1007 process_ncq_command(s, port, cmd_fis, slot);
1008 return;
1009 }
1010
1011 /* Decompose the FIS:
1012 * AHCI does not interpret FIS packets, it only forwards them.
1013 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets.
1014 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets.
1015 *
1016 * ATA4 describes sector number for LBA28/CHS commands.
1017 * ATA6 describes sector number for LBA48 commands.
1018 * ATA8 deprecates CHS fully, describing only LBA28/48.
1019 *
1020 * We dutifully convert the FIS into IDE registers, and allow the
1021 * core layer to interpret them as needed. */
1022 ide_state->feature = cmd_fis[3];
1023 ide_state->sector = cmd_fis[4]; /* LBA 7:0 */
1024 ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */
1025 ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */
1026 ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */
1027 ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */
1028 ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */
1029 ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */
1030 ide_state->hob_feature = cmd_fis[11];
1031 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]);
1032 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */
1033 /* 15: Only valid when UPDATE_COMMAND not set. */
1034
1035 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1036 * table to ide_state->io_buffer */
1037 if (opts & AHCI_CMD_ATAPI) {
1038 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10);
1039 debug_print_fis(ide_state->io_buffer, 0x10);
1040 s->dev[port].done_atapi_packet = false;
1041 /* XXX send PIO setup FIS */
1042 }
1043
1044 ide_state->error = 0;
1045
1046 /* Reset transferred byte counter */
1047 cmd->status = 0;
1048
1049 /* We're ready to process the command in FIS byte 2. */
1050 ide_exec_cmd(&s->dev[port].port, cmd_fis[2]);
1051 }
1052
1053 static int handle_cmd(AHCIState *s, int port, int slot)
1054 {
1055 IDEState *ide_state;
1056 uint64_t tbl_addr;
1057 AHCICmdHdr *cmd;
1058 uint8_t *cmd_fis;
1059 dma_addr_t cmd_len;
1060
1061 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
1062 /* Engine currently busy, try again later */
1063 DPRINTF(port, "engine busy\n");
1064 return -1;
1065 }
1066
1067 if (!s->dev[port].lst) {
1068 DPRINTF(port, "error: lst not given but cmd handled");
1069 return -1;
1070 }
1071 cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot];
1072 /* remember current slot handle for later */
1073 s->dev[port].cur_cmd = cmd;
1074
1075 /* The device we are working for */
1076 ide_state = &s->dev[port].port.ifs[0];
1077 if (!ide_state->blk) {
1078 DPRINTF(port, "error: guest accessed unused port");
1079 return -1;
1080 }
1081
1082 tbl_addr = le64_to_cpu(cmd->tbl_addr);
1083 cmd_len = 0x80;
1084 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len,
1085 DMA_DIRECTION_FROM_DEVICE);
1086 if (!cmd_fis) {
1087 DPRINTF(port, "error: guest passed us an invalid cmd fis\n");
1088 return -1;
1089 } else if (cmd_len != 0x80) {
1090 ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_HBUS_ERR);
1091 DPRINTF(port, "error: dma_memory_map failed: "
1092 "(len(%02"PRIx64") != 0x80)\n",
1093 cmd_len);
1094 goto out;
1095 }
1096 debug_print_fis(cmd_fis, 0x80);
1097
1098 switch (cmd_fis[0]) {
1099 case SATA_FIS_TYPE_REGISTER_H2D:
1100 handle_reg_h2d_fis(s, port, slot, cmd_fis);
1101 break;
1102 default:
1103 DPRINTF(port, "unknown command cmd_fis[0]=%02x cmd_fis[1]=%02x "
1104 "cmd_fis[2]=%02x\n", cmd_fis[0], cmd_fis[1],
1105 cmd_fis[2]);
1106 break;
1107 }
1108
1109 out:
1110 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_FROM_DEVICE,
1111 cmd_len);
1112
1113 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
1114 /* async command, complete later */
1115 s->dev[port].busy_slot = slot;
1116 return -1;
1117 }
1118
1119 /* done handling the command */
1120 return 0;
1121 }
1122
1123 /* DMA dev <-> ram */
1124 static void ahci_start_transfer(IDEDMA *dma)
1125 {
1126 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1127 IDEState *s = &ad->port.ifs[0];
1128 uint32_t size = (uint32_t)(s->data_end - s->data_ptr);
1129 /* write == ram -> device */
1130 uint32_t opts = le32_to_cpu(ad->cur_cmd->opts);
1131 int is_write = opts & AHCI_CMD_WRITE;
1132 int is_atapi = opts & AHCI_CMD_ATAPI;
1133 int has_sglist = 0;
1134
1135 if (is_atapi && !ad->done_atapi_packet) {
1136 /* already prepopulated iobuffer */
1137 ad->done_atapi_packet = true;
1138 size = 0;
1139 goto out;
1140 }
1141
1142 if (ahci_dma_prepare_buf(dma, is_write)) {
1143 has_sglist = 1;
1144 }
1145
1146 DPRINTF(ad->port_no, "%sing %d bytes on %s w/%s sglist\n",
1147 is_write ? "writ" : "read", size, is_atapi ? "atapi" : "ata",
1148 has_sglist ? "" : "o");
1149
1150 if (has_sglist && size) {
1151 if (is_write) {
1152 dma_buf_write(s->data_ptr, size, &s->sg);
1153 } else {
1154 dma_buf_read(s->data_ptr, size, &s->sg);
1155 }
1156 }
1157
1158 out:
1159 /* declare that we processed everything */
1160 s->data_ptr = s->data_end;
1161
1162 /* Update number of transferred bytes, destroy sglist */
1163 ahci_commit_buf(dma, size);
1164
1165 s->end_transfer_func(s);
1166
1167 if (!(s->status & DRQ_STAT)) {
1168 /* done with PIO send/receive */
1169 ahci_write_fis_pio(ad, le32_to_cpu(ad->cur_cmd->status));
1170 }
1171 }
1172
1173 static void ahci_start_dma(IDEDMA *dma, IDEState *s,
1174 BlockCompletionFunc *dma_cb)
1175 {
1176 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1177 DPRINTF(ad->port_no, "\n");
1178 s->io_buffer_offset = 0;
1179 dma_cb(s, 0);
1180 }
1181
1182 static void ahci_restart_dma(IDEDMA *dma)
1183 {
1184 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
1185 }
1186
1187 /**
1188 * Called in DMA R/W chains to read the PRDT, utilizing ahci_populate_sglist.
1189 * Not currently invoked by PIO R/W chains,
1190 * which invoke ahci_populate_sglist via ahci_start_transfer.
1191 */
1192 static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int is_write)
1193 {
1194 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1195 IDEState *s = &ad->port.ifs[0];
1196
1197 if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset) == -1) {
1198 DPRINTF(ad->port_no, "ahci_dma_prepare_buf failed.\n");
1199 return -1;
1200 }
1201 s->io_buffer_size = s->sg.size;
1202
1203 DPRINTF(ad->port_no, "len=%#x\n", s->io_buffer_size);
1204 return s->io_buffer_size;
1205 }
1206
1207 /**
1208 * Destroys the scatter-gather list,
1209 * and updates the command header with a bytes-read value.
1210 * called explicitly via ahci_dma_rw_buf (ATAPI DMA),
1211 * and ahci_start_transfer (PIO R/W),
1212 * and called via callback from ide_dma_cb for DMA R/W paths.
1213 */
1214 static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes)
1215 {
1216 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1217 IDEState *s = &ad->port.ifs[0];
1218
1219 tx_bytes += le32_to_cpu(ad->cur_cmd->status);
1220 ad->cur_cmd->status = cpu_to_le32(tx_bytes);
1221
1222 qemu_sglist_destroy(&s->sg);
1223 }
1224
1225 static int ahci_dma_rw_buf(IDEDMA *dma, int is_write)
1226 {
1227 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1228 IDEState *s = &ad->port.ifs[0];
1229 uint8_t *p = s->io_buffer + s->io_buffer_index;
1230 int l = s->io_buffer_size - s->io_buffer_index;
1231
1232 if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset)) {
1233 return 0;
1234 }
1235
1236 if (is_write) {
1237 dma_buf_read(p, l, &s->sg);
1238 } else {
1239 dma_buf_write(p, l, &s->sg);
1240 }
1241
1242 /* free sglist, update byte count */
1243 ahci_commit_buf(dma, l);
1244
1245 s->io_buffer_index += l;
1246 s->io_buffer_offset += l;
1247
1248 DPRINTF(ad->port_no, "len=%#x\n", l);
1249
1250 return 1;
1251 }
1252
1253 static void ahci_cmd_done(IDEDMA *dma)
1254 {
1255 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1256
1257 DPRINTF(ad->port_no, "cmd done\n");
1258
1259 /* update d2h status */
1260 ahci_write_fis_d2h(ad, NULL);
1261
1262 if (!ad->check_bh) {
1263 /* maybe we still have something to process, check later */
1264 ad->check_bh = qemu_bh_new(ahci_check_cmd_bh, ad);
1265 qemu_bh_schedule(ad->check_bh);
1266 }
1267 }
1268
1269 static void ahci_irq_set(void *opaque, int n, int level)
1270 {
1271 }
1272
1273 static const IDEDMAOps ahci_dma_ops = {
1274 .start_dma = ahci_start_dma,
1275 .restart_dma = ahci_restart_dma,
1276 .start_transfer = ahci_start_transfer,
1277 .prepare_buf = ahci_dma_prepare_buf,
1278 .commit_buf = ahci_commit_buf,
1279 .rw_buf = ahci_dma_rw_buf,
1280 .cmd_done = ahci_cmd_done,
1281 };
1282
1283 void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
1284 {
1285 qemu_irq *irqs;
1286 int i;
1287
1288 s->as = as;
1289 s->ports = ports;
1290 s->dev = g_new0(AHCIDevice, ports);
1291 ahci_reg_init(s);
1292 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1293 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
1294 "ahci", AHCI_MEM_BAR_SIZE);
1295 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
1296 "ahci-idp", 32);
1297
1298 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
1299
1300 for (i = 0; i < s->ports; i++) {
1301 AHCIDevice *ad = &s->dev[i];
1302
1303 ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1);
1304 ide_init2(&ad->port, irqs[i]);
1305
1306 ad->hba = s;
1307 ad->port_no = i;
1308 ad->port.dma = &ad->dma;
1309 ad->port.dma->ops = &ahci_dma_ops;
1310 ide_register_restart_cb(&ad->port);
1311 }
1312 }
1313
1314 void ahci_uninit(AHCIState *s)
1315 {
1316 g_free(s->dev);
1317 }
1318
1319 void ahci_reset(AHCIState *s)
1320 {
1321 AHCIPortRegs *pr;
1322 int i;
1323
1324 s->control_regs.irqstatus = 0;
1325 /* AHCI Enable (AE)
1326 * The implementation of this bit is dependent upon the value of the
1327 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and
1328 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be
1329 * read-only and shall have a reset value of '1'.
1330 *
1331 * We set HOST_CAP_AHCI so we must enable AHCI at reset.
1332 */
1333 s->control_regs.ghc = HOST_CTL_AHCI_EN;
1334
1335 for (i = 0; i < s->ports; i++) {
1336 pr = &s->dev[i].port_regs;
1337 pr->irq_stat = 0;
1338 pr->irq_mask = 0;
1339 pr->scr_ctl = 0;
1340 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;
1341 ahci_reset_port(s, i);
1342 }
1343 }
1344
1345 static const VMStateDescription vmstate_ahci_device = {
1346 .name = "ahci port",
1347 .version_id = 1,
1348 .fields = (VMStateField[]) {
1349 VMSTATE_IDE_BUS(port, AHCIDevice),
1350 VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice),
1351 VMSTATE_UINT32(port_state, AHCIDevice),
1352 VMSTATE_UINT32(finished, AHCIDevice),
1353 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice),
1354 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice),
1355 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice),
1356 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice),
1357 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice),
1358 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice),
1359 VMSTATE_UINT32(port_regs.cmd, AHCIDevice),
1360 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice),
1361 VMSTATE_UINT32(port_regs.sig, AHCIDevice),
1362 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice),
1363 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice),
1364 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice),
1365 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice),
1366 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice),
1367 VMSTATE_BOOL(done_atapi_packet, AHCIDevice),
1368 VMSTATE_INT32(busy_slot, AHCIDevice),
1369 VMSTATE_BOOL(init_d2h_sent, AHCIDevice),
1370 VMSTATE_END_OF_LIST()
1371 },
1372 };
1373
1374 static int ahci_state_post_load(void *opaque, int version_id)
1375 {
1376 int i;
1377 struct AHCIDevice *ad;
1378 AHCIState *s = opaque;
1379
1380 for (i = 0; i < s->ports; i++) {
1381 ad = &s->dev[i];
1382
1383 ahci_map_clb_address(ad);
1384 ahci_map_fis_address(ad);
1385 /*
1386 * If an error is present, ad->busy_slot will be valid and not -1.
1387 * In this case, an operation is waiting to resume and will re-check
1388 * for additional AHCI commands to execute upon completion.
1389 *
1390 * In the case where no error was present, busy_slot will be -1,
1391 * and we should check to see if there are additional commands waiting.
1392 */
1393 if (ad->busy_slot == -1) {
1394 check_cmd(s, i);
1395 } else {
1396 /* We are in the middle of a command, and may need to access
1397 * the command header in guest memory again. */
1398 if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) {
1399 return -1;
1400 }
1401 ad->cur_cmd = &((AHCICmdHdr *)ad->lst)[ad->busy_slot];
1402 }
1403 }
1404
1405 return 0;
1406 }
1407
1408 const VMStateDescription vmstate_ahci = {
1409 .name = "ahci",
1410 .version_id = 1,
1411 .post_load = ahci_state_post_load,
1412 .fields = (VMStateField[]) {
1413 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports,
1414 vmstate_ahci_device, AHCIDevice),
1415 VMSTATE_UINT32(control_regs.cap, AHCIState),
1416 VMSTATE_UINT32(control_regs.ghc, AHCIState),
1417 VMSTATE_UINT32(control_regs.irqstatus, AHCIState),
1418 VMSTATE_UINT32(control_regs.impl, AHCIState),
1419 VMSTATE_UINT32(control_regs.version, AHCIState),
1420 VMSTATE_UINT32(idp_index, AHCIState),
1421 VMSTATE_INT32_EQUAL(ports, AHCIState),
1422 VMSTATE_END_OF_LIST()
1423 },
1424 };
1425
1426 #define TYPE_SYSBUS_AHCI "sysbus-ahci"
1427 #define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
1428
1429 typedef struct SysbusAHCIState {
1430 /*< private >*/
1431 SysBusDevice parent_obj;
1432 /*< public >*/
1433
1434 AHCIState ahci;
1435 uint32_t num_ports;
1436 } SysbusAHCIState;
1437
1438 static const VMStateDescription vmstate_sysbus_ahci = {
1439 .name = "sysbus-ahci",
1440 .unmigratable = 1, /* Still buggy under I/O load */
1441 .fields = (VMStateField[]) {
1442 VMSTATE_AHCI(ahci, SysbusAHCIState),
1443 VMSTATE_END_OF_LIST()
1444 },
1445 };
1446
1447 static void sysbus_ahci_reset(DeviceState *dev)
1448 {
1449 SysbusAHCIState *s = SYSBUS_AHCI(dev);
1450
1451 ahci_reset(&s->ahci);
1452 }
1453
1454 static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
1455 {
1456 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1457 SysbusAHCIState *s = SYSBUS_AHCI(dev);
1458
1459 ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports);
1460
1461 sysbus_init_mmio(sbd, &s->ahci.mem);
1462 sysbus_init_irq(sbd, &s->ahci.irq);
1463 }
1464
1465 static Property sysbus_ahci_properties[] = {
1466 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
1467 DEFINE_PROP_END_OF_LIST(),
1468 };
1469
1470 static void sysbus_ahci_class_init(ObjectClass *klass, void *data)
1471 {
1472 DeviceClass *dc = DEVICE_CLASS(klass);
1473
1474 dc->realize = sysbus_ahci_realize;
1475 dc->vmsd = &vmstate_sysbus_ahci;
1476 dc->props = sysbus_ahci_properties;
1477 dc->reset = sysbus_ahci_reset;
1478 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1479 }
1480
1481 static const TypeInfo sysbus_ahci_info = {
1482 .name = TYPE_SYSBUS_AHCI,
1483 .parent = TYPE_SYS_BUS_DEVICE,
1484 .instance_size = sizeof(SysbusAHCIState),
1485 .class_init = sysbus_ahci_class_init,
1486 };
1487
1488 static void sysbus_ahci_register_types(void)
1489 {
1490 type_register_static(&sysbus_ahci_info);
1491 }
1492
1493 type_init(sysbus_ahci_register_types)
1494
1495 void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
1496 {
1497 AHCIPCIState *d = ICH_AHCI(dev);
1498 AHCIState *ahci = &d->ahci;
1499 int i;
1500
1501 for (i = 0; i < ahci->ports; i++) {
1502 if (hd[i] == NULL) {
1503 continue;
1504 }
1505 ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
1506 }
1507
1508 }
AR7 emulation for QEMU