2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "qemu/error-report.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "monitor/monitor.h"
17 #include "hw/ppc/fdt.h"
18 #include "hw/ppc/spapr.h"
19 #include "hw/ppc/spapr_xive.h"
20 #include "hw/ppc/xive.h"
21 #include "hw/ppc/xive_regs.h"
24 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
25 * use for the ESB pages and the TIMA pages
27 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
28 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
31 * The allocation of VP blocks is a complex operation in OPAL and the
32 * VP identifiers have a relation with the number of HW chips, the
33 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
34 * controller model does not have the same constraints and can use a
35 * simple mapping scheme of the CPU vcpu_id
37 * These identifiers are never returned to the OS.
40 #define SPAPR_XIVE_NVT_BASE 0x400
43 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value
44 * to the controller block id value. It can nevertheless be changed
45 * for testing purpose.
47 #define SPAPR_XIVE_BLOCK_ID 0x0
50 * sPAPR NVT and END indexing helpers
52 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
54 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
57 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
58 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
63 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
67 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
71 static int spapr_xive_target_to_nvt(uint32_t target
,
72 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
74 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
80 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
85 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
88 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
89 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
94 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
98 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
102 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
103 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
105 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
111 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
116 * On sPAPR machines, use a simplified output for the XIVE END
117 * structure dumping only the information related to the OS EQ.
119 static void spapr_xive_end_pic_print_info(sPAPRXive
*xive
, XiveEND
*end
,
122 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
123 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
124 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
125 uint32_t qentries
= 1 << (qsize
+ 10);
126 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
127 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
129 monitor_printf(mon
, "%3d/%d % 6d/%5d ^%d",
130 spapr_xive_nvt_to_target(0, nvt
),
131 priority
, qindex
, qentries
, qgen
);
133 xive_end_queue_pic_print_info(end
, 6, mon
);
134 monitor_printf(mon
, "]");
137 void spapr_xive_pic_print_info(sPAPRXive
*xive
, Monitor
*mon
)
139 XiveSource
*xsrc
= &xive
->source
;
142 monitor_printf(mon
, " LSIN PQ EISN CPU/PRIO EQ\n");
144 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
145 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
146 XiveEAS
*eas
= &xive
->eat
[i
];
148 if (!xive_eas_is_valid(eas
)) {
152 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
153 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
154 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
155 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
156 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
157 xive_eas_is_masked(eas
) ? "M" : " ",
158 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
160 if (!xive_eas_is_masked(eas
)) {
161 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
164 assert(end_idx
< xive
->nr_ends
);
165 end
= &xive
->endt
[end_idx
];
167 if (xive_end_is_valid(end
)) {
168 spapr_xive_end_pic_print_info(xive
, end
, mon
);
171 monitor_printf(mon
, "\n");
175 static void spapr_xive_map_mmio(sPAPRXive
*xive
)
177 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
178 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
179 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
183 * When a Virtual Processor is scheduled to run on a HW thread, the
184 * hypervisor pushes its identifier in the OS CAM line. Emulate the
185 * same behavior under QEMU.
187 void spapr_xive_set_tctx_os_cam(XiveTCTX
*tctx
)
193 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx
->cs
), &nvt_blk
, &nvt_idx
);
195 nvt_cam
= cpu_to_be32(TM_QW1W2_VO
| xive_nvt_cam_line(nvt_blk
, nvt_idx
));
196 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &nvt_cam
, 4);
199 static void spapr_xive_end_reset(XiveEND
*end
)
201 memset(end
, 0, sizeof(*end
));
203 /* switch off the escalation and notification ESBs */
204 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
207 static void spapr_xive_reset(void *dev
)
209 sPAPRXive
*xive
= SPAPR_XIVE(dev
);
213 * The XiveSource has its own reset handler, which mask off all
217 /* Mask all valid EASs in the IRQ number space. */
218 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
219 XiveEAS
*eas
= &xive
->eat
[i
];
220 if (xive_eas_is_valid(eas
)) {
221 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
228 for (i
= 0; i
< xive
->nr_ends
; i
++) {
229 spapr_xive_end_reset(&xive
->endt
[i
]);
233 static void spapr_xive_instance_init(Object
*obj
)
235 sPAPRXive
*xive
= SPAPR_XIVE(obj
);
237 object_initialize(&xive
->source
, sizeof(xive
->source
), TYPE_XIVE_SOURCE
);
238 object_property_add_child(obj
, "source", OBJECT(&xive
->source
), NULL
);
240 object_initialize(&xive
->end_source
, sizeof(xive
->end_source
),
241 TYPE_XIVE_END_SOURCE
);
242 object_property_add_child(obj
, "end_source", OBJECT(&xive
->end_source
),
246 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
248 sPAPRXive
*xive
= SPAPR_XIVE(dev
);
249 XiveSource
*xsrc
= &xive
->source
;
250 XiveENDSource
*end_xsrc
= &xive
->end_source
;
251 Error
*local_err
= NULL
;
253 if (!xive
->nr_irqs
) {
254 error_setg(errp
, "Number of interrupt needs to be greater 0");
258 if (!xive
->nr_ends
) {
259 error_setg(errp
, "Number of interrupt needs to be greater 0");
264 * Initialize the internal sources, for IPIs and virtual devices.
266 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
268 object_property_add_const_link(OBJECT(xsrc
), "xive", OBJECT(xive
),
270 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
272 error_propagate(errp
, local_err
);
277 * Initialize the END ESB source
279 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
281 object_property_add_const_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
283 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
285 error_propagate(errp
, local_err
);
289 /* Set the mapping address of the END ESB pages after the source ESBs */
290 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
293 * Allocate the routing tables
295 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
296 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
298 /* TIMA initialization */
299 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
300 "xive.tima", 4ull << TM_SHIFT
);
302 /* Define all XIVE MMIO regions on SysBus */
303 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
304 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
305 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
307 /* Map all regions */
308 spapr_xive_map_mmio(xive
);
310 qemu_register_reset(spapr_xive_reset
, dev
);
313 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
314 uint32_t eas_idx
, XiveEAS
*eas
)
316 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
318 if (eas_idx
>= xive
->nr_irqs
) {
322 *eas
= xive
->eat
[eas_idx
];
326 static int spapr_xive_get_end(XiveRouter
*xrtr
,
327 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
329 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
331 if (end_idx
>= xive
->nr_ends
) {
335 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
339 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
340 uint32_t end_idx
, XiveEND
*end
,
343 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
345 if (end_idx
>= xive
->nr_ends
) {
349 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
353 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
354 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
356 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
357 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
360 /* TODO: should we assert() if we can find a NVT ? */
365 * sPAPR does not maintain a NVT table. Return that the NVT is
366 * valid if we have found a matching CPU
368 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
372 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
373 uint32_t nvt_idx
, XiveNVT
*nvt
,
377 * We don't need to write back to the NVTs because the sPAPR
378 * machine should never hit a non-scheduled NVT. It should never
381 g_assert_not_reached();
384 static const VMStateDescription vmstate_spapr_xive_end
= {
385 .name
= TYPE_SPAPR_XIVE
"/end",
387 .minimum_version_id
= 1,
388 .fields
= (VMStateField
[]) {
389 VMSTATE_UINT32(w0
, XiveEND
),
390 VMSTATE_UINT32(w1
, XiveEND
),
391 VMSTATE_UINT32(w2
, XiveEND
),
392 VMSTATE_UINT32(w3
, XiveEND
),
393 VMSTATE_UINT32(w4
, XiveEND
),
394 VMSTATE_UINT32(w5
, XiveEND
),
395 VMSTATE_UINT32(w6
, XiveEND
),
396 VMSTATE_UINT32(w7
, XiveEND
),
397 VMSTATE_END_OF_LIST()
401 static const VMStateDescription vmstate_spapr_xive_eas
= {
402 .name
= TYPE_SPAPR_XIVE
"/eas",
404 .minimum_version_id
= 1,
405 .fields
= (VMStateField
[]) {
406 VMSTATE_UINT64(w
, XiveEAS
),
407 VMSTATE_END_OF_LIST()
411 static const VMStateDescription vmstate_spapr_xive
= {
412 .name
= TYPE_SPAPR_XIVE
,
414 .minimum_version_id
= 1,
415 .fields
= (VMStateField
[]) {
416 VMSTATE_UINT32_EQUAL(nr_irqs
, sPAPRXive
, NULL
),
417 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, sPAPRXive
, nr_irqs
,
418 vmstate_spapr_xive_eas
, XiveEAS
),
419 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, sPAPRXive
, nr_ends
,
420 vmstate_spapr_xive_end
, XiveEND
),
421 VMSTATE_END_OF_LIST()
425 static Property spapr_xive_properties
[] = {
426 DEFINE_PROP_UINT32("nr-irqs", sPAPRXive
, nr_irqs
, 0),
427 DEFINE_PROP_UINT32("nr-ends", sPAPRXive
, nr_ends
, 0),
428 DEFINE_PROP_UINT64("vc-base", sPAPRXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
429 DEFINE_PROP_UINT64("tm-base", sPAPRXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
430 DEFINE_PROP_END_OF_LIST(),
433 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
435 DeviceClass
*dc
= DEVICE_CLASS(klass
);
436 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
438 dc
->desc
= "sPAPR XIVE Interrupt Controller";
439 dc
->props
= spapr_xive_properties
;
440 dc
->realize
= spapr_xive_realize
;
441 dc
->vmsd
= &vmstate_spapr_xive
;
443 xrc
->get_eas
= spapr_xive_get_eas
;
444 xrc
->get_end
= spapr_xive_get_end
;
445 xrc
->write_end
= spapr_xive_write_end
;
446 xrc
->get_nvt
= spapr_xive_get_nvt
;
447 xrc
->write_nvt
= spapr_xive_write_nvt
;
450 static const TypeInfo spapr_xive_info
= {
451 .name
= TYPE_SPAPR_XIVE
,
452 .parent
= TYPE_XIVE_ROUTER
,
453 .instance_init
= spapr_xive_instance_init
,
454 .instance_size
= sizeof(sPAPRXive
),
455 .class_init
= spapr_xive_class_init
,
458 static void spapr_xive_register_types(void)
460 type_register_static(&spapr_xive_info
);
463 type_init(spapr_xive_register_types
)
465 bool spapr_xive_irq_claim(sPAPRXive
*xive
, uint32_t lisn
, bool lsi
)
467 XiveSource
*xsrc
= &xive
->source
;
469 if (lisn
>= xive
->nr_irqs
) {
473 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
);
474 xive_source_irq_set(xsrc
, lisn
, lsi
);
478 bool spapr_xive_irq_free(sPAPRXive
*xive
, uint32_t lisn
)
480 XiveSource
*xsrc
= &xive
->source
;
482 if (lisn
>= xive
->nr_irqs
) {
486 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
487 xive_source_irq_set(xsrc
, lisn
, false);
494 * The terminology used by the XIVE hcalls is the following :
497 * EQ Event Queue assigned by OS to receive event data
498 * ESB page for source interrupt management
499 * LISN Logical Interrupt Source Number identifying a source in the
501 * EISN Effective Interrupt Source Number used by guest OS to
502 * identify source in the guest
504 * The EAS, END, NVT structures are not exposed.
508 * Linux hosts under OPAL reserve priority 7 for their own escalation
509 * interrupts (DD2.X POWER9). So we only allow the guest to use
512 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
517 case 7: /* OPAL escalation queue */
524 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
525 * real address of the MMIO page through which the Event State Buffer
526 * entry associated with the value of the "lisn" parameter is managed.
532 * - R5: "lisn" is per "interrupts", "interrupt-map", or
533 * "ibm,xive-lisn-ranges" properties, or as returned by the
534 * ibm,query-interrupt-source-number RTAS call, or as returned
535 * by the H_ALLOCATE_VAS_WINDOW hcall
539 * Bits 0-59: Reserved
540 * Bit 60: H_INT_ESB must be used for Event State Buffer
542 * Bit 61: 1 == LSI 0 == MSI
543 * Bit 62: the full function page supports trigger
544 * Bit 63: Store EOI Supported
545 * - R5: Logical Real address of full function Event State Buffer
546 * management page, -1 if H_INT_ESB hcall flag is set to 1.
547 * - R6: Logical Real Address of trigger only Event State Buffer
548 * management page or -1.
549 * - R7: Power of 2 page size for the ESB management pages returned in
553 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
554 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
555 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
557 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
559 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
560 sPAPRMachineState
*spapr
,
564 sPAPRXive
*xive
= spapr
->xive
;
565 XiveSource
*xsrc
= &xive
->source
;
566 target_ulong flags
= args
[0];
567 target_ulong lisn
= args
[1];
569 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
577 if (lisn
>= xive
->nr_irqs
) {
578 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
583 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
584 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
590 * All sources are emulated under the main XIVE object and share
591 * the same characteristics.
594 if (!xive_source_esb_has_2page(xsrc
)) {
595 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
597 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
598 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
602 * Force the use of the H_INT_ESB hcall in case of an LSI
603 * interrupt. This is necessary under KVM to re-trigger the
604 * interrupt if the level is still asserted
606 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
607 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
610 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
611 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
616 if (xive_source_esb_has_2page(xsrc
) &&
617 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
618 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
623 if (xive_source_esb_has_2page(xsrc
)) {
624 args
[3] = xsrc
->esb_shift
- 1;
626 args
[3] = xsrc
->esb_shift
;
633 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
634 * Interrupt Source to a target. The Logical Interrupt Source is
635 * designated with the "lisn" parameter and the target is designated
636 * with the "target" and "priority" parameters. Upon return from the
637 * hcall(), no additional interrupts will be directed to the old EQ.
642 * Bits 0-61: Reserved
643 * Bit 62: set the "eisn" in the EAS
644 * Bit 63: masks the interrupt source in the hardware interrupt
645 * control structure. An interrupt masked by this mechanism will
646 * be dropped, but it's source state bits will still be
647 * set. There is no race-free way of unmasking and restoring the
648 * source. Thus this should only be used in interrupts that are
649 * also masked at the source, and only in cases where the
650 * interrupt is not meant to be used for a large amount of time
651 * because no valid target exists for it for example
652 * - R5: "lisn" is per "interrupts", "interrupt-map", or
653 * "ibm,xive-lisn-ranges" properties, or as returned by the
654 * ibm,query-interrupt-source-number RTAS call, or as returned by
655 * the H_ALLOCATE_VAS_WINDOW hcall
656 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
657 * "ibm,ppc-interrupt-gserver#s"
658 * - R7: "priority" is a valid priority not in
659 * "ibm,plat-res-int-priorities"
660 * - R8: "eisn" is the guest EISN associated with the "lisn"
666 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
667 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
669 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
670 sPAPRMachineState
*spapr
,
674 sPAPRXive
*xive
= spapr
->xive
;
675 XiveEAS eas
, new_eas
;
676 target_ulong flags
= args
[0];
677 target_ulong lisn
= args
[1];
678 target_ulong target
= args
[2];
679 target_ulong priority
= args
[3];
680 target_ulong eisn
= args
[4];
684 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
688 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
692 if (lisn
>= xive
->nr_irqs
) {
693 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
698 eas
= xive
->eat
[lisn
];
699 if (!xive_eas_is_valid(&eas
)) {
700 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
705 /* priority 0xff is used to reset the EAS */
706 if (priority
== 0xff) {
707 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
711 if (flags
& SPAPR_XIVE_SRC_MASK
) {
712 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
714 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
717 if (spapr_xive_priority_is_reserved(priority
)) {
718 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
719 " is reserved\n", priority
);
724 * Validate that "target" is part of the list of threads allocated
725 * to the partition. For that, find the END corresponding to the
728 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
732 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
733 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
735 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
736 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
740 xive
->eat
[lisn
] = new_eas
;
745 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
746 * target/priority pair is assigned to the specified Logical Interrupt
753 * - R5: "lisn" is per "interrupts", "interrupt-map", or
754 * "ibm,xive-lisn-ranges" properties, or as returned by the
755 * ibm,query-interrupt-source-number RTAS call, or as
756 * returned by the H_ALLOCATE_VAS_WINDOW hcall
759 * - R4: Target to which the specified Logical Interrupt Source is
761 * - R5: Priority to which the specified Logical Interrupt Source is
763 * - R6: EISN for the specified Logical Interrupt Source (this will be
764 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
766 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
767 sPAPRMachineState
*spapr
,
771 sPAPRXive
*xive
= spapr
->xive
;
772 target_ulong flags
= args
[0];
773 target_ulong lisn
= args
[1];
777 uint32_t end_idx
, nvt_idx
;
779 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
787 if (lisn
>= xive
->nr_irqs
) {
788 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
793 eas
= xive
->eat
[lisn
];
794 if (!xive_eas_is_valid(&eas
)) {
795 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
800 /* EAS_END_BLOCK is unused on sPAPR */
801 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
803 assert(end_idx
< xive
->nr_ends
);
804 end
= &xive
->endt
[end_idx
];
806 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
807 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
808 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
810 if (xive_eas_is_masked(&eas
)) {
813 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
816 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
822 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
823 * address of the notification management page associated with the
824 * specified target and priority.
830 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
831 * "ibm,ppc-interrupt-gserver#s"
832 * - R6: "priority" is a valid priority not in
833 * "ibm,plat-res-int-priorities"
836 * - R4: Logical real address of notification page
837 * - R5: Power of 2 page size of the notification page
839 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
840 sPAPRMachineState
*spapr
,
844 sPAPRXive
*xive
= spapr
->xive
;
845 XiveENDSource
*end_xsrc
= &xive
->end_source
;
846 target_ulong flags
= args
[0];
847 target_ulong target
= args
[1];
848 target_ulong priority
= args
[2];
853 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
862 * H_STATE should be returned if a H_INT_RESET is in progress.
863 * This is not needed when running the emulation under QEMU
866 if (spapr_xive_priority_is_reserved(priority
)) {
867 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
868 " is reserved\n", priority
);
873 * Validate that "target" is part of the list of threads allocated
874 * to the partition. For that, find the END corresponding to the
877 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
881 assert(end_idx
< xive
->nr_ends
);
882 end
= &xive
->endt
[end_idx
];
884 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
885 if (xive_end_is_enqueue(end
)) {
886 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
895 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
896 * a given "target" and "priority". It is also used to set the
897 * notification config associated with the EQ. An EQ size of 0 is
898 * used to reset the EQ config for a given target and priority. If
899 * resetting the EQ config, the END associated with the given "target"
900 * and "priority" will be changed to disable queueing.
902 * Upon return from the hcall(), no additional interrupts will be
903 * directed to the old EQ (if one was set). The old EQ (if one was
904 * set) should be investigated for interrupts that occurred prior to
905 * or during the hcall().
910 * Bits 0-62: Reserved
911 * Bit 63: Unconditional Notify (n) per the XIVE spec
912 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
913 * "ibm,ppc-interrupt-gserver#s"
914 * - R6: "priority" is a valid priority not in
915 * "ibm,plat-res-int-priorities"
916 * - R7: "eventQueue": The logical real address of the start of the EQ
917 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
923 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
925 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
926 sPAPRMachineState
*spapr
,
930 sPAPRXive
*xive
= spapr
->xive
;
931 target_ulong flags
= args
[0];
932 target_ulong target
= args
[1];
933 target_ulong priority
= args
[2];
934 target_ulong qpage
= args
[3];
935 target_ulong qsize
= args
[4];
937 uint8_t end_blk
, nvt_blk
;
938 uint32_t end_idx
, nvt_idx
;
940 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
944 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
949 * H_STATE should be returned if a H_INT_RESET is in progress.
950 * This is not needed when running the emulation under QEMU
953 if (spapr_xive_priority_is_reserved(priority
)) {
954 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
955 " is reserved\n", priority
);
960 * Validate that "target" is part of the list of threads allocated
961 * to the partition. For that, find the END corresponding to the
965 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
969 assert(end_idx
< xive
->nr_ends
);
970 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
977 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
978 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
979 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
980 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
983 /* reset queue and disable queueing */
984 spapr_xive_end_reset(&end
);
988 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
994 hwaddr plen
= 1 << qsize
;
998 * Validate the guest EQ. We should also check that the queue
999 * has been zeroed by the OS.
1001 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1002 MEMTXATTRS_UNSPECIFIED
);
1003 if (plen
!= 1 << qsize
) {
1004 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1005 HWADDR_PRIx
"\n", qpage
);
1008 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1011 /* "target" should have been validated above */
1012 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1013 g_assert_not_reached();
1017 * Ensure the priority and target are correctly set (they will not
1018 * be right after allocation)
1020 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1021 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1022 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1024 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1025 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1027 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1031 * The generation bit for the END starts at 1 and The END page
1032 * offset counter starts at 0.
1034 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1035 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1036 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1039 * TODO: issue syncs required to ensure all in-flight interrupts
1040 * are complete on the old END
1045 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1050 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1051 * target and priority.
1056 * Bits 0-62: Reserved
1057 * Bit 63: Debug: Return debug data
1058 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1059 * "ibm,ppc-interrupt-gserver#s"
1060 * - R6: "priority" is a valid priority not in
1061 * "ibm,plat-res-int-priorities"
1065 * Bits 0-61: Reserved
1066 * Bit 62: The value of Event Queue Generation Number (g) per
1067 * the XIVE spec if "Debug" = 1
1068 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1069 * - R5: The logical real address of the start of the EQ
1070 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1071 * - R7: The value of Event Queue Offset Counter per XIVE spec
1072 * if "Debug" = 1, else 0
1076 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1078 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1079 sPAPRMachineState
*spapr
,
1080 target_ulong opcode
,
1083 sPAPRXive
*xive
= spapr
->xive
;
1084 target_ulong flags
= args
[0];
1085 target_ulong target
= args
[1];
1086 target_ulong priority
= args
[2];
1091 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1095 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1100 * H_STATE should be returned if a H_INT_RESET is in progress.
1101 * This is not needed when running the emulation under QEMU
1104 if (spapr_xive_priority_is_reserved(priority
)) {
1105 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1106 " is reserved\n", priority
);
1111 * Validate that "target" is part of the list of threads allocated
1112 * to the partition. For that, find the END corresponding to the
1115 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1119 assert(end_idx
< xive
->nr_ends
);
1120 end
= &xive
->endt
[end_idx
];
1123 if (xive_end_is_notify(end
)) {
1124 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1127 if (xive_end_is_enqueue(end
)) {
1128 args
[1] = (uint64_t) be32_to_cpu(end
->w2
& 0x0fffffff) << 32
1129 | be32_to_cpu(end
->w3
);
1130 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1136 /* TODO: do we need any locking on the END ? */
1137 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1138 /* Load the event queue generation number into the return flags */
1139 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1141 /* Load R7 with the event queue offset counter */
1142 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1151 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1152 * reporting cache line pair for the calling thread. The reporting
1153 * cache lines will contain the OS interrupt context when the OS
1154 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1155 * interrupt. The reporting cache lines can be reset by inputting -1
1156 * in "reportingLine". Issuing the CI store byte without reporting
1157 * cache lines registered will result in the data not being accessible
1163 * Bits 0-63: Reserved
1164 * - R5: "reportingLine": The logical real address of the reporting cache
1170 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1171 sPAPRMachineState
*spapr
,
1172 target_ulong opcode
,
1175 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1180 * H_STATE should be returned if a H_INT_RESET is in progress.
1181 * This is not needed when running the emulation under QEMU
1184 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1189 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1190 * real address of the reporting cache line pair set for the input
1191 * "target". If no reporting cache line pair has been set, -1 is
1197 * Bits 0-63: Reserved
1198 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1199 * "ibm,ppc-interrupt-gserver#s"
1200 * - R6: "reportingLine": The logical real address of the reporting
1204 * - R4: The logical real address of the reporting line if set, else -1
1206 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1207 sPAPRMachineState
*spapr
,
1208 target_ulong opcode
,
1211 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1216 * H_STATE should be returned if a H_INT_RESET is in progress.
1217 * This is not needed when running the emulation under QEMU
1220 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1225 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1226 * page for the input "lisn". This hcall is only supported for LISNs
1227 * that have the ESB hcall flag set to 1 when returned from hcall()
1228 * H_INT_GET_SOURCE_INFO.
1233 * Bits 0-62: Reserved
1234 * bit 63: Store: Store=1, store operation, else load operation
1235 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1236 * "ibm,xive-lisn-ranges" properties, or as returned by the
1237 * ibm,query-interrupt-source-number RTAS call, or as
1238 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1239 * - R6: "esbOffset" is the offset into the ESB page for the load or
1241 * - R7: "storeData" is the data to write for a store operation
1244 * - R4: The value of the load if load operation, else -1
1247 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1249 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1250 sPAPRMachineState
*spapr
,
1251 target_ulong opcode
,
1254 sPAPRXive
*xive
= spapr
->xive
;
1256 target_ulong flags
= args
[0];
1257 target_ulong lisn
= args
[1];
1258 target_ulong offset
= args
[2];
1259 target_ulong data
= args
[3];
1261 XiveSource
*xsrc
= &xive
->source
;
1263 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1267 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1271 if (lisn
>= xive
->nr_irqs
) {
1272 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1277 eas
= xive
->eat
[lisn
];
1278 if (!xive_eas_is_valid(&eas
)) {
1279 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1284 if (offset
> (1ull << xsrc
->esb_shift
)) {
1288 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1290 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1291 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1292 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1293 HWADDR_PRIx
"\n", mmio_addr
);
1296 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1301 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1302 * ensure any in flight events for the input lisn are in the event
1308 * Bits 0-63: Reserved
1309 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1310 * "ibm,xive-lisn-ranges" properties, or as returned by the
1311 * ibm,query-interrupt-source-number RTAS call, or as
1312 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1317 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1318 sPAPRMachineState
*spapr
,
1319 target_ulong opcode
,
1322 sPAPRXive
*xive
= spapr
->xive
;
1324 target_ulong flags
= args
[0];
1325 target_ulong lisn
= args
[1];
1327 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1335 if (lisn
>= xive
->nr_irqs
) {
1336 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1341 eas
= xive
->eat
[lisn
];
1342 if (!xive_eas_is_valid(&eas
)) {
1343 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1349 * H_STATE should be returned if a H_INT_RESET is in progress.
1350 * This is not needed when running the emulation under QEMU
1353 /* This is not real hardware. Nothing to be done */
1358 * The H_INT_RESET hcall() is used to reset all of the partition's
1359 * interrupt exploitation structures to their initial state. This
1360 * means losing all previously set interrupt state set via
1361 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1366 * Bits 0-63: Reserved
1371 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1372 sPAPRMachineState
*spapr
,
1373 target_ulong opcode
,
1376 sPAPRXive
*xive
= spapr
->xive
;
1377 target_ulong flags
= args
[0];
1379 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1387 device_reset(DEVICE(xive
));
1391 void spapr_xive_hcall_init(sPAPRMachineState
*spapr
)
1393 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1394 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1395 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1396 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1397 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1398 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1399 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1400 h_int_set_os_reporting_line
);
1401 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1402 h_int_get_os_reporting_line
);
1403 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1404 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1405 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);
1408 void spapr_dt_xive(sPAPRMachineState
*spapr
, uint32_t nr_servers
, void *fdt
,
1411 sPAPRXive
*xive
= spapr
->xive
;
1413 uint64_t timas
[2 * 2];
1414 /* Interrupt number ranges for the IPIs */
1415 uint32_t lisn_ranges
[] = {
1417 cpu_to_be32(nr_servers
),
1420 * EQ size - the sizes of pages supported by the system 4K, 64K,
1421 * 2M, 16M. We only advertise 64K for the moment.
1423 uint32_t eq_sizes
[] = {
1424 cpu_to_be32(16), /* 64K */
1427 * The following array is in sync with the reserved priorities
1428 * defined by the 'spapr_xive_priority_is_reserved' routine.
1430 uint32_t plat_res_int_priorities
[] = {
1431 cpu_to_be32(7), /* start */
1432 cpu_to_be32(0xf8), /* count */
1436 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
1437 timas
[0] = cpu_to_be64(xive
->tm_base
+
1438 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
1439 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
1440 timas
[2] = cpu_to_be64(xive
->tm_base
+
1441 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
1442 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
1444 nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
1445 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
1446 _FDT(node
= fdt_add_subnode(fdt
, 0, nodename
));
1449 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
1450 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
1452 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
1453 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
1455 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
1456 sizeof(lisn_ranges
)));
1458 /* For Linux to link the LSIs to the interrupt controller. */
1459 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
1460 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
1463 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
1464 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
1467 * The "ibm,plat-res-int-priorities" property defines the priority
1468 * ranges reserved by the hypervisor
1470 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
1471 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));