target/arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 /* internal defines */
   5 typedef struct DisasContext {
   6     target_ulong pc;
   7     uint32_t insn;
   8     int is_jmp;
   9     /* Nonzero if this instruction has been conditionally skipped.  */
  10     int condjmp;
  11     /* The label that will be jumped to when the instruction is skipped.  */
  12     TCGLabel *condlabel;
  13     /* Thumb-2 conditional execution bits.  */
  14     int condexec_mask;
  15     int condexec_cond;
  16     struct TranslationBlock *tb;
  17     int singlestep_enabled;
  18     int thumb;
  19     int sctlr_b;
  20     TCGMemOp be_data;
  21 #if !defined(CONFIG_USER_ONLY)
  22     int user;
  23 #endif
  24     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  25     bool tbi0;         /* TBI0 for EL0/1 or TBI for EL2/3 */
  26     bool tbi1;         /* TBI1 for EL0/1, not used for EL2/3 */
  27     bool ns;        /* Use non-secure CPREG bank on access */
  28     int fp_excp_el; /* FP exception EL or 0 if enabled */
  29     /* Flag indicating that exceptions from secure mode are routed to EL3. */
  30     bool secure_routed_to_el3;
  31     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  32     int vec_len;
  33     int vec_stride;
  34     bool v7m_handler_mode;
  35     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  36      * so that top level loop can generate correct syndrome information.
  37      */
  38     uint32_t svc_imm;
  39     int aarch64;
  40     int current_el;
  41     GHashTable *cp_regs;
  42     uint64_t features; /* CPU features bits */
  43     /* Because unallocated encodings generate different exception syndrome
  44      * information from traps due to FP being disabled, we can't do a single
  45      * "is fp access disabled" check at a high level in the decode tree.
  46      * To help in catching bugs where the access check was forgotten in some
  47      * code path, we set this flag when the access check is done, and assert
  48      * that it is set at the point where we actually touch the FP regs.
  49      */
  50     bool fp_access_checked;
  51     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  52      * single-step support).
  53      */
  54     bool ss_active;
  55     bool pstate_ss;
  56     /* True if the insn just emitted was a load-exclusive instruction
  57      * (necessary for syndrome information for single step exceptions),
  58      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  59      */
  60     bool is_ldex;
  61     /* True if a single-step exception will be taken to the current EL */
  62     bool ss_same_el;
  63     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  64     int c15_cpar;
  65     /* TCG op index of the current insn_start.  */
  66     int insn_start_idx;
  67 #define TMP_A64_MAX 16
  68     int tmp_a64_count;
  69     TCGv_i64 tmp_a64[TMP_A64_MAX];
  70 } DisasContext;
  71
  72 typedef struct DisasCompare {
  73     TCGCond cond;
  74     TCGv_i32 value;
  75     bool value_global;
  76 } DisasCompare;
  77
  78 /* Share the TCG temporaries common between 32 and 64 bit modes.  */
  79 extern TCGv_env cpu_env;
  80 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
  81 extern TCGv_i64 cpu_exclusive_addr;
  82 extern TCGv_i64 cpu_exclusive_val;
  83
  84 static inline int arm_dc_feature(DisasContext *dc, int feature)
  85 {
  86     return (dc->features & (1ULL << feature)) != 0;
  87 }
  88
  89 static inline int get_mem_index(DisasContext *s)
  90 {
  91     return arm_to_core_mmu_idx(s->mmu_idx);
  92 }
  93
  94 /* Function used to determine the target exception EL when otherwise not known
  95  * or default.
  96  */
  97 static inline int default_exception_el(DisasContext *s)
  98 {
  99     /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
 100      * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
 101      * exceptions can only be routed to ELs above 1, so we target the higher of
 102      * 1 or the current EL.
 103      */
 104     return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
 105             ? 3 : MAX(1, s->current_el);
 106 }
 107
 108 static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 109 {
 110     /* We don't need to save all of the syndrome so we mask and shift
 111      * out unneeded bits to help the sleb128 encoder do a better job.
 112      */
 113     syn &= ARM_INSN_START_WORD2_MASK;
 114     syn >>= ARM_INSN_START_WORD2_SHIFT;
 115
 116     /* We check and clear insn_start_idx to catch multiple updates.  */
 117     assert(s->insn_start_idx != 0);
 118     tcg_set_insn_param(s->insn_start_idx, 2, syn);
 119     s->insn_start_idx = 0;
 120 }
 121
 122 /* target-specific extra values for is_jmp */
 123 /* These instructions trap after executing, so the A32/T32 decoder must
 124  * defer them until after the conditional execution state has been updated.
 125  * WFI also needs special handling when single-stepping.
 126  */
 127 #define DISAS_WFI 5
 128 #define DISAS_SWI 6
 129 /* WFE */
 130 #define DISAS_WFE 7
 131 #define DISAS_HVC 8
 132 #define DISAS_SMC 9
 133 #define DISAS_YIELD 10
 134 /* M profile branch which might be an exception return (and so needs
 135  * custom end-of-TB code)
 136  */
 137 #define DISAS_BX_EXCRET 11
 138 /* For instructions which want an immediate exit to the main loop,
 139  * as opposed to attempting to use lookup_and_goto_ptr. Unlike
 140  * DISAS_UPDATE this doesn't write the PC on exiting the translation
 141  * loop so you need to ensure something (gen_a64_set_pc_im or runtime
 142  * helper) has done so before we reach return from cpu_tb_exec.
 143  */
 144 #define DISAS_EXIT 12
 145
 146 #ifdef TARGET_AARCH64
 147 void a64_translate_init(void);
 148 void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb);
 149 void gen_a64_set_pc_im(uint64_t val);
 150 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 151                             fprintf_function cpu_fprintf, int flags);
 152 #else
 153 static inline void a64_translate_init(void)
 154 {
 155 }
 156
 157 static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb)
 158 {
 159 }
 160
 161 static inline void gen_a64_set_pc_im(uint64_t val)
 162 {
 163 }
 164
 165 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 166                                           fprintf_function cpu_fprintf,
 167                                           int flags)
 168 {
 169 }
 170 #endif
 171
 172 void arm_test_cc(DisasCompare *cmp, int cc);
 173 void arm_free_cc(DisasCompare *cmp);
 174 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 175 void arm_gen_test_cc(int cc, TCGLabel *label);
 176
 177 #endif /* TARGET_ARM_TRANSLATE_H */