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migration/ram: Fix some helper functions' parameter to use PageSearchStatus
[qemu/ar7.git] / target-m68k / translate.c
bloba402bd847ac90b61bb87fd93a1fd37721aafc05f
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "qemu/log.h"
26 #include "exec/cpu_ldst.h"
27
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
30
31 #include "trace-tcg.h"
32 #include "exec/log.h"
33
34
35 //#define DEBUG_DISPATCH 1
36
37 /* Fake floating point. */
38 #define tcg_gen_mov_f64 tcg_gen_mov_i64
39 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
40 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
41
42 #define DEFO32(name, offset) static TCGv QREG_##name;
43 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
44 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
45 #include "qregs.def"
46 #undef DEFO32
47 #undef DEFO64
48 #undef DEFF64
49
50 static TCGv_i32 cpu_halted;
51 static TCGv_i32 cpu_exception_index;
52
53 static TCGv_ptr cpu_env;
54
55 static char cpu_reg_names[3*8*3 + 5*4];
56 static TCGv cpu_dregs[8];
57 static TCGv cpu_aregs[8];
58 static TCGv_i64 cpu_fregs[8];
59 static TCGv_i64 cpu_macc[4];
60
61 #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]
62 #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]
63 #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]
64 #define MACREG(acc) cpu_macc[acc]
65 #define QREG_SP cpu_aregs[7]
66
67 static TCGv NULL_QREG;
68 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
69 /* Used to distinguish stores from bad addressing modes. */
70 static TCGv store_dummy;
71
72 #include "exec/gen-icount.h"
73
74 void m68k_tcg_init(void)
75 {
76 char *p;
77 int i;
78
79 #define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
80 #define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
81 #define DEFF64(name, offset) DEFO64(name, offset)
82 #include "qregs.def"
83 #undef DEFO32
84 #undef DEFO64
85 #undef DEFF64
86
87 cpu_halted = tcg_global_mem_new_i32(TCG_AREG0,
88 -offsetof(M68kCPU, env) +
89 offsetof(CPUState, halted), "HALTED");
90 cpu_exception_index = tcg_global_mem_new_i32(TCG_AREG0,
91 -offsetof(M68kCPU, env) +
92 offsetof(CPUState, exception_index),
93 "EXCEPTION");
94
95 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
96
97 p = cpu_reg_names;
98 for (i = 0; i < 8; i++) {
99 sprintf(p, "D%d", i);
100 cpu_dregs[i] = tcg_global_mem_new(TCG_AREG0,
101 offsetof(CPUM68KState, dregs[i]), p);
102 p += 3;
103 sprintf(p, "A%d", i);
104 cpu_aregs[i] = tcg_global_mem_new(TCG_AREG0,
105 offsetof(CPUM68KState, aregs[i]), p);
106 p += 3;
107 sprintf(p, "F%d", i);
108 cpu_fregs[i] = tcg_global_mem_new_i64(TCG_AREG0,
109 offsetof(CPUM68KState, fregs[i]), p);
110 p += 3;
111 }
112 for (i = 0; i < 4; i++) {
113 sprintf(p, "ACC%d", i);
114 cpu_macc[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUM68KState, macc[i]), p);
116 p += 5;
117 }
118
119 NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL");
120 store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL");
121 }
122
123 /* internal defines */
124 typedef struct DisasContext {
125 CPUM68KState *env;
126 target_ulong insn_pc; /* Start of the current instruction. */
127 target_ulong pc;
128 int is_jmp;
129 int cc_op;
130 int user;
131 uint32_t fpcr;
132 struct TranslationBlock *tb;
133 int singlestep_enabled;
134 TCGv_i64 mactmp;
135 int done_mac;
136 } DisasContext;
137
138 #define DISAS_JUMP_NEXT 4
139
140 #if defined(CONFIG_USER_ONLY)
141 #define IS_USER(s) 1
142 #else
143 #define IS_USER(s) s->user
144 #endif
145
146 /* XXX: move that elsewhere */
147 /* ??? Fix exceptions. */
148 static void *gen_throws_exception;
149 #define gen_last_qop NULL
150
151 #define OS_BYTE 0
152 #define OS_WORD 1
153 #define OS_LONG 2
154 #define OS_SINGLE 4
155 #define OS_DOUBLE 5
156
157 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
158
159 #ifdef DEBUG_DISPATCH
160 #define DISAS_INSN(name) \
161 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
162 uint16_t insn); \
163 static void disas_##name(CPUM68KState *env, DisasContext *s, \
164 uint16_t insn) \
165 { \
166 qemu_log("Dispatch " #name "\n"); \
167 real_disas_##name(s, env, insn); \
168 } \
169 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
170 uint16_t insn)
171 #else
172 #define DISAS_INSN(name) \
173 static void disas_##name(CPUM68KState *env, DisasContext *s, \
174 uint16_t insn)
175 #endif
176
177 /* Generate a load from the specified address. Narrow values are
178 sign extended to full register width. */
179 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
180 {
181 TCGv tmp;
182 int index = IS_USER(s);
183 tmp = tcg_temp_new_i32();
184 switch(opsize) {
185 case OS_BYTE:
186 if (sign)
187 tcg_gen_qemu_ld8s(tmp, addr, index);
188 else
189 tcg_gen_qemu_ld8u(tmp, addr, index);
190 break;
191 case OS_WORD:
192 if (sign)
193 tcg_gen_qemu_ld16s(tmp, addr, index);
194 else
195 tcg_gen_qemu_ld16u(tmp, addr, index);
196 break;
197 case OS_LONG:
198 case OS_SINGLE:
199 tcg_gen_qemu_ld32u(tmp, addr, index);
200 break;
201 default:
202 g_assert_not_reached();
203 }
204 gen_throws_exception = gen_last_qop;
205 return tmp;
206 }
207
208 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
209 {
210 TCGv_i64 tmp;
211 int index = IS_USER(s);
212 tmp = tcg_temp_new_i64();
213 tcg_gen_qemu_ldf64(tmp, addr, index);
214 gen_throws_exception = gen_last_qop;
215 return tmp;
216 }
217
218 /* Generate a store. */
219 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
220 {
221 int index = IS_USER(s);
222 switch(opsize) {
223 case OS_BYTE:
224 tcg_gen_qemu_st8(val, addr, index);
225 break;
226 case OS_WORD:
227 tcg_gen_qemu_st16(val, addr, index);
228 break;
229 case OS_LONG:
230 case OS_SINGLE:
231 tcg_gen_qemu_st32(val, addr, index);
232 break;
233 default:
234 g_assert_not_reached();
235 }
236 gen_throws_exception = gen_last_qop;
237 }
238
239 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
240 {
241 int index = IS_USER(s);
242 tcg_gen_qemu_stf64(val, addr, index);
243 gen_throws_exception = gen_last_qop;
244 }
245
246 typedef enum {
247 EA_STORE,
248 EA_LOADU,
249 EA_LOADS
250 } ea_what;
251
252 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
253 otherwise generate a store. */
254 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
255 ea_what what)
256 {
257 if (what == EA_STORE) {
258 gen_store(s, opsize, addr, val);
259 return store_dummy;
260 } else {
261 return gen_load(s, opsize, addr, what == EA_LOADS);
262 }
263 }
264
265 /* Read a 32-bit immediate constant. */
266 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
267 {
268 uint32_t im;
269 im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16;
270 s->pc += 2;
271 im |= cpu_lduw_code(env, s->pc);
272 s->pc += 2;
273 return im;
274 }
275
276 /* Calculate and address index. */
277 static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
278 {
279 TCGv add;
280 int scale;
281
282 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
283 if ((ext & 0x800) == 0) {
284 tcg_gen_ext16s_i32(tmp, add);
285 add = tmp;
286 }
287 scale = (ext >> 9) & 3;
288 if (scale != 0) {
289 tcg_gen_shli_i32(tmp, add, scale);
290 add = tmp;
291 }
292 return add;
293 }
294
295 /* Handle a base + index + displacement effective addresss.
296 A NULL_QREG base means pc-relative. */
297 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
298 {
299 uint32_t offset;
300 uint16_t ext;
301 TCGv add;
302 TCGv tmp;
303 uint32_t bd, od;
304
305 offset = s->pc;
306 ext = cpu_lduw_code(env, s->pc);
307 s->pc += 2;
308
309 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
310 return NULL_QREG;
311
312 if (ext & 0x100) {
313 /* full extension word format */
314 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
315 return NULL_QREG;
316
317 if ((ext & 0x30) > 0x10) {
318 /* base displacement */
319 if ((ext & 0x30) == 0x20) {
320 bd = (int16_t)cpu_lduw_code(env, s->pc);
321 s->pc += 2;
322 } else {
323 bd = read_im32(env, s);
324 }
325 } else {
326 bd = 0;
327 }
328 tmp = tcg_temp_new();
329 if ((ext & 0x44) == 0) {
330 /* pre-index */
331 add = gen_addr_index(ext, tmp);
332 } else {
333 add = NULL_QREG;
334 }
335 if ((ext & 0x80) == 0) {
336 /* base not suppressed */
337 if (IS_NULL_QREG(base)) {
338 base = tcg_const_i32(offset + bd);
339 bd = 0;
340 }
341 if (!IS_NULL_QREG(add)) {
342 tcg_gen_add_i32(tmp, add, base);
343 add = tmp;
344 } else {
345 add = base;
346 }
347 }
348 if (!IS_NULL_QREG(add)) {
349 if (bd != 0) {
350 tcg_gen_addi_i32(tmp, add, bd);
351 add = tmp;
352 }
353 } else {
354 add = tcg_const_i32(bd);
355 }
356 if ((ext & 3) != 0) {
357 /* memory indirect */
358 base = gen_load(s, OS_LONG, add, 0);
359 if ((ext & 0x44) == 4) {
360 add = gen_addr_index(ext, tmp);
361 tcg_gen_add_i32(tmp, add, base);
362 add = tmp;
363 } else {
364 add = base;
365 }
366 if ((ext & 3) > 1) {
367 /* outer displacement */
368 if ((ext & 3) == 2) {
369 od = (int16_t)cpu_lduw_code(env, s->pc);
370 s->pc += 2;
371 } else {
372 od = read_im32(env, s);
373 }
374 } else {
375 od = 0;
376 }
377 if (od != 0) {
378 tcg_gen_addi_i32(tmp, add, od);
379 add = tmp;
380 }
381 }
382 } else {
383 /* brief extension word format */
384 tmp = tcg_temp_new();
385 add = gen_addr_index(ext, tmp);
386 if (!IS_NULL_QREG(base)) {
387 tcg_gen_add_i32(tmp, add, base);
388 if ((int8_t)ext)
389 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
390 } else {
391 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
392 }
393 add = tmp;
394 }
395 return add;
396 }
397
398 /* Update the CPU env CC_OP state. */
399 static inline void gen_flush_cc_op(DisasContext *s)
400 {
401 if (s->cc_op != CC_OP_DYNAMIC)
402 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
403 }
404
405 /* Evaluate all the CC flags. */
406 static inline void gen_flush_flags(DisasContext *s)
407 {
408 if (s->cc_op == CC_OP_FLAGS)
409 return;
410 gen_flush_cc_op(s);
411 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
412 s->cc_op = CC_OP_FLAGS;
413 }
414
415 static void gen_logic_cc(DisasContext *s, TCGv val)
416 {
417 tcg_gen_mov_i32(QREG_CC_DEST, val);
418 s->cc_op = CC_OP_LOGIC;
419 }
420
421 static void gen_update_cc_add(TCGv dest, TCGv src)
422 {
423 tcg_gen_mov_i32(QREG_CC_DEST, dest);
424 tcg_gen_mov_i32(QREG_CC_SRC, src);
425 }
426
427 static inline int opsize_bytes(int opsize)
428 {
429 switch (opsize) {
430 case OS_BYTE: return 1;
431 case OS_WORD: return 2;
432 case OS_LONG: return 4;
433 case OS_SINGLE: return 4;
434 case OS_DOUBLE: return 8;
435 default:
436 g_assert_not_reached();
437 }
438 }
439
440 /* Assign value to a register. If the width is less than the register width
441 only the low part of the register is set. */
442 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
443 {
444 TCGv tmp;
445 switch (opsize) {
446 case OS_BYTE:
447 tcg_gen_andi_i32(reg, reg, 0xffffff00);
448 tmp = tcg_temp_new();
449 tcg_gen_ext8u_i32(tmp, val);
450 tcg_gen_or_i32(reg, reg, tmp);
451 break;
452 case OS_WORD:
453 tcg_gen_andi_i32(reg, reg, 0xffff0000);
454 tmp = tcg_temp_new();
455 tcg_gen_ext16u_i32(tmp, val);
456 tcg_gen_or_i32(reg, reg, tmp);
457 break;
458 case OS_LONG:
459 case OS_SINGLE:
460 tcg_gen_mov_i32(reg, val);
461 break;
462 default:
463 g_assert_not_reached();
464 }
465 }
466
467 /* Sign or zero extend a value. */
468 static inline TCGv gen_extend(TCGv val, int opsize, int sign)
469 {
470 TCGv tmp;
471
472 switch (opsize) {
473 case OS_BYTE:
474 tmp = tcg_temp_new();
475 if (sign)
476 tcg_gen_ext8s_i32(tmp, val);
477 else
478 tcg_gen_ext8u_i32(tmp, val);
479 break;
480 case OS_WORD:
481 tmp = tcg_temp_new();
482 if (sign)
483 tcg_gen_ext16s_i32(tmp, val);
484 else
485 tcg_gen_ext16u_i32(tmp, val);
486 break;
487 case OS_LONG:
488 case OS_SINGLE:
489 tmp = val;
490 break;
491 default:
492 g_assert_not_reached();
493 }
494 return tmp;
495 }
496
497 /* Generate code for an "effective address". Does not adjust the base
498 register for autoincrement addressing modes. */
499 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
500 int opsize)
501 {
502 TCGv reg;
503 TCGv tmp;
504 uint16_t ext;
505 uint32_t offset;
506
507 switch ((insn >> 3) & 7) {
508 case 0: /* Data register direct. */
509 case 1: /* Address register direct. */
510 return NULL_QREG;
511 case 2: /* Indirect register */
512 case 3: /* Indirect postincrement. */
513 return AREG(insn, 0);
514 case 4: /* Indirect predecrememnt. */
515 reg = AREG(insn, 0);
516 tmp = tcg_temp_new();
517 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
518 return tmp;
519 case 5: /* Indirect displacement. */
520 reg = AREG(insn, 0);
521 tmp = tcg_temp_new();
522 ext = cpu_lduw_code(env, s->pc);
523 s->pc += 2;
524 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
525 return tmp;
526 case 6: /* Indirect index + displacement. */
527 reg = AREG(insn, 0);
528 return gen_lea_indexed(env, s, reg);
529 case 7: /* Other */
530 switch (insn & 7) {
531 case 0: /* Absolute short. */
532 offset = cpu_ldsw_code(env, s->pc);
533 s->pc += 2;
534 return tcg_const_i32(offset);
535 case 1: /* Absolute long. */
536 offset = read_im32(env, s);
537 return tcg_const_i32(offset);
538 case 2: /* pc displacement */
539 offset = s->pc;
540 offset += cpu_ldsw_code(env, s->pc);
541 s->pc += 2;
542 return tcg_const_i32(offset);
543 case 3: /* pc index+displacement. */
544 return gen_lea_indexed(env, s, NULL_QREG);
545 case 4: /* Immediate. */
546 default:
547 return NULL_QREG;
548 }
549 }
550 /* Should never happen. */
551 return NULL_QREG;
552 }
553
554 /* Helper function for gen_ea. Reuse the computed address between the
555 for read/write operands. */
556 static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
557 uint16_t insn, int opsize, TCGv val,
558 TCGv *addrp, ea_what what)
559 {
560 TCGv tmp;
561
562 if (addrp && what == EA_STORE) {
563 tmp = *addrp;
564 } else {
565 tmp = gen_lea(env, s, insn, opsize);
566 if (IS_NULL_QREG(tmp))
567 return tmp;
568 if (addrp)
569 *addrp = tmp;
570 }
571 return gen_ldst(s, opsize, tmp, val, what);
572 }
573
574 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
575 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
576 ADDRP is non-null for readwrite operands. */
577 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
578 int opsize, TCGv val, TCGv *addrp, ea_what what)
579 {
580 TCGv reg;
581 TCGv result;
582 uint32_t offset;
583
584 switch ((insn >> 3) & 7) {
585 case 0: /* Data register direct. */
586 reg = DREG(insn, 0);
587 if (what == EA_STORE) {
588 gen_partset_reg(opsize, reg, val);
589 return store_dummy;
590 } else {
591 return gen_extend(reg, opsize, what == EA_LOADS);
592 }
593 case 1: /* Address register direct. */
594 reg = AREG(insn, 0);
595 if (what == EA_STORE) {
596 tcg_gen_mov_i32(reg, val);
597 return store_dummy;
598 } else {
599 return gen_extend(reg, opsize, what == EA_LOADS);
600 }
601 case 2: /* Indirect register */
602 reg = AREG(insn, 0);
603 return gen_ldst(s, opsize, reg, val, what);
604 case 3: /* Indirect postincrement. */
605 reg = AREG(insn, 0);
606 result = gen_ldst(s, opsize, reg, val, what);
607 /* ??? This is not exception safe. The instruction may still
608 fault after this point. */
609 if (what == EA_STORE || !addrp)
610 tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
611 return result;
612 case 4: /* Indirect predecrememnt. */
613 {
614 TCGv tmp;
615 if (addrp && what == EA_STORE) {
616 tmp = *addrp;
617 } else {
618 tmp = gen_lea(env, s, insn, opsize);
619 if (IS_NULL_QREG(tmp))
620 return tmp;
621 if (addrp)
622 *addrp = tmp;
623 }
624 result = gen_ldst(s, opsize, tmp, val, what);
625 /* ??? This is not exception safe. The instruction may still
626 fault after this point. */
627 if (what == EA_STORE || !addrp) {
628 reg = AREG(insn, 0);
629 tcg_gen_mov_i32(reg, tmp);
630 }
631 }
632 return result;
633 case 5: /* Indirect displacement. */
634 case 6: /* Indirect index + displacement. */
635 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
636 case 7: /* Other */
637 switch (insn & 7) {
638 case 0: /* Absolute short. */
639 case 1: /* Absolute long. */
640 case 2: /* pc displacement */
641 case 3: /* pc index+displacement. */
642 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
643 case 4: /* Immediate. */
644 /* Sign extend values for consistency. */
645 switch (opsize) {
646 case OS_BYTE:
647 if (what == EA_LOADS) {
648 offset = cpu_ldsb_code(env, s->pc + 1);
649 } else {
650 offset = cpu_ldub_code(env, s->pc + 1);
651 }
652 s->pc += 2;
653 break;
654 case OS_WORD:
655 if (what == EA_LOADS) {
656 offset = cpu_ldsw_code(env, s->pc);
657 } else {
658 offset = cpu_lduw_code(env, s->pc);
659 }
660 s->pc += 2;
661 break;
662 case OS_LONG:
663 offset = read_im32(env, s);
664 break;
665 default:
666 g_assert_not_reached();
667 }
668 return tcg_const_i32(offset);
669 default:
670 return NULL_QREG;
671 }
672 }
673 /* Should never happen. */
674 return NULL_QREG;
675 }
676
677 /* This generates a conditional branch, clobbering all temporaries. */
678 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
679 {
680 TCGv tmp;
681
682 /* TODO: Optimize compare/branch pairs rather than always flushing
683 flag state to CC_OP_FLAGS. */
684 gen_flush_flags(s);
685 switch (cond) {
686 case 0: /* T */
687 tcg_gen_br(l1);
688 break;
689 case 1: /* F */
690 break;
691 case 2: /* HI (!C && !Z) */
692 tmp = tcg_temp_new();
693 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
694 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
695 break;
696 case 3: /* LS (C || Z) */
697 tmp = tcg_temp_new();
698 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
699 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
700 break;
701 case 4: /* CC (!C) */
702 tmp = tcg_temp_new();
703 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
704 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
705 break;
706 case 5: /* CS (C) */
707 tmp = tcg_temp_new();
708 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
709 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
710 break;
711 case 6: /* NE (!Z) */
712 tmp = tcg_temp_new();
713 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
714 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
715 break;
716 case 7: /* EQ (Z) */
717 tmp = tcg_temp_new();
718 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
719 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
720 break;
721 case 8: /* VC (!V) */
722 tmp = tcg_temp_new();
723 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
724 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
725 break;
726 case 9: /* VS (V) */
727 tmp = tcg_temp_new();
728 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
729 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
730 break;
731 case 10: /* PL (!N) */
732 tmp = tcg_temp_new();
733 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
734 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
735 break;
736 case 11: /* MI (N) */
737 tmp = tcg_temp_new();
738 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
739 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
740 break;
741 case 12: /* GE (!(N ^ V)) */
742 tmp = tcg_temp_new();
743 assert(CCF_V == (CCF_N >> 2));
744 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
745 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
746 tcg_gen_andi_i32(tmp, tmp, CCF_V);
747 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
748 break;
749 case 13: /* LT (N ^ V) */
750 tmp = tcg_temp_new();
751 assert(CCF_V == (CCF_N >> 2));
752 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
753 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
754 tcg_gen_andi_i32(tmp, tmp, CCF_V);
755 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
756 break;
757 case 14: /* GT (!(Z || (N ^ V))) */
758 tmp = tcg_temp_new();
759 assert(CCF_V == (CCF_N >> 2));
760 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
761 tcg_gen_shri_i32(tmp, tmp, 2);
762 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
763 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
764 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
765 break;
766 case 15: /* LE (Z || (N ^ V)) */
767 tmp = tcg_temp_new();
768 assert(CCF_V == (CCF_N >> 2));
769 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
770 tcg_gen_shri_i32(tmp, tmp, 2);
771 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
772 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
773 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
774 break;
775 default:
776 /* Should ever happen. */
777 abort();
778 }
779 }
780
781 DISAS_INSN(scc)
782 {
783 TCGLabel *l1;
784 int cond;
785 TCGv reg;
786
787 l1 = gen_new_label();
788 cond = (insn >> 8) & 0xf;
789 reg = DREG(insn, 0);
790 tcg_gen_andi_i32(reg, reg, 0xffffff00);
791 /* This is safe because we modify the reg directly, with no other values
792 live. */
793 gen_jmpcc(s, cond ^ 1, l1);
794 tcg_gen_ori_i32(reg, reg, 0xff);
795 gen_set_label(l1);
796 }
797
798 /* Force a TB lookup after an instruction that changes the CPU state. */
799 static void gen_lookup_tb(DisasContext *s)
800 {
801 gen_flush_cc_op(s);
802 tcg_gen_movi_i32(QREG_PC, s->pc);
803 s->is_jmp = DISAS_UPDATE;
804 }
805
806 /* Generate a jump to an immediate address. */
807 static void gen_jmp_im(DisasContext *s, uint32_t dest)
808 {
809 gen_flush_cc_op(s);
810 tcg_gen_movi_i32(QREG_PC, dest);
811 s->is_jmp = DISAS_JUMP;
812 }
813
814 /* Generate a jump to the address in qreg DEST. */
815 static void gen_jmp(DisasContext *s, TCGv dest)
816 {
817 gen_flush_cc_op(s);
818 tcg_gen_mov_i32(QREG_PC, dest);
819 s->is_jmp = DISAS_JUMP;
820 }
821
822 static void gen_exception(DisasContext *s, uint32_t where, int nr)
823 {
824 gen_flush_cc_op(s);
825 gen_jmp_im(s, where);
826 gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
827 }
828
829 static inline void gen_addr_fault(DisasContext *s)
830 {
831 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
832 }
833
834 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
835 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
836 op_sign ? EA_LOADS : EA_LOADU); \
837 if (IS_NULL_QREG(result)) { \
838 gen_addr_fault(s); \
839 return; \
840 } \
841 } while (0)
842
843 #define DEST_EA(env, insn, opsize, val, addrp) do { \
844 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
845 if (IS_NULL_QREG(ea_result)) { \
846 gen_addr_fault(s); \
847 return; \
848 } \
849 } while (0)
850
851 /* Generate a jump to an immediate address. */
852 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
853 {
854 TranslationBlock *tb;
855
856 tb = s->tb;
857 if (unlikely(s->singlestep_enabled)) {
858 gen_exception(s, dest, EXCP_DEBUG);
859 } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
860 (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
861 tcg_gen_goto_tb(n);
862 tcg_gen_movi_i32(QREG_PC, dest);
863 tcg_gen_exit_tb((uintptr_t)tb + n);
864 } else {
865 gen_jmp_im(s, dest);
866 tcg_gen_exit_tb(0);
867 }
868 s->is_jmp = DISAS_TB_JUMP;
869 }
870
871 DISAS_INSN(undef_mac)
872 {
873 gen_exception(s, s->pc - 2, EXCP_LINEA);
874 }
875
876 DISAS_INSN(undef_fpu)
877 {
878 gen_exception(s, s->pc - 2, EXCP_LINEF);
879 }
880
881 DISAS_INSN(undef)
882 {
883 M68kCPU *cpu = m68k_env_get_cpu(env);
884
885 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
886 cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
887 }
888
889 DISAS_INSN(mulw)
890 {
891 TCGv reg;
892 TCGv tmp;
893 TCGv src;
894 int sign;
895
896 sign = (insn & 0x100) != 0;
897 reg = DREG(insn, 9);
898 tmp = tcg_temp_new();
899 if (sign)
900 tcg_gen_ext16s_i32(tmp, reg);
901 else
902 tcg_gen_ext16u_i32(tmp, reg);
903 SRC_EA(env, src, OS_WORD, sign, NULL);
904 tcg_gen_mul_i32(tmp, tmp, src);
905 tcg_gen_mov_i32(reg, tmp);
906 /* Unlike m68k, coldfire always clears the overflow bit. */
907 gen_logic_cc(s, tmp);
908 }
909
910 DISAS_INSN(divw)
911 {
912 TCGv reg;
913 TCGv tmp;
914 TCGv src;
915 int sign;
916
917 sign = (insn & 0x100) != 0;
918 reg = DREG(insn, 9);
919 if (sign) {
920 tcg_gen_ext16s_i32(QREG_DIV1, reg);
921 } else {
922 tcg_gen_ext16u_i32(QREG_DIV1, reg);
923 }
924 SRC_EA(env, src, OS_WORD, sign, NULL);
925 tcg_gen_mov_i32(QREG_DIV2, src);
926 if (sign) {
927 gen_helper_divs(cpu_env, tcg_const_i32(1));
928 } else {
929 gen_helper_divu(cpu_env, tcg_const_i32(1));
930 }
931
932 tmp = tcg_temp_new();
933 src = tcg_temp_new();
934 tcg_gen_ext16u_i32(tmp, QREG_DIV1);
935 tcg_gen_shli_i32(src, QREG_DIV2, 16);
936 tcg_gen_or_i32(reg, tmp, src);
937 s->cc_op = CC_OP_FLAGS;
938 }
939
940 DISAS_INSN(divl)
941 {
942 TCGv num;
943 TCGv den;
944 TCGv reg;
945 uint16_t ext;
946
947 ext = cpu_lduw_code(env, s->pc);
948 s->pc += 2;
949 if (ext & 0x87f8) {
950 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
951 return;
952 }
953 num = DREG(ext, 12);
954 reg = DREG(ext, 0);
955 tcg_gen_mov_i32(QREG_DIV1, num);
956 SRC_EA(env, den, OS_LONG, 0, NULL);
957 tcg_gen_mov_i32(QREG_DIV2, den);
958 if (ext & 0x0800) {
959 gen_helper_divs(cpu_env, tcg_const_i32(0));
960 } else {
961 gen_helper_divu(cpu_env, tcg_const_i32(0));
962 }
963 if ((ext & 7) == ((ext >> 12) & 7)) {
964 /* div */
965 tcg_gen_mov_i32 (reg, QREG_DIV1);
966 } else {
967 /* rem */
968 tcg_gen_mov_i32 (reg, QREG_DIV2);
969 }
970 s->cc_op = CC_OP_FLAGS;
971 }
972
973 DISAS_INSN(addsub)
974 {
975 TCGv reg;
976 TCGv dest;
977 TCGv src;
978 TCGv tmp;
979 TCGv addr;
980 int add;
981
982 add = (insn & 0x4000) != 0;
983 reg = DREG(insn, 9);
984 dest = tcg_temp_new();
985 if (insn & 0x100) {
986 SRC_EA(env, tmp, OS_LONG, 0, &addr);
987 src = reg;
988 } else {
989 tmp = reg;
990 SRC_EA(env, src, OS_LONG, 0, NULL);
991 }
992 if (add) {
993 tcg_gen_add_i32(dest, tmp, src);
994 gen_helper_xflag_lt(QREG_CC_X, dest, src);
995 s->cc_op = CC_OP_ADD;
996 } else {
997 gen_helper_xflag_lt(QREG_CC_X, tmp, src);
998 tcg_gen_sub_i32(dest, tmp, src);
999 s->cc_op = CC_OP_SUB;
1000 }
1001 gen_update_cc_add(dest, src);
1002 if (insn & 0x100) {
1003 DEST_EA(env, insn, OS_LONG, dest, &addr);
1004 } else {
1005 tcg_gen_mov_i32(reg, dest);
1006 }
1007 }
1008
1009
1010 /* Reverse the order of the bits in REG. */
1011 DISAS_INSN(bitrev)
1012 {
1013 TCGv reg;
1014 reg = DREG(insn, 0);
1015 gen_helper_bitrev(reg, reg);
1016 }
1017
1018 DISAS_INSN(bitop_reg)
1019 {
1020 int opsize;
1021 int op;
1022 TCGv src1;
1023 TCGv src2;
1024 TCGv tmp;
1025 TCGv addr;
1026 TCGv dest;
1027
1028 if ((insn & 0x38) != 0)
1029 opsize = OS_BYTE;
1030 else
1031 opsize = OS_LONG;
1032 op = (insn >> 6) & 3;
1033 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1034 src2 = DREG(insn, 9);
1035 dest = tcg_temp_new();
1036
1037 gen_flush_flags(s);
1038 tmp = tcg_temp_new();
1039 if (opsize == OS_BYTE)
1040 tcg_gen_andi_i32(tmp, src2, 7);
1041 else
1042 tcg_gen_andi_i32(tmp, src2, 31);
1043 src2 = tmp;
1044 tmp = tcg_temp_new();
1045 tcg_gen_shr_i32(tmp, src1, src2);
1046 tcg_gen_andi_i32(tmp, tmp, 1);
1047 tcg_gen_shli_i32(tmp, tmp, 2);
1048 /* Clear CCF_Z if bit set. */
1049 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1050 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1051
1052 tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2);
1053 switch (op) {
1054 case 1: /* bchg */
1055 tcg_gen_xor_i32(dest, src1, tmp);
1056 break;
1057 case 2: /* bclr */
1058 tcg_gen_not_i32(tmp, tmp);
1059 tcg_gen_and_i32(dest, src1, tmp);
1060 break;
1061 case 3: /* bset */
1062 tcg_gen_or_i32(dest, src1, tmp);
1063 break;
1064 default: /* btst */
1065 break;
1066 }
1067 if (op)
1068 DEST_EA(env, insn, opsize, dest, &addr);
1069 }
1070
1071 DISAS_INSN(sats)
1072 {
1073 TCGv reg;
1074 reg = DREG(insn, 0);
1075 gen_flush_flags(s);
1076 gen_helper_sats(reg, reg, QREG_CC_DEST);
1077 gen_logic_cc(s, reg);
1078 }
1079
1080 static void gen_push(DisasContext *s, TCGv val)
1081 {
1082 TCGv tmp;
1083
1084 tmp = tcg_temp_new();
1085 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1086 gen_store(s, OS_LONG, tmp, val);
1087 tcg_gen_mov_i32(QREG_SP, tmp);
1088 }
1089
1090 DISAS_INSN(movem)
1091 {
1092 TCGv addr;
1093 int i;
1094 uint16_t mask;
1095 TCGv reg;
1096 TCGv tmp;
1097 int is_load;
1098
1099 mask = cpu_lduw_code(env, s->pc);
1100 s->pc += 2;
1101 tmp = gen_lea(env, s, insn, OS_LONG);
1102 if (IS_NULL_QREG(tmp)) {
1103 gen_addr_fault(s);
1104 return;
1105 }
1106 addr = tcg_temp_new();
1107 tcg_gen_mov_i32(addr, tmp);
1108 is_load = ((insn & 0x0400) != 0);
1109 for (i = 0; i < 16; i++, mask >>= 1) {
1110 if (mask & 1) {
1111 if (i < 8)
1112 reg = DREG(i, 0);
1113 else
1114 reg = AREG(i, 0);
1115 if (is_load) {
1116 tmp = gen_load(s, OS_LONG, addr, 0);
1117 tcg_gen_mov_i32(reg, tmp);
1118 } else {
1119 gen_store(s, OS_LONG, addr, reg);
1120 }
1121 if (mask != 1)
1122 tcg_gen_addi_i32(addr, addr, 4);
1123 }
1124 }
1125 }
1126
1127 DISAS_INSN(bitop_im)
1128 {
1129 int opsize;
1130 int op;
1131 TCGv src1;
1132 uint32_t mask;
1133 int bitnum;
1134 TCGv tmp;
1135 TCGv addr;
1136
1137 if ((insn & 0x38) != 0)
1138 opsize = OS_BYTE;
1139 else
1140 opsize = OS_LONG;
1141 op = (insn >> 6) & 3;
1142
1143 bitnum = cpu_lduw_code(env, s->pc);
1144 s->pc += 2;
1145 if (bitnum & 0xff00) {
1146 disas_undef(env, s, insn);
1147 return;
1148 }
1149
1150 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1151
1152 gen_flush_flags(s);
1153 if (opsize == OS_BYTE)
1154 bitnum &= 7;
1155 else
1156 bitnum &= 31;
1157 mask = 1 << bitnum;
1158
1159 tmp = tcg_temp_new();
1160 assert (CCF_Z == (1 << 2));
1161 if (bitnum > 2)
1162 tcg_gen_shri_i32(tmp, src1, bitnum - 2);
1163 else if (bitnum < 2)
1164 tcg_gen_shli_i32(tmp, src1, 2 - bitnum);
1165 else
1166 tcg_gen_mov_i32(tmp, src1);
1167 tcg_gen_andi_i32(tmp, tmp, CCF_Z);
1168 /* Clear CCF_Z if bit set. */
1169 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1170 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1171 if (op) {
1172 switch (op) {
1173 case 1: /* bchg */
1174 tcg_gen_xori_i32(tmp, src1, mask);
1175 break;
1176 case 2: /* bclr */
1177 tcg_gen_andi_i32(tmp, src1, ~mask);
1178 break;
1179 case 3: /* bset */
1180 tcg_gen_ori_i32(tmp, src1, mask);
1181 break;
1182 default: /* btst */
1183 break;
1184 }
1185 DEST_EA(env, insn, opsize, tmp, &addr);
1186 }
1187 }
1188
1189 DISAS_INSN(arith_im)
1190 {
1191 int op;
1192 uint32_t im;
1193 TCGv src1;
1194 TCGv dest;
1195 TCGv addr;
1196
1197 op = (insn >> 9) & 7;
1198 SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
1199 im = read_im32(env, s);
1200 dest = tcg_temp_new();
1201 switch (op) {
1202 case 0: /* ori */
1203 tcg_gen_ori_i32(dest, src1, im);
1204 gen_logic_cc(s, dest);
1205 break;
1206 case 1: /* andi */
1207 tcg_gen_andi_i32(dest, src1, im);
1208 gen_logic_cc(s, dest);
1209 break;
1210 case 2: /* subi */
1211 tcg_gen_mov_i32(dest, src1);
1212 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1213 tcg_gen_subi_i32(dest, dest, im);
1214 gen_update_cc_add(dest, tcg_const_i32(im));
1215 s->cc_op = CC_OP_SUB;
1216 break;
1217 case 3: /* addi */
1218 tcg_gen_mov_i32(dest, src1);
1219 tcg_gen_addi_i32(dest, dest, im);
1220 gen_update_cc_add(dest, tcg_const_i32(im));
1221 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1222 s->cc_op = CC_OP_ADD;
1223 break;
1224 case 5: /* eori */
1225 tcg_gen_xori_i32(dest, src1, im);
1226 gen_logic_cc(s, dest);
1227 break;
1228 case 6: /* cmpi */
1229 tcg_gen_mov_i32(dest, src1);
1230 tcg_gen_subi_i32(dest, dest, im);
1231 gen_update_cc_add(dest, tcg_const_i32(im));
1232 s->cc_op = CC_OP_SUB;
1233 break;
1234 default:
1235 abort();
1236 }
1237 if (op != 6) {
1238 DEST_EA(env, insn, OS_LONG, dest, &addr);
1239 }
1240 }
1241
1242 DISAS_INSN(byterev)
1243 {
1244 TCGv reg;
1245
1246 reg = DREG(insn, 0);
1247 tcg_gen_bswap32_i32(reg, reg);
1248 }
1249
1250 DISAS_INSN(move)
1251 {
1252 TCGv src;
1253 TCGv dest;
1254 int op;
1255 int opsize;
1256
1257 switch (insn >> 12) {
1258 case 1: /* move.b */
1259 opsize = OS_BYTE;
1260 break;
1261 case 2: /* move.l */
1262 opsize = OS_LONG;
1263 break;
1264 case 3: /* move.w */
1265 opsize = OS_WORD;
1266 break;
1267 default:
1268 abort();
1269 }
1270 SRC_EA(env, src, opsize, 1, NULL);
1271 op = (insn >> 6) & 7;
1272 if (op == 1) {
1273 /* movea */
1274 /* The value will already have been sign extended. */
1275 dest = AREG(insn, 9);
1276 tcg_gen_mov_i32(dest, src);
1277 } else {
1278 /* normal move */
1279 uint16_t dest_ea;
1280 dest_ea = ((insn >> 9) & 7) | (op << 3);
1281 DEST_EA(env, dest_ea, opsize, src, NULL);
1282 /* This will be correct because loads sign extend. */
1283 gen_logic_cc(s, src);
1284 }
1285 }
1286
1287 DISAS_INSN(negx)
1288 {
1289 TCGv reg;
1290
1291 gen_flush_flags(s);
1292 reg = DREG(insn, 0);
1293 gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg);
1294 }
1295
1296 DISAS_INSN(lea)
1297 {
1298 TCGv reg;
1299 TCGv tmp;
1300
1301 reg = AREG(insn, 9);
1302 tmp = gen_lea(env, s, insn, OS_LONG);
1303 if (IS_NULL_QREG(tmp)) {
1304 gen_addr_fault(s);
1305 return;
1306 }
1307 tcg_gen_mov_i32(reg, tmp);
1308 }
1309
1310 DISAS_INSN(clr)
1311 {
1312 int opsize;
1313
1314 switch ((insn >> 6) & 3) {
1315 case 0: /* clr.b */
1316 opsize = OS_BYTE;
1317 break;
1318 case 1: /* clr.w */
1319 opsize = OS_WORD;
1320 break;
1321 case 2: /* clr.l */
1322 opsize = OS_LONG;
1323 break;
1324 default:
1325 abort();
1326 }
1327 DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
1328 gen_logic_cc(s, tcg_const_i32(0));
1329 }
1330
1331 static TCGv gen_get_ccr(DisasContext *s)
1332 {
1333 TCGv dest;
1334
1335 gen_flush_flags(s);
1336 dest = tcg_temp_new();
1337 tcg_gen_shli_i32(dest, QREG_CC_X, 4);
1338 tcg_gen_or_i32(dest, dest, QREG_CC_DEST);
1339 return dest;
1340 }
1341
1342 DISAS_INSN(move_from_ccr)
1343 {
1344 TCGv reg;
1345 TCGv ccr;
1346
1347 ccr = gen_get_ccr(s);
1348 reg = DREG(insn, 0);
1349 gen_partset_reg(OS_WORD, reg, ccr);
1350 }
1351
1352 DISAS_INSN(neg)
1353 {
1354 TCGv reg;
1355 TCGv src1;
1356
1357 reg = DREG(insn, 0);
1358 src1 = tcg_temp_new();
1359 tcg_gen_mov_i32(src1, reg);
1360 tcg_gen_neg_i32(reg, src1);
1361 s->cc_op = CC_OP_SUB;
1362 gen_update_cc_add(reg, src1);
1363 gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1);
1364 s->cc_op = CC_OP_SUB;
1365 }
1366
1367 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
1368 {
1369 tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf);
1370 tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4);
1371 if (!ccr_only) {
1372 gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00));
1373 }
1374 }
1375
1376 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
1377 int ccr_only)
1378 {
1379 TCGv tmp;
1380 TCGv reg;
1381
1382 s->cc_op = CC_OP_FLAGS;
1383 if ((insn & 0x38) == 0)
1384 {
1385 tmp = tcg_temp_new();
1386 reg = DREG(insn, 0);
1387 tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf);
1388 tcg_gen_shri_i32(tmp, reg, 4);
1389 tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
1390 if (!ccr_only) {
1391 gen_helper_set_sr(cpu_env, reg);
1392 }
1393 }
1394 else if ((insn & 0x3f) == 0x3c)
1395 {
1396 uint16_t val;
1397 val = cpu_lduw_code(env, s->pc);
1398 s->pc += 2;
1399 gen_set_sr_im(s, val, ccr_only);
1400 }
1401 else
1402 disas_undef(env, s, insn);
1403 }
1404
1405 DISAS_INSN(move_to_ccr)
1406 {
1407 gen_set_sr(env, s, insn, 1);
1408 }
1409
1410 DISAS_INSN(not)
1411 {
1412 TCGv reg;
1413
1414 reg = DREG(insn, 0);
1415 tcg_gen_not_i32(reg, reg);
1416 gen_logic_cc(s, reg);
1417 }
1418
1419 DISAS_INSN(swap)
1420 {
1421 TCGv src1;
1422 TCGv src2;
1423 TCGv reg;
1424
1425 src1 = tcg_temp_new();
1426 src2 = tcg_temp_new();
1427 reg = DREG(insn, 0);
1428 tcg_gen_shli_i32(src1, reg, 16);
1429 tcg_gen_shri_i32(src2, reg, 16);
1430 tcg_gen_or_i32(reg, src1, src2);
1431 gen_logic_cc(s, reg);
1432 }
1433
1434 DISAS_INSN(pea)
1435 {
1436 TCGv tmp;
1437
1438 tmp = gen_lea(env, s, insn, OS_LONG);
1439 if (IS_NULL_QREG(tmp)) {
1440 gen_addr_fault(s);
1441 return;
1442 }
1443 gen_push(s, tmp);
1444 }
1445
1446 DISAS_INSN(ext)
1447 {
1448 int op;
1449 TCGv reg;
1450 TCGv tmp;
1451
1452 reg = DREG(insn, 0);
1453 op = (insn >> 6) & 7;
1454 tmp = tcg_temp_new();
1455 if (op == 3)
1456 tcg_gen_ext16s_i32(tmp, reg);
1457 else
1458 tcg_gen_ext8s_i32(tmp, reg);
1459 if (op == 2)
1460 gen_partset_reg(OS_WORD, reg, tmp);
1461 else
1462 tcg_gen_mov_i32(reg, tmp);
1463 gen_logic_cc(s, tmp);
1464 }
1465
1466 DISAS_INSN(tst)
1467 {
1468 int opsize;
1469 TCGv tmp;
1470
1471 switch ((insn >> 6) & 3) {
1472 case 0: /* tst.b */
1473 opsize = OS_BYTE;
1474 break;
1475 case 1: /* tst.w */
1476 opsize = OS_WORD;
1477 break;
1478 case 2: /* tst.l */
1479 opsize = OS_LONG;
1480 break;
1481 default:
1482 abort();
1483 }
1484 SRC_EA(env, tmp, opsize, 1, NULL);
1485 gen_logic_cc(s, tmp);
1486 }
1487
1488 DISAS_INSN(pulse)
1489 {
1490 /* Implemented as a NOP. */
1491 }
1492
1493 DISAS_INSN(illegal)
1494 {
1495 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
1496 }
1497
1498 /* ??? This should be atomic. */
1499 DISAS_INSN(tas)
1500 {
1501 TCGv dest;
1502 TCGv src1;
1503 TCGv addr;
1504
1505 dest = tcg_temp_new();
1506 SRC_EA(env, src1, OS_BYTE, 1, &addr);
1507 gen_logic_cc(s, src1);
1508 tcg_gen_ori_i32(dest, src1, 0x80);
1509 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1510 }
1511
1512 DISAS_INSN(mull)
1513 {
1514 uint16_t ext;
1515 TCGv reg;
1516 TCGv src1;
1517 TCGv dest;
1518
1519 /* The upper 32 bits of the product are discarded, so
1520 muls.l and mulu.l are functionally equivalent. */
1521 ext = cpu_lduw_code(env, s->pc);
1522 s->pc += 2;
1523 if (ext & 0x87ff) {
1524 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1525 return;
1526 }
1527 reg = DREG(ext, 12);
1528 SRC_EA(env, src1, OS_LONG, 0, NULL);
1529 dest = tcg_temp_new();
1530 tcg_gen_mul_i32(dest, src1, reg);
1531 tcg_gen_mov_i32(reg, dest);
1532 /* Unlike m68k, coldfire always clears the overflow bit. */
1533 gen_logic_cc(s, dest);
1534 }
1535
1536 DISAS_INSN(link)
1537 {
1538 int16_t offset;
1539 TCGv reg;
1540 TCGv tmp;
1541
1542 offset = cpu_ldsw_code(env, s->pc);
1543 s->pc += 2;
1544 reg = AREG(insn, 0);
1545 tmp = tcg_temp_new();
1546 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1547 gen_store(s, OS_LONG, tmp, reg);
1548 if ((insn & 7) != 7)
1549 tcg_gen_mov_i32(reg, tmp);
1550 tcg_gen_addi_i32(QREG_SP, tmp, offset);
1551 }
1552
1553 DISAS_INSN(unlk)
1554 {
1555 TCGv src;
1556 TCGv reg;
1557 TCGv tmp;
1558
1559 src = tcg_temp_new();
1560 reg = AREG(insn, 0);
1561 tcg_gen_mov_i32(src, reg);
1562 tmp = gen_load(s, OS_LONG, src, 0);
1563 tcg_gen_mov_i32(reg, tmp);
1564 tcg_gen_addi_i32(QREG_SP, src, 4);
1565 }
1566
1567 DISAS_INSN(nop)
1568 {
1569 }
1570
1571 DISAS_INSN(rts)
1572 {
1573 TCGv tmp;
1574
1575 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
1576 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
1577 gen_jmp(s, tmp);
1578 }
1579
1580 DISAS_INSN(jump)
1581 {
1582 TCGv tmp;
1583
1584 /* Load the target address first to ensure correct exception
1585 behavior. */
1586 tmp = gen_lea(env, s, insn, OS_LONG);
1587 if (IS_NULL_QREG(tmp)) {
1588 gen_addr_fault(s);
1589 return;
1590 }
1591 if ((insn & 0x40) == 0) {
1592 /* jsr */
1593 gen_push(s, tcg_const_i32(s->pc));
1594 }
1595 gen_jmp(s, tmp);
1596 }
1597
1598 DISAS_INSN(addsubq)
1599 {
1600 TCGv src1;
1601 TCGv src2;
1602 TCGv dest;
1603 int val;
1604 TCGv addr;
1605
1606 SRC_EA(env, src1, OS_LONG, 0, &addr);
1607 val = (insn >> 9) & 7;
1608 if (val == 0)
1609 val = 8;
1610 dest = tcg_temp_new();
1611 tcg_gen_mov_i32(dest, src1);
1612 if ((insn & 0x38) == 0x08) {
1613 /* Don't update condition codes if the destination is an
1614 address register. */
1615 if (insn & 0x0100) {
1616 tcg_gen_subi_i32(dest, dest, val);
1617 } else {
1618 tcg_gen_addi_i32(dest, dest, val);
1619 }
1620 } else {
1621 src2 = tcg_const_i32(val);
1622 if (insn & 0x0100) {
1623 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1624 tcg_gen_subi_i32(dest, dest, val);
1625 s->cc_op = CC_OP_SUB;
1626 } else {
1627 tcg_gen_addi_i32(dest, dest, val);
1628 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1629 s->cc_op = CC_OP_ADD;
1630 }
1631 gen_update_cc_add(dest, src2);
1632 }
1633 DEST_EA(env, insn, OS_LONG, dest, &addr);
1634 }
1635
1636 DISAS_INSN(tpf)
1637 {
1638 switch (insn & 7) {
1639 case 2: /* One extension word. */
1640 s->pc += 2;
1641 break;
1642 case 3: /* Two extension words. */
1643 s->pc += 4;
1644 break;
1645 case 4: /* No extension words. */
1646 break;
1647 default:
1648 disas_undef(env, s, insn);
1649 }
1650 }
1651
1652 DISAS_INSN(branch)
1653 {
1654 int32_t offset;
1655 uint32_t base;
1656 int op;
1657 TCGLabel *l1;
1658
1659 base = s->pc;
1660 op = (insn >> 8) & 0xf;
1661 offset = (int8_t)insn;
1662 if (offset == 0) {
1663 offset = cpu_ldsw_code(env, s->pc);
1664 s->pc += 2;
1665 } else if (offset == -1) {
1666 offset = read_im32(env, s);
1667 }
1668 if (op == 1) {
1669 /* bsr */
1670 gen_push(s, tcg_const_i32(s->pc));
1671 }
1672 gen_flush_cc_op(s);
1673 if (op > 1) {
1674 /* Bcc */
1675 l1 = gen_new_label();
1676 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
1677 gen_jmp_tb(s, 1, base + offset);
1678 gen_set_label(l1);
1679 gen_jmp_tb(s, 0, s->pc);
1680 } else {
1681 /* Unconditional branch. */
1682 gen_jmp_tb(s, 0, base + offset);
1683 }
1684 }
1685
1686 DISAS_INSN(moveq)
1687 {
1688 uint32_t val;
1689
1690 val = (int8_t)insn;
1691 tcg_gen_movi_i32(DREG(insn, 9), val);
1692 gen_logic_cc(s, tcg_const_i32(val));
1693 }
1694
1695 DISAS_INSN(mvzs)
1696 {
1697 int opsize;
1698 TCGv src;
1699 TCGv reg;
1700
1701 if (insn & 0x40)
1702 opsize = OS_WORD;
1703 else
1704 opsize = OS_BYTE;
1705 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
1706 reg = DREG(insn, 9);
1707 tcg_gen_mov_i32(reg, src);
1708 gen_logic_cc(s, src);
1709 }
1710
1711 DISAS_INSN(or)
1712 {
1713 TCGv reg;
1714 TCGv dest;
1715 TCGv src;
1716 TCGv addr;
1717
1718 reg = DREG(insn, 9);
1719 dest = tcg_temp_new();
1720 if (insn & 0x100) {
1721 SRC_EA(env, src, OS_LONG, 0, &addr);
1722 tcg_gen_or_i32(dest, src, reg);
1723 DEST_EA(env, insn, OS_LONG, dest, &addr);
1724 } else {
1725 SRC_EA(env, src, OS_LONG, 0, NULL);
1726 tcg_gen_or_i32(dest, src, reg);
1727 tcg_gen_mov_i32(reg, dest);
1728 }
1729 gen_logic_cc(s, dest);
1730 }
1731
1732 DISAS_INSN(suba)
1733 {
1734 TCGv src;
1735 TCGv reg;
1736
1737 SRC_EA(env, src, OS_LONG, 0, NULL);
1738 reg = AREG(insn, 9);
1739 tcg_gen_sub_i32(reg, reg, src);
1740 }
1741
1742 DISAS_INSN(subx)
1743 {
1744 TCGv reg;
1745 TCGv src;
1746
1747 gen_flush_flags(s);
1748 reg = DREG(insn, 9);
1749 src = DREG(insn, 0);
1750 gen_helper_subx_cc(reg, cpu_env, reg, src);
1751 }
1752
1753 DISAS_INSN(mov3q)
1754 {
1755 TCGv src;
1756 int val;
1757
1758 val = (insn >> 9) & 7;
1759 if (val == 0)
1760 val = -1;
1761 src = tcg_const_i32(val);
1762 gen_logic_cc(s, src);
1763 DEST_EA(env, insn, OS_LONG, src, NULL);
1764 }
1765
1766 DISAS_INSN(cmp)
1767 {
1768 int op;
1769 TCGv src;
1770 TCGv reg;
1771 TCGv dest;
1772 int opsize;
1773
1774 op = (insn >> 6) & 3;
1775 switch (op) {
1776 case 0: /* cmp.b */
1777 opsize = OS_BYTE;
1778 s->cc_op = CC_OP_CMPB;
1779 break;
1780 case 1: /* cmp.w */
1781 opsize = OS_WORD;
1782 s->cc_op = CC_OP_CMPW;
1783 break;
1784 case 2: /* cmp.l */
1785 opsize = OS_LONG;
1786 s->cc_op = CC_OP_SUB;
1787 break;
1788 default:
1789 abort();
1790 }
1791 SRC_EA(env, src, opsize, 1, NULL);
1792 reg = DREG(insn, 9);
1793 dest = tcg_temp_new();
1794 tcg_gen_sub_i32(dest, reg, src);
1795 gen_update_cc_add(dest, src);
1796 }
1797
1798 DISAS_INSN(cmpa)
1799 {
1800 int opsize;
1801 TCGv src;
1802 TCGv reg;
1803 TCGv dest;
1804
1805 if (insn & 0x100) {
1806 opsize = OS_LONG;
1807 } else {
1808 opsize = OS_WORD;
1809 }
1810 SRC_EA(env, src, opsize, 1, NULL);
1811 reg = AREG(insn, 9);
1812 dest = tcg_temp_new();
1813 tcg_gen_sub_i32(dest, reg, src);
1814 gen_update_cc_add(dest, src);
1815 s->cc_op = CC_OP_SUB;
1816 }
1817
1818 DISAS_INSN(eor)
1819 {
1820 TCGv src;
1821 TCGv reg;
1822 TCGv dest;
1823 TCGv addr;
1824
1825 SRC_EA(env, src, OS_LONG, 0, &addr);
1826 reg = DREG(insn, 9);
1827 dest = tcg_temp_new();
1828 tcg_gen_xor_i32(dest, src, reg);
1829 gen_logic_cc(s, dest);
1830 DEST_EA(env, insn, OS_LONG, dest, &addr);
1831 }
1832
1833 DISAS_INSN(and)
1834 {
1835 TCGv src;
1836 TCGv reg;
1837 TCGv dest;
1838 TCGv addr;
1839
1840 reg = DREG(insn, 9);
1841 dest = tcg_temp_new();
1842 if (insn & 0x100) {
1843 SRC_EA(env, src, OS_LONG, 0, &addr);
1844 tcg_gen_and_i32(dest, src, reg);
1845 DEST_EA(env, insn, OS_LONG, dest, &addr);
1846 } else {
1847 SRC_EA(env, src, OS_LONG, 0, NULL);
1848 tcg_gen_and_i32(dest, src, reg);
1849 tcg_gen_mov_i32(reg, dest);
1850 }
1851 gen_logic_cc(s, dest);
1852 }
1853
1854 DISAS_INSN(adda)
1855 {
1856 TCGv src;
1857 TCGv reg;
1858
1859 SRC_EA(env, src, OS_LONG, 0, NULL);
1860 reg = AREG(insn, 9);
1861 tcg_gen_add_i32(reg, reg, src);
1862 }
1863
1864 DISAS_INSN(addx)
1865 {
1866 TCGv reg;
1867 TCGv src;
1868
1869 gen_flush_flags(s);
1870 reg = DREG(insn, 9);
1871 src = DREG(insn, 0);
1872 gen_helper_addx_cc(reg, cpu_env, reg, src);
1873 s->cc_op = CC_OP_FLAGS;
1874 }
1875
1876 /* TODO: This could be implemented without helper functions. */
1877 DISAS_INSN(shift_im)
1878 {
1879 TCGv reg;
1880 int tmp;
1881 TCGv shift;
1882
1883 reg = DREG(insn, 0);
1884 tmp = (insn >> 9) & 7;
1885 if (tmp == 0)
1886 tmp = 8;
1887 shift = tcg_const_i32(tmp);
1888 /* No need to flush flags becuse we know we will set C flag. */
1889 if (insn & 0x100) {
1890 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1891 } else {
1892 if (insn & 8) {
1893 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1894 } else {
1895 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1896 }
1897 }
1898 s->cc_op = CC_OP_SHIFT;
1899 }
1900
1901 DISAS_INSN(shift_reg)
1902 {
1903 TCGv reg;
1904 TCGv shift;
1905
1906 reg = DREG(insn, 0);
1907 shift = DREG(insn, 9);
1908 /* Shift by zero leaves C flag unmodified. */
1909 gen_flush_flags(s);
1910 if (insn & 0x100) {
1911 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1912 } else {
1913 if (insn & 8) {
1914 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1915 } else {
1916 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1917 }
1918 }
1919 s->cc_op = CC_OP_SHIFT;
1920 }
1921
1922 DISAS_INSN(ff1)
1923 {
1924 TCGv reg;
1925 reg = DREG(insn, 0);
1926 gen_logic_cc(s, reg);
1927 gen_helper_ff1(reg, reg);
1928 }
1929
1930 static TCGv gen_get_sr(DisasContext *s)
1931 {
1932 TCGv ccr;
1933 TCGv sr;
1934
1935 ccr = gen_get_ccr(s);
1936 sr = tcg_temp_new();
1937 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
1938 tcg_gen_or_i32(sr, sr, ccr);
1939 return sr;
1940 }
1941
1942 DISAS_INSN(strldsr)
1943 {
1944 uint16_t ext;
1945 uint32_t addr;
1946
1947 addr = s->pc - 2;
1948 ext = cpu_lduw_code(env, s->pc);
1949 s->pc += 2;
1950 if (ext != 0x46FC) {
1951 gen_exception(s, addr, EXCP_UNSUPPORTED);
1952 return;
1953 }
1954 ext = cpu_lduw_code(env, s->pc);
1955 s->pc += 2;
1956 if (IS_USER(s) || (ext & SR_S) == 0) {
1957 gen_exception(s, addr, EXCP_PRIVILEGE);
1958 return;
1959 }
1960 gen_push(s, gen_get_sr(s));
1961 gen_set_sr_im(s, ext, 0);
1962 }
1963
1964 DISAS_INSN(move_from_sr)
1965 {
1966 TCGv reg;
1967 TCGv sr;
1968
1969 if (IS_USER(s)) {
1970 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1971 return;
1972 }
1973 sr = gen_get_sr(s);
1974 reg = DREG(insn, 0);
1975 gen_partset_reg(OS_WORD, reg, sr);
1976 }
1977
1978 DISAS_INSN(move_to_sr)
1979 {
1980 if (IS_USER(s)) {
1981 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1982 return;
1983 }
1984 gen_set_sr(env, s, insn, 0);
1985 gen_lookup_tb(s);
1986 }
1987
1988 DISAS_INSN(move_from_usp)
1989 {
1990 if (IS_USER(s)) {
1991 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1992 return;
1993 }
1994 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
1995 offsetof(CPUM68KState, sp[M68K_USP]));
1996 }
1997
1998 DISAS_INSN(move_to_usp)
1999 {
2000 if (IS_USER(s)) {
2001 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2002 return;
2003 }
2004 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
2005 offsetof(CPUM68KState, sp[M68K_USP]));
2006 }
2007
2008 DISAS_INSN(halt)
2009 {
2010 gen_exception(s, s->pc, EXCP_HALT_INSN);
2011 }
2012
2013 DISAS_INSN(stop)
2014 {
2015 uint16_t ext;
2016
2017 if (IS_USER(s)) {
2018 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2019 return;
2020 }
2021
2022 ext = cpu_lduw_code(env, s->pc);
2023 s->pc += 2;
2024
2025 gen_set_sr_im(s, ext, 0);
2026 tcg_gen_movi_i32(cpu_halted, 1);
2027 gen_exception(s, s->pc, EXCP_HLT);
2028 }
2029
2030 DISAS_INSN(rte)
2031 {
2032 if (IS_USER(s)) {
2033 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2034 return;
2035 }
2036 gen_exception(s, s->pc - 2, EXCP_RTE);
2037 }
2038
2039 DISAS_INSN(movec)
2040 {
2041 uint16_t ext;
2042 TCGv reg;
2043
2044 if (IS_USER(s)) {
2045 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2046 return;
2047 }
2048
2049 ext = cpu_lduw_code(env, s->pc);
2050 s->pc += 2;
2051
2052 if (ext & 0x8000) {
2053 reg = AREG(ext, 12);
2054 } else {
2055 reg = DREG(ext, 12);
2056 }
2057 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
2058 gen_lookup_tb(s);
2059 }
2060
2061 DISAS_INSN(intouch)
2062 {
2063 if (IS_USER(s)) {
2064 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2065 return;
2066 }
2067 /* ICache fetch. Implement as no-op. */
2068 }
2069
2070 DISAS_INSN(cpushl)
2071 {
2072 if (IS_USER(s)) {
2073 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2074 return;
2075 }
2076 /* Cache push/invalidate. Implement as no-op. */
2077 }
2078
2079 DISAS_INSN(wddata)
2080 {
2081 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2082 }
2083
2084 DISAS_INSN(wdebug)
2085 {
2086 M68kCPU *cpu = m68k_env_get_cpu(env);
2087
2088 if (IS_USER(s)) {
2089 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2090 return;
2091 }
2092 /* TODO: Implement wdebug. */
2093 cpu_abort(CPU(cpu), "WDEBUG not implemented");
2094 }
2095
2096 DISAS_INSN(trap)
2097 {
2098 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
2099 }
2100
2101 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2102 immediately before the next FP instruction is executed. */
2103 DISAS_INSN(fpu)
2104 {
2105 uint16_t ext;
2106 int32_t offset;
2107 int opmode;
2108 TCGv_i64 src;
2109 TCGv_i64 dest;
2110 TCGv_i64 res;
2111 TCGv tmp32;
2112 int round;
2113 int set_dest;
2114 int opsize;
2115
2116 ext = cpu_lduw_code(env, s->pc);
2117 s->pc += 2;
2118 opmode = ext & 0x7f;
2119 switch ((ext >> 13) & 7) {
2120 case 0: case 2:
2121 break;
2122 case 1:
2123 goto undef;
2124 case 3: /* fmove out */
2125 src = FREG(ext, 7);
2126 tmp32 = tcg_temp_new_i32();
2127 /* fmove */
2128 /* ??? TODO: Proper behavior on overflow. */
2129 switch ((ext >> 10) & 7) {
2130 case 0:
2131 opsize = OS_LONG;
2132 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2133 break;
2134 case 1:
2135 opsize = OS_SINGLE;
2136 gen_helper_f64_to_f32(tmp32, cpu_env, src);
2137 break;
2138 case 4:
2139 opsize = OS_WORD;
2140 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2141 break;
2142 case 5: /* OS_DOUBLE */
2143 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2144 switch ((insn >> 3) & 7) {
2145 case 2:
2146 case 3:
2147 break;
2148 case 4:
2149 tcg_gen_addi_i32(tmp32, tmp32, -8);
2150 break;
2151 case 5:
2152 offset = cpu_ldsw_code(env, s->pc);
2153 s->pc += 2;
2154 tcg_gen_addi_i32(tmp32, tmp32, offset);
2155 break;
2156 default:
2157 goto undef;
2158 }
2159 gen_store64(s, tmp32, src);
2160 switch ((insn >> 3) & 7) {
2161 case 3:
2162 tcg_gen_addi_i32(tmp32, tmp32, 8);
2163 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2164 break;
2165 case 4:
2166 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2167 break;
2168 }
2169 tcg_temp_free_i32(tmp32);
2170 return;
2171 case 6:
2172 opsize = OS_BYTE;
2173 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2174 break;
2175 default:
2176 goto undef;
2177 }
2178 DEST_EA(env, insn, opsize, tmp32, NULL);
2179 tcg_temp_free_i32(tmp32);
2180 return;
2181 case 4: /* fmove to control register. */
2182 switch ((ext >> 10) & 7) {
2183 case 4: /* FPCR */
2184 /* Not implemented. Ignore writes. */
2185 break;
2186 case 1: /* FPIAR */
2187 case 2: /* FPSR */
2188 default:
2189 cpu_abort(NULL, "Unimplemented: fmove to control %d",
2190 (ext >> 10) & 7);
2191 }
2192 break;
2193 case 5: /* fmove from control register. */
2194 switch ((ext >> 10) & 7) {
2195 case 4: /* FPCR */
2196 /* Not implemented. Always return zero. */
2197 tmp32 = tcg_const_i32(0);
2198 break;
2199 case 1: /* FPIAR */
2200 case 2: /* FPSR */
2201 default:
2202 cpu_abort(NULL, "Unimplemented: fmove from control %d",
2203 (ext >> 10) & 7);
2204 goto undef;
2205 }
2206 DEST_EA(env, insn, OS_LONG, tmp32, NULL);
2207 break;
2208 case 6: /* fmovem */
2209 case 7:
2210 {
2211 TCGv addr;
2212 uint16_t mask;
2213 int i;
2214 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
2215 goto undef;
2216 tmp32 = gen_lea(env, s, insn, OS_LONG);
2217 if (IS_NULL_QREG(tmp32)) {
2218 gen_addr_fault(s);
2219 return;
2220 }
2221 addr = tcg_temp_new_i32();
2222 tcg_gen_mov_i32(addr, tmp32);
2223 mask = 0x80;
2224 for (i = 0; i < 8; i++) {
2225 if (ext & mask) {
2226 dest = FREG(i, 0);
2227 if (ext & (1 << 13)) {
2228 /* store */
2229 tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
2230 } else {
2231 /* load */
2232 tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
2233 }
2234 if (ext & (mask - 1))
2235 tcg_gen_addi_i32(addr, addr, 8);
2236 }
2237 mask >>= 1;
2238 }
2239 tcg_temp_free_i32(addr);
2240 }
2241 return;
2242 }
2243 if (ext & (1 << 14)) {
2244 /* Source effective address. */
2245 switch ((ext >> 10) & 7) {
2246 case 0: opsize = OS_LONG; break;
2247 case 1: opsize = OS_SINGLE; break;
2248 case 4: opsize = OS_WORD; break;
2249 case 5: opsize = OS_DOUBLE; break;
2250 case 6: opsize = OS_BYTE; break;
2251 default:
2252 goto undef;
2253 }
2254 if (opsize == OS_DOUBLE) {
2255 tmp32 = tcg_temp_new_i32();
2256 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2257 switch ((insn >> 3) & 7) {
2258 case 2:
2259 case 3:
2260 break;
2261 case 4:
2262 tcg_gen_addi_i32(tmp32, tmp32, -8);
2263 break;
2264 case 5:
2265 offset = cpu_ldsw_code(env, s->pc);
2266 s->pc += 2;
2267 tcg_gen_addi_i32(tmp32, tmp32, offset);
2268 break;
2269 case 7:
2270 offset = cpu_ldsw_code(env, s->pc);
2271 offset += s->pc - 2;
2272 s->pc += 2;
2273 tcg_gen_addi_i32(tmp32, tmp32, offset);
2274 break;
2275 default:
2276 goto undef;
2277 }
2278 src = gen_load64(s, tmp32);
2279 switch ((insn >> 3) & 7) {
2280 case 3:
2281 tcg_gen_addi_i32(tmp32, tmp32, 8);
2282 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2283 break;
2284 case 4:
2285 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2286 break;
2287 }
2288 tcg_temp_free_i32(tmp32);
2289 } else {
2290 SRC_EA(env, tmp32, opsize, 1, NULL);
2291 src = tcg_temp_new_i64();
2292 switch (opsize) {
2293 case OS_LONG:
2294 case OS_WORD:
2295 case OS_BYTE:
2296 gen_helper_i32_to_f64(src, cpu_env, tmp32);
2297 break;
2298 case OS_SINGLE:
2299 gen_helper_f32_to_f64(src, cpu_env, tmp32);
2300 break;
2301 }
2302 }
2303 } else {
2304 /* Source register. */
2305 src = FREG(ext, 10);
2306 }
2307 dest = FREG(ext, 7);
2308 res = tcg_temp_new_i64();
2309 if (opmode != 0x3a)
2310 tcg_gen_mov_f64(res, dest);
2311 round = 1;
2312 set_dest = 1;
2313 switch (opmode) {
2314 case 0: case 0x40: case 0x44: /* fmove */
2315 tcg_gen_mov_f64(res, src);
2316 break;
2317 case 1: /* fint */
2318 gen_helper_iround_f64(res, cpu_env, src);
2319 round = 0;
2320 break;
2321 case 3: /* fintrz */
2322 gen_helper_itrunc_f64(res, cpu_env, src);
2323 round = 0;
2324 break;
2325 case 4: case 0x41: case 0x45: /* fsqrt */
2326 gen_helper_sqrt_f64(res, cpu_env, src);
2327 break;
2328 case 0x18: case 0x58: case 0x5c: /* fabs */
2329 gen_helper_abs_f64(res, src);
2330 break;
2331 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2332 gen_helper_chs_f64(res, src);
2333 break;
2334 case 0x20: case 0x60: case 0x64: /* fdiv */
2335 gen_helper_div_f64(res, cpu_env, res, src);
2336 break;
2337 case 0x22: case 0x62: case 0x66: /* fadd */
2338 gen_helper_add_f64(res, cpu_env, res, src);
2339 break;
2340 case 0x23: case 0x63: case 0x67: /* fmul */
2341 gen_helper_mul_f64(res, cpu_env, res, src);
2342 break;
2343 case 0x28: case 0x68: case 0x6c: /* fsub */
2344 gen_helper_sub_f64(res, cpu_env, res, src);
2345 break;
2346 case 0x38: /* fcmp */
2347 gen_helper_sub_cmp_f64(res, cpu_env, res, src);
2348 set_dest = 0;
2349 round = 0;
2350 break;
2351 case 0x3a: /* ftst */
2352 tcg_gen_mov_f64(res, src);
2353 set_dest = 0;
2354 round = 0;
2355 break;
2356 default:
2357 goto undef;
2358 }
2359 if (ext & (1 << 14)) {
2360 tcg_temp_free_i64(src);
2361 }
2362 if (round) {
2363 if (opmode & 0x40) {
2364 if ((opmode & 0x4) != 0)
2365 round = 0;
2366 } else if ((s->fpcr & M68K_FPCR_PREC) == 0) {
2367 round = 0;
2368 }
2369 }
2370 if (round) {
2371 TCGv tmp = tcg_temp_new_i32();
2372 gen_helper_f64_to_f32(tmp, cpu_env, res);
2373 gen_helper_f32_to_f64(res, cpu_env, tmp);
2374 tcg_temp_free_i32(tmp);
2375 }
2376 tcg_gen_mov_f64(QREG_FP_RESULT, res);
2377 if (set_dest) {
2378 tcg_gen_mov_f64(dest, res);
2379 }
2380 tcg_temp_free_i64(res);
2381 return;
2382 undef:
2383 /* FIXME: Is this right for offset addressing modes? */
2384 s->pc -= 2;
2385 disas_undef_fpu(env, s, insn);
2386 }
2387
2388 DISAS_INSN(fbcc)
2389 {
2390 uint32_t offset;
2391 uint32_t addr;
2392 TCGv flag;
2393 TCGLabel *l1;
2394
2395 addr = s->pc;
2396 offset = cpu_ldsw_code(env, s->pc);
2397 s->pc += 2;
2398 if (insn & (1 << 6)) {
2399 offset = (offset << 16) | cpu_lduw_code(env, s->pc);
2400 s->pc += 2;
2401 }
2402
2403 l1 = gen_new_label();
2404 /* TODO: Raise BSUN exception. */
2405 flag = tcg_temp_new();
2406 gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
2407 /* Jump to l1 if condition is true. */
2408 switch (insn & 0xf) {
2409 case 0: /* f */
2410 break;
2411 case 1: /* eq (=0) */
2412 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2413 break;
2414 case 2: /* ogt (=1) */
2415 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
2416 break;
2417 case 3: /* oge (=0 or =1) */
2418 tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
2419 break;
2420 case 4: /* olt (=-1) */
2421 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
2422 break;
2423 case 5: /* ole (=-1 or =0) */
2424 tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
2425 break;
2426 case 6: /* ogl (=-1 or =1) */
2427 tcg_gen_andi_i32(flag, flag, 1);
2428 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2429 break;
2430 case 7: /* or (=2) */
2431 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
2432 break;
2433 case 8: /* un (<2) */
2434 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
2435 break;
2436 case 9: /* ueq (=0 or =2) */
2437 tcg_gen_andi_i32(flag, flag, 1);
2438 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2439 break;
2440 case 10: /* ugt (>0) */
2441 tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
2442 break;
2443 case 11: /* uge (>=0) */
2444 tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
2445 break;
2446 case 12: /* ult (=-1 or =2) */
2447 tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
2448 break;
2449 case 13: /* ule (!=1) */
2450 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
2451 break;
2452 case 14: /* ne (!=0) */
2453 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2454 break;
2455 case 15: /* t */
2456 tcg_gen_br(l1);
2457 break;
2458 }
2459 gen_jmp_tb(s, 0, s->pc);
2460 gen_set_label(l1);
2461 gen_jmp_tb(s, 1, addr + offset);
2462 }
2463
2464 DISAS_INSN(frestore)
2465 {
2466 M68kCPU *cpu = m68k_env_get_cpu(env);
2467
2468 /* TODO: Implement frestore. */
2469 cpu_abort(CPU(cpu), "FRESTORE not implemented");
2470 }
2471
2472 DISAS_INSN(fsave)
2473 {
2474 M68kCPU *cpu = m68k_env_get_cpu(env);
2475
2476 /* TODO: Implement fsave. */
2477 cpu_abort(CPU(cpu), "FSAVE not implemented");
2478 }
2479
2480 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
2481 {
2482 TCGv tmp = tcg_temp_new();
2483 if (s->env->macsr & MACSR_FI) {
2484 if (upper)
2485 tcg_gen_andi_i32(tmp, val, 0xffff0000);
2486 else
2487 tcg_gen_shli_i32(tmp, val, 16);
2488 } else if (s->env->macsr & MACSR_SU) {
2489 if (upper)
2490 tcg_gen_sari_i32(tmp, val, 16);
2491 else
2492 tcg_gen_ext16s_i32(tmp, val);
2493 } else {
2494 if (upper)
2495 tcg_gen_shri_i32(tmp, val, 16);
2496 else
2497 tcg_gen_ext16u_i32(tmp, val);
2498 }
2499 return tmp;
2500 }
2501
2502 static void gen_mac_clear_flags(void)
2503 {
2504 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
2505 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
2506 }
2507
2508 DISAS_INSN(mac)
2509 {
2510 TCGv rx;
2511 TCGv ry;
2512 uint16_t ext;
2513 int acc;
2514 TCGv tmp;
2515 TCGv addr;
2516 TCGv loadval;
2517 int dual;
2518 TCGv saved_flags;
2519
2520 if (!s->done_mac) {
2521 s->mactmp = tcg_temp_new_i64();
2522 s->done_mac = 1;
2523 }
2524
2525 ext = cpu_lduw_code(env, s->pc);
2526 s->pc += 2;
2527
2528 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
2529 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
2530 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
2531 disas_undef(env, s, insn);
2532 return;
2533 }
2534 if (insn & 0x30) {
2535 /* MAC with load. */
2536 tmp = gen_lea(env, s, insn, OS_LONG);
2537 addr = tcg_temp_new();
2538 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
2539 /* Load the value now to ensure correct exception behavior.
2540 Perform writeback after reading the MAC inputs. */
2541 loadval = gen_load(s, OS_LONG, addr, 0);
2542
2543 acc ^= 1;
2544 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
2545 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
2546 } else {
2547 loadval = addr = NULL_QREG;
2548 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2549 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2550 }
2551
2552 gen_mac_clear_flags();
2553 #if 0
2554 l1 = -1;
2555 /* Disabled because conditional branches clobber temporary vars. */
2556 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
2557 /* Skip the multiply if we know we will ignore it. */
2558 l1 = gen_new_label();
2559 tmp = tcg_temp_new();
2560 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
2561 gen_op_jmp_nz32(tmp, l1);
2562 }
2563 #endif
2564
2565 if ((ext & 0x0800) == 0) {
2566 /* Word. */
2567 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
2568 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
2569 }
2570 if (s->env->macsr & MACSR_FI) {
2571 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
2572 } else {
2573 if (s->env->macsr & MACSR_SU)
2574 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
2575 else
2576 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
2577 switch ((ext >> 9) & 3) {
2578 case 1:
2579 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
2580 break;
2581 case 3:
2582 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
2583 break;
2584 }
2585 }
2586
2587 if (dual) {
2588 /* Save the overflow flag from the multiply. */
2589 saved_flags = tcg_temp_new();
2590 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
2591 } else {
2592 saved_flags = NULL_QREG;
2593 }
2594
2595 #if 0
2596 /* Disabled because conditional branches clobber temporary vars. */
2597 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
2598 /* Skip the accumulate if the value is already saturated. */
2599 l1 = gen_new_label();
2600 tmp = tcg_temp_new();
2601 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2602 gen_op_jmp_nz32(tmp, l1);
2603 }
2604 #endif
2605
2606 if (insn & 0x100)
2607 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2608 else
2609 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2610
2611 if (s->env->macsr & MACSR_FI)
2612 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2613 else if (s->env->macsr & MACSR_SU)
2614 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2615 else
2616 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2617
2618 #if 0
2619 /* Disabled because conditional branches clobber temporary vars. */
2620 if (l1 != -1)
2621 gen_set_label(l1);
2622 #endif
2623
2624 if (dual) {
2625 /* Dual accumulate variant. */
2626 acc = (ext >> 2) & 3;
2627 /* Restore the overflow flag from the multiplier. */
2628 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
2629 #if 0
2630 /* Disabled because conditional branches clobber temporary vars. */
2631 if ((s->env->macsr & MACSR_OMC) != 0) {
2632 /* Skip the accumulate if the value is already saturated. */
2633 l1 = gen_new_label();
2634 tmp = tcg_temp_new();
2635 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2636 gen_op_jmp_nz32(tmp, l1);
2637 }
2638 #endif
2639 if (ext & 2)
2640 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2641 else
2642 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2643 if (s->env->macsr & MACSR_FI)
2644 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2645 else if (s->env->macsr & MACSR_SU)
2646 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2647 else
2648 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2649 #if 0
2650 /* Disabled because conditional branches clobber temporary vars. */
2651 if (l1 != -1)
2652 gen_set_label(l1);
2653 #endif
2654 }
2655 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
2656
2657 if (insn & 0x30) {
2658 TCGv rw;
2659 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2660 tcg_gen_mov_i32(rw, loadval);
2661 /* FIXME: Should address writeback happen with the masked or
2662 unmasked value? */
2663 switch ((insn >> 3) & 7) {
2664 case 3: /* Post-increment. */
2665 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
2666 break;
2667 case 4: /* Pre-decrement. */
2668 tcg_gen_mov_i32(AREG(insn, 0), addr);
2669 }
2670 }
2671 }
2672
2673 DISAS_INSN(from_mac)
2674 {
2675 TCGv rx;
2676 TCGv_i64 acc;
2677 int accnum;
2678
2679 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2680 accnum = (insn >> 9) & 3;
2681 acc = MACREG(accnum);
2682 if (s->env->macsr & MACSR_FI) {
2683 gen_helper_get_macf(rx, cpu_env, acc);
2684 } else if ((s->env->macsr & MACSR_OMC) == 0) {
2685 tcg_gen_extrl_i64_i32(rx, acc);
2686 } else if (s->env->macsr & MACSR_SU) {
2687 gen_helper_get_macs(rx, acc);
2688 } else {
2689 gen_helper_get_macu(rx, acc);
2690 }
2691 if (insn & 0x40) {
2692 tcg_gen_movi_i64(acc, 0);
2693 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2694 }
2695 }
2696
2697 DISAS_INSN(move_mac)
2698 {
2699 /* FIXME: This can be done without a helper. */
2700 int src;
2701 TCGv dest;
2702 src = insn & 3;
2703 dest = tcg_const_i32((insn >> 9) & 3);
2704 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
2705 gen_mac_clear_flags();
2706 gen_helper_mac_set_flags(cpu_env, dest);
2707 }
2708
2709 DISAS_INSN(from_macsr)
2710 {
2711 TCGv reg;
2712
2713 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2714 tcg_gen_mov_i32(reg, QREG_MACSR);
2715 }
2716
2717 DISAS_INSN(from_mask)
2718 {
2719 TCGv reg;
2720 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2721 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
2722 }
2723
2724 DISAS_INSN(from_mext)
2725 {
2726 TCGv reg;
2727 TCGv acc;
2728 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2729 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2730 if (s->env->macsr & MACSR_FI)
2731 gen_helper_get_mac_extf(reg, cpu_env, acc);
2732 else
2733 gen_helper_get_mac_exti(reg, cpu_env, acc);
2734 }
2735
2736 DISAS_INSN(macsr_to_ccr)
2737 {
2738 tcg_gen_movi_i32(QREG_CC_X, 0);
2739 tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf);
2740 s->cc_op = CC_OP_FLAGS;
2741 }
2742
2743 DISAS_INSN(to_mac)
2744 {
2745 TCGv_i64 acc;
2746 TCGv val;
2747 int accnum;
2748 accnum = (insn >> 9) & 3;
2749 acc = MACREG(accnum);
2750 SRC_EA(env, val, OS_LONG, 0, NULL);
2751 if (s->env->macsr & MACSR_FI) {
2752 tcg_gen_ext_i32_i64(acc, val);
2753 tcg_gen_shli_i64(acc, acc, 8);
2754 } else if (s->env->macsr & MACSR_SU) {
2755 tcg_gen_ext_i32_i64(acc, val);
2756 } else {
2757 tcg_gen_extu_i32_i64(acc, val);
2758 }
2759 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2760 gen_mac_clear_flags();
2761 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
2762 }
2763
2764 DISAS_INSN(to_macsr)
2765 {
2766 TCGv val;
2767 SRC_EA(env, val, OS_LONG, 0, NULL);
2768 gen_helper_set_macsr(cpu_env, val);
2769 gen_lookup_tb(s);
2770 }
2771
2772 DISAS_INSN(to_mask)
2773 {
2774 TCGv val;
2775 SRC_EA(env, val, OS_LONG, 0, NULL);
2776 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
2777 }
2778
2779 DISAS_INSN(to_mext)
2780 {
2781 TCGv val;
2782 TCGv acc;
2783 SRC_EA(env, val, OS_LONG, 0, NULL);
2784 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2785 if (s->env->macsr & MACSR_FI)
2786 gen_helper_set_mac_extf(cpu_env, val, acc);
2787 else if (s->env->macsr & MACSR_SU)
2788 gen_helper_set_mac_exts(cpu_env, val, acc);
2789 else
2790 gen_helper_set_mac_extu(cpu_env, val, acc);
2791 }
2792
2793 static disas_proc opcode_table[65536];
2794
2795 static void
2796 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
2797 {
2798 int i;
2799 int from;
2800 int to;
2801
2802 /* Sanity check. All set bits must be included in the mask. */
2803 if (opcode & ~mask) {
2804 fprintf(stderr,
2805 "qemu internal error: bogus opcode definition %04x/%04x\n",
2806 opcode, mask);
2807 abort();
2808 }
2809 /* This could probably be cleverer. For now just optimize the case where
2810 the top bits are known. */
2811 /* Find the first zero bit in the mask. */
2812 i = 0x8000;
2813 while ((i & mask) != 0)
2814 i >>= 1;
2815 /* Iterate over all combinations of this and lower bits. */
2816 if (i == 0)
2817 i = 1;
2818 else
2819 i <<= 1;
2820 from = opcode & ~(i - 1);
2821 to = from + i;
2822 for (i = from; i < to; i++) {
2823 if ((i & mask) == opcode)
2824 opcode_table[i] = proc;
2825 }
2826 }
2827
2828 /* Register m68k opcode handlers. Order is important.
2829 Later insn override earlier ones. */
2830 void register_m68k_insns (CPUM68KState *env)
2831 {
2832 #define INSN(name, opcode, mask, feature) do { \
2833 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2834 register_opcode(disas_##name, 0x##opcode, 0x##mask); \
2835 } while(0)
2836 INSN(undef, 0000, 0000, CF_ISA_A);
2837 INSN(arith_im, 0080, fff8, CF_ISA_A);
2838 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
2839 INSN(bitop_reg, 0100, f1c0, CF_ISA_A);
2840 INSN(bitop_reg, 0140, f1c0, CF_ISA_A);
2841 INSN(bitop_reg, 0180, f1c0, CF_ISA_A);
2842 INSN(bitop_reg, 01c0, f1c0, CF_ISA_A);
2843 INSN(arith_im, 0280, fff8, CF_ISA_A);
2844 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
2845 INSN(arith_im, 0480, fff8, CF_ISA_A);
2846 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
2847 INSN(arith_im, 0680, fff8, CF_ISA_A);
2848 INSN(bitop_im, 0800, ffc0, CF_ISA_A);
2849 INSN(bitop_im, 0840, ffc0, CF_ISA_A);
2850 INSN(bitop_im, 0880, ffc0, CF_ISA_A);
2851 INSN(bitop_im, 08c0, ffc0, CF_ISA_A);
2852 INSN(arith_im, 0a80, fff8, CF_ISA_A);
2853 INSN(arith_im, 0c00, ff38, CF_ISA_A);
2854 INSN(move, 1000, f000, CF_ISA_A);
2855 INSN(move, 2000, f000, CF_ISA_A);
2856 INSN(move, 3000, f000, CF_ISA_A);
2857 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
2858 INSN(negx, 4080, fff8, CF_ISA_A);
2859 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
2860 INSN(lea, 41c0, f1c0, CF_ISA_A);
2861 INSN(clr, 4200, ff00, CF_ISA_A);
2862 INSN(undef, 42c0, ffc0, CF_ISA_A);
2863 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
2864 INSN(neg, 4480, fff8, CF_ISA_A);
2865 INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A);
2866 INSN(not, 4680, fff8, CF_ISA_A);
2867 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
2868 INSN(pea, 4840, ffc0, CF_ISA_A);
2869 INSN(swap, 4840, fff8, CF_ISA_A);
2870 INSN(movem, 48c0, fbc0, CF_ISA_A);
2871 INSN(ext, 4880, fff8, CF_ISA_A);
2872 INSN(ext, 48c0, fff8, CF_ISA_A);
2873 INSN(ext, 49c0, fff8, CF_ISA_A);
2874 INSN(tst, 4a00, ff00, CF_ISA_A);
2875 INSN(tas, 4ac0, ffc0, CF_ISA_B);
2876 INSN(halt, 4ac8, ffff, CF_ISA_A);
2877 INSN(pulse, 4acc, ffff, CF_ISA_A);
2878 INSN(illegal, 4afc, ffff, CF_ISA_A);
2879 INSN(mull, 4c00, ffc0, CF_ISA_A);
2880 INSN(divl, 4c40, ffc0, CF_ISA_A);
2881 INSN(sats, 4c80, fff8, CF_ISA_B);
2882 INSN(trap, 4e40, fff0, CF_ISA_A);
2883 INSN(link, 4e50, fff8, CF_ISA_A);
2884 INSN(unlk, 4e58, fff8, CF_ISA_A);
2885 INSN(move_to_usp, 4e60, fff8, USP);
2886 INSN(move_from_usp, 4e68, fff8, USP);
2887 INSN(nop, 4e71, ffff, CF_ISA_A);
2888 INSN(stop, 4e72, ffff, CF_ISA_A);
2889 INSN(rte, 4e73, ffff, CF_ISA_A);
2890 INSN(rts, 4e75, ffff, CF_ISA_A);
2891 INSN(movec, 4e7b, ffff, CF_ISA_A);
2892 INSN(jump, 4e80, ffc0, CF_ISA_A);
2893 INSN(jump, 4ec0, ffc0, CF_ISA_A);
2894 INSN(addsubq, 5180, f1c0, CF_ISA_A);
2895 INSN(scc, 50c0, f0f8, CF_ISA_A);
2896 INSN(addsubq, 5080, f1c0, CF_ISA_A);
2897 INSN(tpf, 51f8, fff8, CF_ISA_A);
2898
2899 /* Branch instructions. */
2900 INSN(branch, 6000, f000, CF_ISA_A);
2901 /* Disable long branch instructions, then add back the ones we want. */
2902 INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */
2903 INSN(branch, 60ff, f0ff, CF_ISA_B);
2904 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
2905 INSN(branch, 60ff, ffff, BRAL);
2906
2907 INSN(moveq, 7000, f100, CF_ISA_A);
2908 INSN(mvzs, 7100, f100, CF_ISA_B);
2909 INSN(or, 8000, f000, CF_ISA_A);
2910 INSN(divw, 80c0, f0c0, CF_ISA_A);
2911 INSN(addsub, 9000, f000, CF_ISA_A);
2912 INSN(subx, 9180, f1f8, CF_ISA_A);
2913 INSN(suba, 91c0, f1c0, CF_ISA_A);
2914
2915 INSN(undef_mac, a000, f000, CF_ISA_A);
2916 INSN(mac, a000, f100, CF_EMAC);
2917 INSN(from_mac, a180, f9b0, CF_EMAC);
2918 INSN(move_mac, a110, f9fc, CF_EMAC);
2919 INSN(from_macsr,a980, f9f0, CF_EMAC);
2920 INSN(from_mask, ad80, fff0, CF_EMAC);
2921 INSN(from_mext, ab80, fbf0, CF_EMAC);
2922 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
2923 INSN(to_mac, a100, f9c0, CF_EMAC);
2924 INSN(to_macsr, a900, ffc0, CF_EMAC);
2925 INSN(to_mext, ab00, fbc0, CF_EMAC);
2926 INSN(to_mask, ad00, ffc0, CF_EMAC);
2927
2928 INSN(mov3q, a140, f1c0, CF_ISA_B);
2929 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
2930 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
2931 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
2932 INSN(cmp, b080, f1c0, CF_ISA_A);
2933 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
2934 INSN(eor, b180, f1c0, CF_ISA_A);
2935 INSN(and, c000, f000, CF_ISA_A);
2936 INSN(mulw, c0c0, f0c0, CF_ISA_A);
2937 INSN(addsub, d000, f000, CF_ISA_A);
2938 INSN(addx, d180, f1f8, CF_ISA_A);
2939 INSN(adda, d1c0, f1c0, CF_ISA_A);
2940 INSN(shift_im, e080, f0f0, CF_ISA_A);
2941 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
2942 INSN(undef_fpu, f000, f000, CF_ISA_A);
2943 INSN(fpu, f200, ffc0, CF_FPU);
2944 INSN(fbcc, f280, ffc0, CF_FPU);
2945 INSN(frestore, f340, ffc0, CF_FPU);
2946 INSN(fsave, f340, ffc0, CF_FPU);
2947 INSN(intouch, f340, ffc0, CF_ISA_A);
2948 INSN(cpushl, f428, ff38, CF_ISA_A);
2949 INSN(wddata, fb00, ff00, CF_ISA_A);
2950 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
2951 #undef INSN
2952 }
2953
2954 /* ??? Some of this implementation is not exception safe. We should always
2955 write back the result to memory before setting the condition codes. */
2956 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
2957 {
2958 uint16_t insn;
2959
2960 insn = cpu_lduw_code(env, s->pc);
2961 s->pc += 2;
2962
2963 opcode_table[insn](env, s, insn);
2964 }
2965
2966 /* generate intermediate code for basic block 'tb'. */
2967 void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
2968 {
2969 M68kCPU *cpu = m68k_env_get_cpu(env);
2970 CPUState *cs = CPU(cpu);
2971 DisasContext dc1, *dc = &dc1;
2972 target_ulong pc_start;
2973 int pc_offset;
2974 int num_insns;
2975 int max_insns;
2976
2977 /* generate intermediate code */
2978 pc_start = tb->pc;
2979
2980 dc->tb = tb;
2981
2982 dc->env = env;
2983 dc->is_jmp = DISAS_NEXT;
2984 dc->pc = pc_start;
2985 dc->cc_op = CC_OP_DYNAMIC;
2986 dc->singlestep_enabled = cs->singlestep_enabled;
2987 dc->fpcr = env->fpcr;
2988 dc->user = (env->sr & SR_S) == 0;
2989 dc->done_mac = 0;
2990 num_insns = 0;
2991 max_insns = tb->cflags & CF_COUNT_MASK;
2992 if (max_insns == 0) {
2993 max_insns = CF_COUNT_MASK;
2994 }
2995 if (max_insns > TCG_MAX_INSNS) {
2996 max_insns = TCG_MAX_INSNS;
2997 }
2998
2999 gen_tb_start(tb);
3000 do {
3001 pc_offset = dc->pc - pc_start;
3002 gen_throws_exception = NULL;
3003 tcg_gen_insn_start(dc->pc);
3004 num_insns++;
3005
3006 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3007 gen_exception(dc, dc->pc, EXCP_DEBUG);
3008 dc->is_jmp = DISAS_JUMP;
3009 /* The address covered by the breakpoint must be included in
3010 [tb->pc, tb->pc + tb->size) in order to for it to be
3011 properly cleared -- thus we increment the PC here so that
3012 the logic setting tb->size below does the right thing. */
3013 dc->pc += 2;
3014 break;
3015 }
3016
3017 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
3018 gen_io_start();
3019 }
3020
3021 dc->insn_pc = dc->pc;
3022 disas_m68k_insn(env, dc);
3023 } while (!dc->is_jmp && !tcg_op_buf_full() &&
3024 !cs->singlestep_enabled &&
3025 !singlestep &&
3026 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
3027 num_insns < max_insns);
3028
3029 if (tb->cflags & CF_LAST_IO)
3030 gen_io_end();
3031 if (unlikely(cs->singlestep_enabled)) {
3032 /* Make sure the pc is updated, and raise a debug exception. */
3033 if (!dc->is_jmp) {
3034 gen_flush_cc_op(dc);
3035 tcg_gen_movi_i32(QREG_PC, dc->pc);
3036 }
3037 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
3038 } else {
3039 switch(dc->is_jmp) {
3040 case DISAS_NEXT:
3041 gen_flush_cc_op(dc);
3042 gen_jmp_tb(dc, 0, dc->pc);
3043 break;
3044 default:
3045 case DISAS_JUMP:
3046 case DISAS_UPDATE:
3047 gen_flush_cc_op(dc);
3048 /* indicate that the hash table must be used to find the next TB */
3049 tcg_gen_exit_tb(0);
3050 break;
3051 case DISAS_TB_JUMP:
3052 /* nothing more to generate */
3053 break;
3054 }
3055 }
3056 gen_tb_end(tb, num_insns);
3057
3058 #ifdef DEBUG_DISAS
3059 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3060 qemu_log("----------------\n");
3061 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3062 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
3063 qemu_log("\n");
3064 }
3065 #endif
3066 tb->size = dc->pc - pc_start;
3067 tb->icount = num_insns;
3068 }
3069
3070 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3071 int flags)
3072 {
3073 M68kCPU *cpu = M68K_CPU(cs);
3074 CPUM68KState *env = &cpu->env;
3075 int i;
3076 uint16_t sr;
3077 CPU_DoubleU u;
3078 for (i = 0; i < 8; i++)
3079 {
3080 u.d = env->fregs[i];
3081 cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3082 i, env->dregs[i], i, env->aregs[i],
3083 i, u.l.upper, u.l.lower, *(double *)&u.d);
3084 }
3085 cpu_fprintf (f, "PC = %08x ", env->pc);
3086 sr = env->sr;
3087 cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-',
3088 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
3089 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
3090 cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
3091 }
3092
3093 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
3094 target_ulong *data)
3095 {
3096 env->pc = data[0];
3097 }
AR7 emulation for QEMU