target-openrisc/sys_helper.c

   1 /*
   2  * OpenRISC system instructions helper routines
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Zhizhou Zhang <etouzh@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "exec/helper-proto.h"
  25
  26 #define TO_SPR(group, number) (((group) << 11) + (number))
  27
  28 void HELPER(mtspr)(CPUOpenRISCState *env,
  29                    target_ulong ra, target_ulong rb, target_ulong offset)
  30 {
  31 #ifndef CONFIG_USER_ONLY
  32     int spr = (ra | offset);
  33     int idx;
  34
  35     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
  36     CPUState *cs = CPU(cpu);
  37
  38     switch (spr) {
  39     case TO_SPR(0, 0): /* VR */
  40         env->vr = rb;
  41         break;
  42
  43     case TO_SPR(0, 16): /* NPC */
  44         env->npc = rb;
  45         break;
  46
  47     case TO_SPR(0, 17): /* SR */
  48         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
  49             (rb & (SR_IME | SR_DME | SR_SM))) {
  50             tlb_flush(cs, 1);
  51         }
  52         env->sr = rb;
  53         env->sr |= SR_FO;      /* FO is const equal to 1 */
  54         if (env->sr & SR_DME) {
  55             env->tlb->cpu_openrisc_map_address_data =
  56                 &cpu_openrisc_get_phys_data;
  57         } else {
  58             env->tlb->cpu_openrisc_map_address_data =
  59                 &cpu_openrisc_get_phys_nommu;
  60         }
  61
  62         if (env->sr & SR_IME) {
  63             env->tlb->cpu_openrisc_map_address_code =
  64                 &cpu_openrisc_get_phys_code;
  65         } else {
  66             env->tlb->cpu_openrisc_map_address_code =
  67                 &cpu_openrisc_get_phys_nommu;
  68         }
  69         break;
  70
  71     case TO_SPR(0, 18): /* PPC */
  72         env->ppc = rb;
  73         break;
  74
  75     case TO_SPR(0, 32): /* EPCR */
  76         env->epcr = rb;
  77         break;
  78
  79     case TO_SPR(0, 48): /* EEAR */
  80         env->eear = rb;
  81         break;
  82
  83     case TO_SPR(0, 64): /* ESR */
  84         env->esr = rb;
  85         break;
  86     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
  87         idx = spr - TO_SPR(1, 512);
  88         if (!(rb & 1)) {
  89             tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
  90         }
  91         env->tlb->dtlb[0][idx].mr = rb;
  92         break;
  93
  94     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
  95         idx = spr - TO_SPR(1, 640);
  96         env->tlb->dtlb[0][idx].tr = rb;
  97         break;
  98     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
  99     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 100     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 101     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 102     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 103     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 104         break;
 105     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):   /* ITLBW0MR 0-127 */
 106         idx = spr - TO_SPR(2, 512);
 107         if (!(rb & 1)) {
 108             tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
 109         }
 110         env->tlb->itlb[0][idx].mr = rb;
 111         break;
 112
 113     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 114         idx = spr - TO_SPR(2, 640);
 115         env->tlb->itlb[0][idx].tr = rb;
 116         break;
 117     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 118     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 119     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 120     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 121     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 122     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 123         break;
 124     case TO_SPR(9, 0):  /* PICMR */
 125         env->picmr |= rb;
 126         break;
 127     case TO_SPR(9, 2):  /* PICSR */
 128         env->picsr &= ~rb;
 129         break;
 130     case TO_SPR(10, 0): /* TTMR */
 131         {
 132             if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
 133                 switch (rb & TTMR_M) {
 134                 case TIMER_NONE:
 135                     cpu_openrisc_count_stop(cpu);
 136                     break;
 137                 case TIMER_INTR:
 138                 case TIMER_SHOT:
 139                 case TIMER_CONT:
 140                     cpu_openrisc_count_start(cpu);
 141                     break;
 142                 default:
 143                     break;
 144                 }
 145             }
 146
 147             int ip = env->ttmr & TTMR_IP;
 148
 149             if (rb & TTMR_IP) {    /* Keep IP bit.  */
 150                 env->ttmr = (rb & ~TTMR_IP) | ip;
 151             } else {    /* Clear IP bit.  */
 152                 env->ttmr = rb & ~TTMR_IP;
 153                 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 154             }
 155
 156             cpu_openrisc_timer_update(cpu);
 157         }
 158         break;
 159
 160     case TO_SPR(10, 1): /* TTCR */
 161         env->ttcr = rb;
 162         if (env->ttmr & TIMER_NONE) {
 163             return;
 164         }
 165         cpu_openrisc_timer_update(cpu);
 166         break;
 167     default:
 168
 169         break;
 170     }
 171 #endif
 172 }
 173
 174 target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
 175                            target_ulong rd, target_ulong ra, uint32_t offset)
 176 {
 177 #ifndef CONFIG_USER_ONLY
 178     int spr = (ra | offset);
 179     int idx;
 180
 181     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
 182
 183     switch (spr) {
 184     case TO_SPR(0, 0): /* VR */
 185         return env->vr & SPR_VR;
 186
 187     case TO_SPR(0, 1): /* UPR */
 188         return env->upr;    /* TT, DM, IM, UP present */
 189
 190     case TO_SPR(0, 2): /* CPUCFGR */
 191         return env->cpucfgr;
 192
 193     case TO_SPR(0, 3): /* DMMUCFGR */
 194         return env->dmmucfgr;    /* 1Way, 64 entries */
 195
 196     case TO_SPR(0, 4): /* IMMUCFGR */
 197         return env->immucfgr;
 198
 199     case TO_SPR(0, 16): /* NPC */
 200         return env->npc;
 201
 202     case TO_SPR(0, 17): /* SR */
 203         return env->sr;
 204
 205     case TO_SPR(0, 18): /* PPC */
 206         return env->ppc;
 207
 208     case TO_SPR(0, 32): /* EPCR */
 209         return env->epcr;
 210
 211     case TO_SPR(0, 48): /* EEAR */
 212         return env->eear;
 213
 214     case TO_SPR(0, 64): /* ESR */
 215         return env->esr;
 216
 217     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
 218         idx = spr - TO_SPR(1, 512);
 219         return env->tlb->dtlb[0][idx].mr;
 220
 221     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
 222         idx = spr - TO_SPR(1, 640);
 223         return env->tlb->dtlb[0][idx].tr;
 224
 225     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
 226     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 227     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 228     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 229     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 230     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 231         break;
 232
 233     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
 234         idx = spr - TO_SPR(2, 512);
 235         return env->tlb->itlb[0][idx].mr;
 236
 237     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 238         idx = spr - TO_SPR(2, 640);
 239         return env->tlb->itlb[0][idx].tr;
 240
 241     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 242     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 243     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 244     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 245     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 246     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 247         break;
 248
 249     case TO_SPR(9, 0):  /* PICMR */
 250         return env->picmr;
 251
 252     case TO_SPR(9, 2):  /* PICSR */
 253         return env->picsr;
 254
 255     case TO_SPR(10, 0): /* TTMR */
 256         return env->ttmr;
 257
 258     case TO_SPR(10, 1): /* TTCR */
 259         cpu_openrisc_count_update(cpu);
 260         return env->ttcr;
 261
 262     default:
 263         break;
 264     }
 265 #endif
 266
 267 /*If we later need to add tracepoints (or debug printfs) for the return
 268 value, it may be useful to structure the code like this:
 269
 270 target_ulong ret = 0;
 271
 272 switch() {
 273 case x:
 274  ret = y;
 275  break;
 276 case z:
 277  ret = 42;
 278  break;
 279 ...
 280 }
 281
 282 later something like trace_spr_read(ret);
 283
 284 return ret;*/
 285
 286     /* for rd is passed in, if rd unchanged, just keep it back.  */
 287     return rd;
 288 }