hw/pci/pci_host.c

   1 /*
   2  * pci_host.c
   3  *
   4  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/pci/pci.h"
  23 #include "hw/pci/pci_host.h"
  24 #include "hw/pci/pci_bus.h"
  25 #include "trace.h"
  26
  27 /* debug PCI */
  28 //#define DEBUG_PCI
  29
  30 #ifdef DEBUG_PCI
  31 #define PCI_DPRINTF(fmt, ...) \
  32 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
  33 #else
  34 #define PCI_DPRINTF(fmt, ...)
  35 #endif
  36
  37 /*
  38  * PCI address
  39  * bit 16 - 24: bus number
  40  * bit  8 - 15: devfun number
  41  * bit  0 -  7: offset in configuration space of a given pci device
  42  */
  43
  44 /* the helper function to get a PCIDevice* for a given pci address */
  45 static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
  46 {
  47     uint8_t bus_num = addr >> 16;
  48     uint8_t devfn = addr >> 8;
  49
  50     return pci_find_device(bus, bus_num, devfn);
  51 }
  52
  53 void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
  54                                   uint32_t limit, uint32_t val, uint32_t len)
  55 {
  56     assert(len <= 4);
  57     /* non-zero functions are only exposed when function 0 is present,
  58      * allowing direct removal of unexposed functions.
  59      */
  60     if (pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) {
  61         return;
  62     }
  63
  64     trace_pci_cfg_write(pci_dev->name, PCI_SLOT(pci_dev->devfn),
  65                         PCI_FUNC(pci_dev->devfn), addr, val);
  66     pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
  67 }
  68
  69 uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
  70                                      uint32_t limit, uint32_t len)
  71 {
  72     uint32_t ret;
  73
  74     assert(len <= 4);
  75     /* non-zero functions are only exposed when function 0 is present,
  76      * allowing direct removal of unexposed functions.
  77      */
  78     if (pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) {
  79         return ~0x0;
  80     }
  81
  82     ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
  83     trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn),
  84                        PCI_FUNC(pci_dev->devfn), addr, ret);
  85
  86     return ret;
  87 }
  88
  89 void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
  90 {
  91     PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
  92     uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
  93
  94     if (!pci_dev) {
  95         return;
  96     }
  97
  98     PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n",
  99                 __func__, pci_dev->name, config_addr, val, len);
 100     pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE,
 101                                  val, len);
 102 }
 103
 104 uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
 105 {
 106     PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
 107     uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
 108     uint32_t val;
 109
 110     if (!pci_dev) {
 111         return ~0x0;
 112     }
 113
 114     val = pci_host_config_read_common(pci_dev, config_addr,
 115                                       PCI_CONFIG_SPACE_SIZE, len);
 116     PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n",
 117                 __func__, pci_dev->name, config_addr, val, len);
 118
 119     return val;
 120 }
 121
 122 static void pci_host_config_write(void *opaque, hwaddr addr,
 123                                   uint64_t val, unsigned len)
 124 {
 125     PCIHostState *s = opaque;
 126
 127     PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
 128                 __func__, addr, len, val);
 129     if (addr != 0 || len != 4) {
 130         return;
 131     }
 132     s->config_reg = val;
 133 }
 134
 135 static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
 136                                      unsigned len)
 137 {
 138     PCIHostState *s = opaque;
 139     uint32_t val = s->config_reg;
 140
 141     PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
 142                 __func__, addr, len, val);
 143     return val;
 144 }
 145
 146 static void pci_host_data_write(void *opaque, hwaddr addr,
 147                                 uint64_t val, unsigned len)
 148 {
 149     PCIHostState *s = opaque;
 150     PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n",
 151                 addr, len, (unsigned)val);
 152     if (s->config_reg & (1u << 31))
 153         pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
 154 }
 155
 156 static uint64_t pci_host_data_read(void *opaque,
 157                                    hwaddr addr, unsigned len)
 158 {
 159     PCIHostState *s = opaque;
 160     uint32_t val;
 161     if (!(s->config_reg & (1U << 31))) {
 162         return 0xffffffff;
 163     }
 164     val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
 165     PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
 166                 addr, len, val);
 167     return val;
 168 }
 169
 170 const MemoryRegionOps pci_host_conf_le_ops = {
 171     .read = pci_host_config_read,
 172     .write = pci_host_config_write,
 173     .endianness = DEVICE_LITTLE_ENDIAN,
 174 };
 175
 176 const MemoryRegionOps pci_host_conf_be_ops = {
 177     .read = pci_host_config_read,
 178     .write = pci_host_config_write,
 179     .endianness = DEVICE_BIG_ENDIAN,
 180 };
 181
 182 const MemoryRegionOps pci_host_data_le_ops = {
 183     .read = pci_host_data_read,
 184     .write = pci_host_data_write,
 185     .endianness = DEVICE_LITTLE_ENDIAN,
 186 };
 187
 188 const MemoryRegionOps pci_host_data_be_ops = {
 189     .read = pci_host_data_read,
 190     .write = pci_host_data_write,
 191     .endianness = DEVICE_BIG_ENDIAN,
 192 };
 193
 194 static const TypeInfo pci_host_type_info = {
 195     .name = TYPE_PCI_HOST_BRIDGE,
 196     .parent = TYPE_SYS_BUS_DEVICE,
 197     .abstract = true,
 198     .class_size = sizeof(PCIHostBridgeClass),
 199     .instance_size = sizeof(PCIHostState),
 200 };
 201
 202 static void pci_host_register_types(void)
 203 {
 204     type_register_static(&pci_host_type_info);
 205 }
 206
 207 type_init(pci_host_register_types)