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[qemu/ar7.git] / hw / misc / slavio_misc.c
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1 /*
2 * QEMU Sparc SLAVIO aux io port emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/sysbus.h"
28 #include "trace.h"
31 * This is the auxio port, chip control and system control part of
32 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
35 * This also includes the PMC CPU idle controller.
38 #define TYPE_SLAVIO_MISC "slavio_misc"
39 #define SLAVIO_MISC(obj) OBJECT_CHECK(MiscState, (obj), TYPE_SLAVIO_MISC)
41 typedef struct MiscState {
42 SysBusDevice parent_obj;
44 MemoryRegion cfg_iomem;
45 MemoryRegion diag_iomem;
46 MemoryRegion mdm_iomem;
47 MemoryRegion led_iomem;
48 MemoryRegion sysctrl_iomem;
49 MemoryRegion aux1_iomem;
50 MemoryRegion aux2_iomem;
51 qemu_irq irq;
52 qemu_irq fdc_tc;
53 uint32_t dummy;
54 uint8_t config;
55 uint8_t aux1, aux2;
56 uint8_t diag, mctrl;
57 uint8_t sysctrl;
58 uint16_t leds;
59 } MiscState;
61 #define TYPE_APC "apc"
62 #define APC(obj) OBJECT_CHECK(APCState, (obj), TYPE_APC)
64 typedef struct APCState {
65 SysBusDevice parent_obj;
67 MemoryRegion iomem;
68 qemu_irq cpu_halt;
69 } APCState;
71 #define MISC_SIZE 1
72 #define LED_SIZE 2
73 #define SYSCTRL_SIZE 4
75 #define AUX1_TC 0x02
77 #define AUX2_PWROFF 0x01
78 #define AUX2_PWRINTCLR 0x02
79 #define AUX2_PWRFAIL 0x20
81 #define CFG_PWRINTEN 0x08
83 #define SYS_RESET 0x01
84 #define SYS_RESETSTAT 0x02
86 static void slavio_misc_update_irq(void *opaque)
88 MiscState *s = opaque;
90 if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
91 trace_slavio_misc_update_irq_raise();
92 qemu_irq_raise(s->irq);
93 } else {
94 trace_slavio_misc_update_irq_lower();
95 qemu_irq_lower(s->irq);
99 static void slavio_misc_reset(DeviceState *d)
101 MiscState *s = SLAVIO_MISC(d);
103 // Diagnostic and system control registers not cleared in reset
104 s->config = s->aux1 = s->aux2 = s->mctrl = 0;
107 static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
109 MiscState *s = opaque;
111 trace_slavio_set_power_fail(power_failing, s->config);
112 if (power_failing && (s->config & CFG_PWRINTEN)) {
113 s->aux2 |= AUX2_PWRFAIL;
114 } else {
115 s->aux2 &= ~AUX2_PWRFAIL;
117 slavio_misc_update_irq(s);
120 static void slavio_cfg_mem_writeb(void *opaque, hwaddr addr,
121 uint64_t val, unsigned size)
123 MiscState *s = opaque;
125 trace_slavio_cfg_mem_writeb(val & 0xff);
126 s->config = val & 0xff;
127 slavio_misc_update_irq(s);
130 static uint64_t slavio_cfg_mem_readb(void *opaque, hwaddr addr,
131 unsigned size)
133 MiscState *s = opaque;
134 uint32_t ret = 0;
136 ret = s->config;
137 trace_slavio_cfg_mem_readb(ret);
138 return ret;
141 static const MemoryRegionOps slavio_cfg_mem_ops = {
142 .read = slavio_cfg_mem_readb,
143 .write = slavio_cfg_mem_writeb,
144 .endianness = DEVICE_NATIVE_ENDIAN,
145 .valid = {
146 .min_access_size = 1,
147 .max_access_size = 1,
151 static void slavio_diag_mem_writeb(void *opaque, hwaddr addr,
152 uint64_t val, unsigned size)
154 MiscState *s = opaque;
156 trace_slavio_diag_mem_writeb(val & 0xff);
157 s->diag = val & 0xff;
160 static uint64_t slavio_diag_mem_readb(void *opaque, hwaddr addr,
161 unsigned size)
163 MiscState *s = opaque;
164 uint32_t ret = 0;
166 ret = s->diag;
167 trace_slavio_diag_mem_readb(ret);
168 return ret;
171 static const MemoryRegionOps slavio_diag_mem_ops = {
172 .read = slavio_diag_mem_readb,
173 .write = slavio_diag_mem_writeb,
174 .endianness = DEVICE_NATIVE_ENDIAN,
175 .valid = {
176 .min_access_size = 1,
177 .max_access_size = 1,
181 static void slavio_mdm_mem_writeb(void *opaque, hwaddr addr,
182 uint64_t val, unsigned size)
184 MiscState *s = opaque;
186 trace_slavio_mdm_mem_writeb(val & 0xff);
187 s->mctrl = val & 0xff;
190 static uint64_t slavio_mdm_mem_readb(void *opaque, hwaddr addr,
191 unsigned size)
193 MiscState *s = opaque;
194 uint32_t ret = 0;
196 ret = s->mctrl;
197 trace_slavio_mdm_mem_readb(ret);
198 return ret;
201 static const MemoryRegionOps slavio_mdm_mem_ops = {
202 .read = slavio_mdm_mem_readb,
203 .write = slavio_mdm_mem_writeb,
204 .endianness = DEVICE_NATIVE_ENDIAN,
205 .valid = {
206 .min_access_size = 1,
207 .max_access_size = 1,
211 static void slavio_aux1_mem_writeb(void *opaque, hwaddr addr,
212 uint64_t val, unsigned size)
214 MiscState *s = opaque;
216 trace_slavio_aux1_mem_writeb(val & 0xff);
217 if (val & AUX1_TC) {
218 // Send a pulse to floppy terminal count line
219 if (s->fdc_tc) {
220 qemu_irq_raise(s->fdc_tc);
221 qemu_irq_lower(s->fdc_tc);
223 val &= ~AUX1_TC;
225 s->aux1 = val & 0xff;
228 static uint64_t slavio_aux1_mem_readb(void *opaque, hwaddr addr,
229 unsigned size)
231 MiscState *s = opaque;
232 uint32_t ret = 0;
234 ret = s->aux1;
235 trace_slavio_aux1_mem_readb(ret);
236 return ret;
239 static const MemoryRegionOps slavio_aux1_mem_ops = {
240 .read = slavio_aux1_mem_readb,
241 .write = slavio_aux1_mem_writeb,
242 .endianness = DEVICE_NATIVE_ENDIAN,
243 .valid = {
244 .min_access_size = 1,
245 .max_access_size = 1,
249 static void slavio_aux2_mem_writeb(void *opaque, hwaddr addr,
250 uint64_t val, unsigned size)
252 MiscState *s = opaque;
254 val &= AUX2_PWRINTCLR | AUX2_PWROFF;
255 trace_slavio_aux2_mem_writeb(val & 0xff);
256 val |= s->aux2 & AUX2_PWRFAIL;
257 if (val & AUX2_PWRINTCLR) // Clear Power Fail int
258 val &= AUX2_PWROFF;
259 s->aux2 = val;
260 if (val & AUX2_PWROFF)
261 qemu_system_shutdown_request();
262 slavio_misc_update_irq(s);
265 static uint64_t slavio_aux2_mem_readb(void *opaque, hwaddr addr,
266 unsigned size)
268 MiscState *s = opaque;
269 uint32_t ret = 0;
271 ret = s->aux2;
272 trace_slavio_aux2_mem_readb(ret);
273 return ret;
276 static const MemoryRegionOps slavio_aux2_mem_ops = {
277 .read = slavio_aux2_mem_readb,
278 .write = slavio_aux2_mem_writeb,
279 .endianness = DEVICE_NATIVE_ENDIAN,
280 .valid = {
281 .min_access_size = 1,
282 .max_access_size = 1,
286 static void apc_mem_writeb(void *opaque, hwaddr addr,
287 uint64_t val, unsigned size)
289 APCState *s = opaque;
291 trace_apc_mem_writeb(val & 0xff);
292 qemu_irq_raise(s->cpu_halt);
295 static uint64_t apc_mem_readb(void *opaque, hwaddr addr,
296 unsigned size)
298 uint32_t ret = 0;
300 trace_apc_mem_readb(ret);
301 return ret;
304 static const MemoryRegionOps apc_mem_ops = {
305 .read = apc_mem_readb,
306 .write = apc_mem_writeb,
307 .endianness = DEVICE_NATIVE_ENDIAN,
308 .valid = {
309 .min_access_size = 1,
310 .max_access_size = 1,
314 static uint64_t slavio_sysctrl_mem_readl(void *opaque, hwaddr addr,
315 unsigned size)
317 MiscState *s = opaque;
318 uint32_t ret = 0;
320 switch (addr) {
321 case 0:
322 ret = s->sysctrl;
323 break;
324 default:
325 break;
327 trace_slavio_sysctrl_mem_readl(ret);
328 return ret;
331 static void slavio_sysctrl_mem_writel(void *opaque, hwaddr addr,
332 uint64_t val, unsigned size)
334 MiscState *s = opaque;
336 trace_slavio_sysctrl_mem_writel(val);
337 switch (addr) {
338 case 0:
339 if (val & SYS_RESET) {
340 s->sysctrl = SYS_RESETSTAT;
341 qemu_system_reset_request();
343 break;
344 default:
345 break;
349 static const MemoryRegionOps slavio_sysctrl_mem_ops = {
350 .read = slavio_sysctrl_mem_readl,
351 .write = slavio_sysctrl_mem_writel,
352 .endianness = DEVICE_NATIVE_ENDIAN,
353 .valid = {
354 .min_access_size = 4,
355 .max_access_size = 4,
359 static uint64_t slavio_led_mem_readw(void *opaque, hwaddr addr,
360 unsigned size)
362 MiscState *s = opaque;
363 uint32_t ret = 0;
365 switch (addr) {
366 case 0:
367 ret = s->leds;
368 break;
369 default:
370 break;
372 trace_slavio_led_mem_readw(ret);
373 return ret;
376 static void slavio_led_mem_writew(void *opaque, hwaddr addr,
377 uint64_t val, unsigned size)
379 MiscState *s = opaque;
381 trace_slavio_led_mem_writew(val & 0xffff);
382 switch (addr) {
383 case 0:
384 s->leds = val;
385 break;
386 default:
387 break;
391 static const MemoryRegionOps slavio_led_mem_ops = {
392 .read = slavio_led_mem_readw,
393 .write = slavio_led_mem_writew,
394 .endianness = DEVICE_NATIVE_ENDIAN,
395 .valid = {
396 .min_access_size = 2,
397 .max_access_size = 2,
401 static const VMStateDescription vmstate_misc = {
402 .name ="slavio_misc",
403 .version_id = 1,
404 .minimum_version_id = 1,
405 .fields = (VMStateField[]) {
406 VMSTATE_UINT32(dummy, MiscState),
407 VMSTATE_UINT8(config, MiscState),
408 VMSTATE_UINT8(aux1, MiscState),
409 VMSTATE_UINT8(aux2, MiscState),
410 VMSTATE_UINT8(diag, MiscState),
411 VMSTATE_UINT8(mctrl, MiscState),
412 VMSTATE_UINT8(sysctrl, MiscState),
413 VMSTATE_END_OF_LIST()
417 static int apc_init1(SysBusDevice *dev)
419 APCState *s = APC(dev);
421 sysbus_init_irq(dev, &s->cpu_halt);
423 /* Power management (APC) XXX: not a Slavio device */
424 memory_region_init_io(&s->iomem, OBJECT(s), &apc_mem_ops, s,
425 "apc", MISC_SIZE);
426 sysbus_init_mmio(dev, &s->iomem);
427 return 0;
430 static int slavio_misc_init1(SysBusDevice *sbd)
432 DeviceState *dev = DEVICE(sbd);
433 MiscState *s = SLAVIO_MISC(dev);
435 sysbus_init_irq(sbd, &s->irq);
436 sysbus_init_irq(sbd, &s->fdc_tc);
438 /* 8 bit registers */
439 /* Slavio control */
440 memory_region_init_io(&s->cfg_iomem, OBJECT(s), &slavio_cfg_mem_ops, s,
441 "configuration", MISC_SIZE);
442 sysbus_init_mmio(sbd, &s->cfg_iomem);
444 /* Diagnostics */
445 memory_region_init_io(&s->diag_iomem, OBJECT(s), &slavio_diag_mem_ops, s,
446 "diagnostic", MISC_SIZE);
447 sysbus_init_mmio(sbd, &s->diag_iomem);
449 /* Modem control */
450 memory_region_init_io(&s->mdm_iomem, OBJECT(s), &slavio_mdm_mem_ops, s,
451 "modem", MISC_SIZE);
452 sysbus_init_mmio(sbd, &s->mdm_iomem);
454 /* 16 bit registers */
455 /* ss600mp diag LEDs */
456 memory_region_init_io(&s->led_iomem, OBJECT(s), &slavio_led_mem_ops, s,
457 "leds", LED_SIZE);
458 sysbus_init_mmio(sbd, &s->led_iomem);
460 /* 32 bit registers */
461 /* System control */
462 memory_region_init_io(&s->sysctrl_iomem, OBJECT(s), &slavio_sysctrl_mem_ops, s,
463 "system-control", SYSCTRL_SIZE);
464 sysbus_init_mmio(sbd, &s->sysctrl_iomem);
466 /* AUX 1 (Misc System Functions) */
467 memory_region_init_io(&s->aux1_iomem, OBJECT(s), &slavio_aux1_mem_ops, s,
468 "misc-system-functions", MISC_SIZE);
469 sysbus_init_mmio(sbd, &s->aux1_iomem);
471 /* AUX 2 (Software Powerdown Control) */
472 memory_region_init_io(&s->aux2_iomem, OBJECT(s), &slavio_aux2_mem_ops, s,
473 "software-powerdown-control", MISC_SIZE);
474 sysbus_init_mmio(sbd, &s->aux2_iomem);
476 qdev_init_gpio_in(dev, slavio_set_power_fail, 1);
478 return 0;
481 static void slavio_misc_class_init(ObjectClass *klass, void *data)
483 DeviceClass *dc = DEVICE_CLASS(klass);
484 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
486 k->init = slavio_misc_init1;
487 dc->reset = slavio_misc_reset;
488 dc->vmsd = &vmstate_misc;
491 static const TypeInfo slavio_misc_info = {
492 .name = TYPE_SLAVIO_MISC,
493 .parent = TYPE_SYS_BUS_DEVICE,
494 .instance_size = sizeof(MiscState),
495 .class_init = slavio_misc_class_init,
498 static void apc_class_init(ObjectClass *klass, void *data)
500 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
502 k->init = apc_init1;
505 static const TypeInfo apc_info = {
506 .name = TYPE_APC,
507 .parent = TYPE_SYS_BUS_DEVICE,
508 .instance_size = sizeof(MiscState),
509 .class_init = apc_class_init,
512 static void slavio_misc_register_types(void)
514 type_register_static(&slavio_misc_info);
515 type_register_static(&apc_info);
518 type_init(slavio_misc_register_types)