4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "qemu/datadir.h"
28 #include "qemu/units.h"
30 #include "hw/pci/pci.h"
31 #include "hw/pci/pci_bridge.h"
32 #include "hw/pci/pci_bus.h"
33 #include "hw/pci/pci_host.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/qdev-properties-system.h"
36 #include "migration/qemu-file-types.h"
37 #include "migration/vmstate.h"
38 #include "monitor/monitor.h"
40 #include "sysemu/numa.h"
41 #include "sysemu/sysemu.h"
42 #include "hw/loader.h"
43 #include "qemu/error-report.h"
44 #include "qemu/range.h"
46 #include "hw/pci/msi.h"
47 #include "hw/pci/msix.h"
48 #include "exec/address-spaces.h"
49 #include "hw/hotplug.h"
50 #include "hw/boards.h"
51 #include "qapi/error.h"
52 #include "qapi/qapi-commands-pci.h"
53 #include "qemu/cutils.h"
57 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
59 # define PCI_DPRINTF(format, ...) do { } while (0)
62 bool pci_available
= true;
64 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
65 static char *pcibus_get_dev_path(DeviceState
*dev
);
66 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
67 static void pcibus_reset(BusState
*qbus
);
69 static Property pci_props
[] = {
70 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
71 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
72 DEFINE_PROP_UINT32("romsize", PCIDevice
, romsize
, -1),
73 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
74 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
75 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
76 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice
, cap_present
,
77 QEMU_PCIE_LNKSTA_DLLLA_BITNR
, true),
78 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice
, cap_present
,
79 QEMU_PCIE_EXTCAP_INIT_BITNR
, true),
80 DEFINE_PROP_STRING("failover_pair_id", PCIDevice
,
82 DEFINE_PROP_UINT32("acpi-index", PCIDevice
, acpi_index
, 0),
83 DEFINE_PROP_END_OF_LIST()
86 static const VMStateDescription vmstate_pcibus
= {
89 .minimum_version_id
= 1,
90 .fields
= (VMStateField
[]) {
91 VMSTATE_INT32_EQUAL(nirq
, PCIBus
, NULL
),
92 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
,
93 nirq
, 0, vmstate_info_int32
,
99 static void pci_init_bus_master(PCIDevice
*pci_dev
)
101 AddressSpace
*dma_as
= pci_device_iommu_address_space(pci_dev
);
103 memory_region_init_alias(&pci_dev
->bus_master_enable_region
,
104 OBJECT(pci_dev
), "bus master",
105 dma_as
->root
, 0, memory_region_size(dma_as
->root
));
106 memory_region_set_enabled(&pci_dev
->bus_master_enable_region
, false);
107 memory_region_add_subregion(&pci_dev
->bus_master_container_region
, 0,
108 &pci_dev
->bus_master_enable_region
);
111 static void pcibus_machine_done(Notifier
*notifier
, void *data
)
113 PCIBus
*bus
= container_of(notifier
, PCIBus
, machine_done
);
116 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
117 if (bus
->devices
[i
]) {
118 pci_init_bus_master(bus
->devices
[i
]);
123 static void pci_bus_realize(BusState
*qbus
, Error
**errp
)
125 PCIBus
*bus
= PCI_BUS(qbus
);
127 bus
->machine_done
.notify
= pcibus_machine_done
;
128 qemu_add_machine_init_done_notifier(&bus
->machine_done
);
130 vmstate_register(NULL
, VMSTATE_INSTANCE_ID_ANY
, &vmstate_pcibus
, bus
);
133 static void pcie_bus_realize(BusState
*qbus
, Error
**errp
)
135 PCIBus
*bus
= PCI_BUS(qbus
);
136 Error
*local_err
= NULL
;
138 pci_bus_realize(qbus
, &local_err
);
140 error_propagate(errp
, local_err
);
145 * A PCI-E bus can support extended config space if it's the root
146 * bus, or if the bus/bridge above it does as well
148 if (pci_bus_is_root(bus
)) {
149 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
151 PCIBus
*parent_bus
= pci_get_bus(bus
->parent_dev
);
153 if (pci_bus_allows_extended_config_space(parent_bus
)) {
154 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
159 static void pci_bus_unrealize(BusState
*qbus
)
161 PCIBus
*bus
= PCI_BUS(qbus
);
163 qemu_remove_machine_init_done_notifier(&bus
->machine_done
);
165 vmstate_unregister(NULL
, &vmstate_pcibus
, bus
);
168 static int pcibus_num(PCIBus
*bus
)
170 if (pci_bus_is_root(bus
)) {
171 return 0; /* pci host bridge */
173 return bus
->parent_dev
->config
[PCI_SECONDARY_BUS
];
176 static uint16_t pcibus_numa_node(PCIBus
*bus
)
178 return NUMA_NODE_UNASSIGNED
;
181 static void pci_bus_class_init(ObjectClass
*klass
, void *data
)
183 BusClass
*k
= BUS_CLASS(klass
);
184 PCIBusClass
*pbc
= PCI_BUS_CLASS(klass
);
186 k
->print_dev
= pcibus_dev_print
;
187 k
->get_dev_path
= pcibus_get_dev_path
;
188 k
->get_fw_dev_path
= pcibus_get_fw_dev_path
;
189 k
->realize
= pci_bus_realize
;
190 k
->unrealize
= pci_bus_unrealize
;
191 k
->reset
= pcibus_reset
;
193 pbc
->bus_num
= pcibus_num
;
194 pbc
->numa_node
= pcibus_numa_node
;
197 static const TypeInfo pci_bus_info
= {
198 .name
= TYPE_PCI_BUS
,
200 .instance_size
= sizeof(PCIBus
),
201 .class_size
= sizeof(PCIBusClass
),
202 .class_init
= pci_bus_class_init
,
205 static const TypeInfo pcie_interface_info
= {
206 .name
= INTERFACE_PCIE_DEVICE
,
207 .parent
= TYPE_INTERFACE
,
210 static const TypeInfo conventional_pci_interface_info
= {
211 .name
= INTERFACE_CONVENTIONAL_PCI_DEVICE
,
212 .parent
= TYPE_INTERFACE
,
215 static void pcie_bus_class_init(ObjectClass
*klass
, void *data
)
217 BusClass
*k
= BUS_CLASS(klass
);
219 k
->realize
= pcie_bus_realize
;
222 static const TypeInfo pcie_bus_info
= {
223 .name
= TYPE_PCIE_BUS
,
224 .parent
= TYPE_PCI_BUS
,
225 .class_init
= pcie_bus_class_init
,
228 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
229 static void pci_update_mappings(PCIDevice
*d
);
230 static void pci_irq_handler(void *opaque
, int irq_num
, int level
);
231 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
, Error
**);
232 static void pci_del_option_rom(PCIDevice
*pdev
);
234 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
235 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
237 static QLIST_HEAD(, PCIHostState
) pci_host_bridges
;
239 int pci_bar(PCIDevice
*d
, int reg
)
243 if (reg
!= PCI_ROM_SLOT
)
244 return PCI_BASE_ADDRESS_0
+ reg
* 4;
246 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
247 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
250 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
252 return (d
->irq_state
>> irq_num
) & 0x1;
255 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
257 d
->irq_state
&= ~(0x1 << irq_num
);
258 d
->irq_state
|= level
<< irq_num
;
261 static void pci_bus_change_irq_level(PCIBus
*bus
, int irq_num
, int change
)
263 assert(irq_num
>= 0);
264 assert(irq_num
< bus
->nirq
);
265 bus
->irq_count
[irq_num
] += change
;
266 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
269 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
273 bus
= pci_get_bus(pci_dev
);
274 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
277 pci_dev
= bus
->parent_dev
;
279 pci_bus_change_irq_level(bus
, irq_num
, change
);
282 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
284 assert(irq_num
>= 0);
285 assert(irq_num
< bus
->nirq
);
286 return !!bus
->irq_count
[irq_num
];
289 /* Update interrupt status bit in config space on interrupt
291 static void pci_update_irq_status(PCIDevice
*dev
)
293 if (dev
->irq_state
) {
294 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
296 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
300 void pci_device_deassert_intx(PCIDevice
*dev
)
303 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
304 pci_irq_handler(dev
, i
, 0);
308 static void pci_do_device_reset(PCIDevice
*dev
)
312 pci_device_deassert_intx(dev
);
313 assert(dev
->irq_state
== 0);
315 /* Clear all writable bits */
316 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
317 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
318 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
319 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
320 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
321 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
322 /* Some devices make bits of PCI_INTERRUPT_LINE read only */
323 pci_byte_test_and_clear_mask(dev
->config
+ PCI_INTERRUPT_LINE
,
324 pci_get_word(dev
->wmask
+ PCI_INTERRUPT_LINE
) |
325 pci_get_word(dev
->w1cmask
+ PCI_INTERRUPT_LINE
));
326 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
327 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
328 PCIIORegion
*region
= &dev
->io_regions
[r
];
333 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
334 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
335 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
337 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
340 pci_update_mappings(dev
);
347 * This function is called on #RST and FLR.
348 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
350 void pci_device_reset(PCIDevice
*dev
)
352 qdev_reset_all(&dev
->qdev
);
353 pci_do_device_reset(dev
);
357 * Trigger pci bus reset under a given bus.
358 * Called via qbus_reset_all on RST# assert, after the devices
359 * have been reset qdev_reset_all-ed already.
361 static void pcibus_reset(BusState
*qbus
)
363 PCIBus
*bus
= DO_UPCAST(PCIBus
, qbus
, qbus
);
366 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
367 if (bus
->devices
[i
]) {
368 pci_do_device_reset(bus
->devices
[i
]);
372 for (i
= 0; i
< bus
->nirq
; i
++) {
373 assert(bus
->irq_count
[i
] == 0);
377 static void pci_host_bus_register(DeviceState
*host
)
379 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
381 QLIST_INSERT_HEAD(&pci_host_bridges
, host_bridge
, next
);
384 static void pci_host_bus_unregister(DeviceState
*host
)
386 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
388 QLIST_REMOVE(host_bridge
, next
);
391 PCIBus
*pci_device_root_bus(const PCIDevice
*d
)
393 PCIBus
*bus
= pci_get_bus(d
);
395 while (!pci_bus_is_root(bus
)) {
399 bus
= pci_get_bus(d
);
405 const char *pci_root_bus_path(PCIDevice
*dev
)
407 PCIBus
*rootbus
= pci_device_root_bus(dev
);
408 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(rootbus
->qbus
.parent
);
409 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_GET_CLASS(host_bridge
);
411 assert(host_bridge
->bus
== rootbus
);
413 if (hc
->root_bus_path
) {
414 return (*hc
->root_bus_path
)(host_bridge
, rootbus
);
417 return rootbus
->qbus
.name
;
420 static void pci_root_bus_init(PCIBus
*bus
, DeviceState
*parent
,
421 MemoryRegion
*address_space_mem
,
422 MemoryRegion
*address_space_io
,
425 assert(PCI_FUNC(devfn_min
) == 0);
426 bus
->devfn_min
= devfn_min
;
427 bus
->slot_reserved_mask
= 0x0;
428 bus
->address_space_mem
= address_space_mem
;
429 bus
->address_space_io
= address_space_io
;
430 bus
->flags
|= PCI_BUS_IS_ROOT
;
433 QLIST_INIT(&bus
->child
);
435 pci_host_bus_register(parent
);
438 static void pci_bus_uninit(PCIBus
*bus
)
440 pci_host_bus_unregister(BUS(bus
)->parent
);
443 bool pci_bus_is_express(PCIBus
*bus
)
445 return object_dynamic_cast(OBJECT(bus
), TYPE_PCIE_BUS
);
448 void pci_root_bus_new_inplace(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
450 MemoryRegion
*address_space_mem
,
451 MemoryRegion
*address_space_io
,
452 uint8_t devfn_min
, const char *typename
)
454 qbus_create_inplace(bus
, bus_size
, typename
, parent
, name
);
455 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
459 PCIBus
*pci_root_bus_new(DeviceState
*parent
, const char *name
,
460 MemoryRegion
*address_space_mem
,
461 MemoryRegion
*address_space_io
,
462 uint8_t devfn_min
, const char *typename
)
466 bus
= PCI_BUS(qbus_create(typename
, parent
, name
));
467 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
472 void pci_root_bus_cleanup(PCIBus
*bus
)
475 /* the caller of the unplug hotplug handler will delete this device */
476 qbus_unrealize(BUS(bus
));
479 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
480 void *irq_opaque
, int nirq
)
482 bus
->set_irq
= set_irq
;
483 bus
->map_irq
= map_irq
;
484 bus
->irq_opaque
= irq_opaque
;
486 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
489 void pci_bus_irqs_cleanup(PCIBus
*bus
)
493 bus
->irq_opaque
= NULL
;
495 g_free(bus
->irq_count
);
498 PCIBus
*pci_register_root_bus(DeviceState
*parent
, const char *name
,
499 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
501 MemoryRegion
*address_space_mem
,
502 MemoryRegion
*address_space_io
,
503 uint8_t devfn_min
, int nirq
,
504 const char *typename
)
508 bus
= pci_root_bus_new(parent
, name
, address_space_mem
,
509 address_space_io
, devfn_min
, typename
);
510 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
514 void pci_unregister_root_bus(PCIBus
*bus
)
516 pci_bus_irqs_cleanup(bus
);
517 pci_root_bus_cleanup(bus
);
520 int pci_bus_num(PCIBus
*s
)
522 return PCI_BUS_GET_CLASS(s
)->bus_num(s
);
525 int pci_bus_numa_node(PCIBus
*bus
)
527 return PCI_BUS_GET_CLASS(bus
)->numa_node(bus
);
530 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
531 const VMStateField
*field
)
533 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
534 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(s
);
538 assert(size
== pci_config_size(s
));
539 config
= g_malloc(size
);
541 qemu_get_buffer(f
, config
, size
);
542 for (i
= 0; i
< size
; ++i
) {
543 if ((config
[i
] ^ s
->config
[i
]) &
544 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
545 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
546 "cmask: %x wmask: %x w1cmask:%x", __func__
,
547 i
, config
[i
], s
->config
[i
],
548 s
->cmask
[i
], s
->wmask
[i
], s
->w1cmask
[i
]);
553 memcpy(s
->config
, config
, size
);
555 pci_update_mappings(s
);
557 PCIBridge
*b
= PCI_BRIDGE(s
);
558 pci_bridge_update_mappings(b
);
561 memory_region_set_enabled(&s
->bus_master_enable_region
,
562 pci_get_word(s
->config
+ PCI_COMMAND
)
563 & PCI_COMMAND_MASTER
);
569 /* just put buffer */
570 static int put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
571 const VMStateField
*field
, JSONWriter
*vmdesc
)
573 const uint8_t **v
= pv
;
574 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
575 qemu_put_buffer(f
, *v
, size
);
580 static VMStateInfo vmstate_info_pci_config
= {
581 .name
= "pci config",
582 .get
= get_pci_config_device
,
583 .put
= put_pci_config_device
,
586 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
587 const VMStateField
*field
)
589 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
590 uint32_t irq_state
[PCI_NUM_PINS
];
592 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
593 irq_state
[i
] = qemu_get_be32(f
);
594 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
595 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
601 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
602 pci_set_irq_state(s
, i
, irq_state
[i
]);
608 static int put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
609 const VMStateField
*field
, JSONWriter
*vmdesc
)
612 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
614 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
615 qemu_put_be32(f
, pci_irq_state(s
, i
));
621 static VMStateInfo vmstate_info_pci_irq_state
= {
622 .name
= "pci irq state",
623 .get
= get_pci_irq_state
,
624 .put
= put_pci_irq_state
,
627 static bool migrate_is_pcie(void *opaque
, int version_id
)
629 return pci_is_express((PCIDevice
*)opaque
);
632 static bool migrate_is_not_pcie(void *opaque
, int version_id
)
634 return !pci_is_express((PCIDevice
*)opaque
);
637 const VMStateDescription vmstate_pci_device
= {
640 .minimum_version_id
= 1,
641 .fields
= (VMStateField
[]) {
642 VMSTATE_INT32_POSITIVE_LE(version_id
, PCIDevice
),
643 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
645 0, vmstate_info_pci_config
,
646 PCI_CONFIG_SPACE_SIZE
),
647 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
649 0, vmstate_info_pci_config
,
650 PCIE_CONFIG_SPACE_SIZE
),
651 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
652 vmstate_info_pci_irq_state
,
653 PCI_NUM_PINS
* sizeof(int32_t)),
654 VMSTATE_END_OF_LIST()
659 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
661 /* Clear interrupt status bit: it is implicit
662 * in irq_state which we are saving.
663 * This makes us compatible with old devices
664 * which never set or clear this bit. */
665 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
666 vmstate_save_state(f
, &vmstate_pci_device
, s
, NULL
);
667 /* Restore the interrupt status bit. */
668 pci_update_irq_status(s
);
671 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
674 ret
= vmstate_load_state(f
, &vmstate_pci_device
, s
, s
->version_id
);
675 /* Restore the interrupt status bit. */
676 pci_update_irq_status(s
);
680 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
682 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
683 pci_default_sub_vendor_id
);
684 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
685 pci_default_sub_device_id
);
689 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
690 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
692 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
693 unsigned int *slotp
, unsigned int *funcp
)
698 unsigned long dom
= 0, bus
= 0;
699 unsigned int slot
= 0;
700 unsigned int func
= 0;
703 val
= strtoul(p
, &e
, 16);
709 val
= strtoul(p
, &e
, 16);
716 val
= strtoul(p
, &e
, 16);
729 val
= strtoul(p
, &e
, 16);
736 /* if funcp == NULL func is 0 */
737 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
751 static void pci_init_cmask(PCIDevice
*dev
)
753 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
754 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
755 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
756 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
757 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
758 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
759 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
760 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
763 static void pci_init_wmask(PCIDevice
*dev
)
765 int config_size
= pci_config_size(dev
);
767 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
768 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
769 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
770 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
771 PCI_COMMAND_INTX_DISABLE
);
772 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
774 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
775 config_size
- PCI_CONFIG_HEADER_SIZE
);
778 static void pci_init_w1cmask(PCIDevice
*dev
)
781 * Note: It's okay to set w1cmask even for readonly bits as
782 * long as their value is hardwired to 0.
784 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
785 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
786 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
787 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
790 static void pci_init_mask_bridge(PCIDevice
*d
)
792 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
793 PCI_SEC_LETENCY_TIMER */
794 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
797 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
798 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
799 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
800 PCI_MEMORY_RANGE_MASK
& 0xffff);
801 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
802 PCI_MEMORY_RANGE_MASK
& 0xffff);
803 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
804 PCI_PREF_RANGE_MASK
& 0xffff);
805 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
806 PCI_PREF_RANGE_MASK
& 0xffff);
808 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
809 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
811 /* Supported memory and i/o types */
812 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
813 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
814 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
815 PCI_PREF_RANGE_TYPE_64
);
816 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
817 PCI_PREF_RANGE_TYPE_64
);
820 * TODO: Bridges default to 10-bit VGA decoding but we currently only
821 * implement 16-bit decoding (no alias support).
823 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
824 PCI_BRIDGE_CTL_PARITY
|
825 PCI_BRIDGE_CTL_SERR
|
828 PCI_BRIDGE_CTL_VGA_16BIT
|
829 PCI_BRIDGE_CTL_MASTER_ABORT
|
830 PCI_BRIDGE_CTL_BUS_RESET
|
831 PCI_BRIDGE_CTL_FAST_BACK
|
832 PCI_BRIDGE_CTL_DISCARD
|
833 PCI_BRIDGE_CTL_SEC_DISCARD
|
834 PCI_BRIDGE_CTL_DISCARD_SERR
);
835 /* Below does not do anything as we never set this bit, put here for
837 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
838 PCI_BRIDGE_CTL_DISCARD_STATUS
);
839 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
840 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
841 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
842 PCI_PREF_RANGE_TYPE_MASK
);
843 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
844 PCI_PREF_RANGE_TYPE_MASK
);
847 static void pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
, Error
**errp
)
849 uint8_t slot
= PCI_SLOT(dev
->devfn
);
852 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
853 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
857 * multifunction bit is interpreted in two ways as follows.
858 * - all functions must set the bit to 1.
860 * - function 0 must set the bit, but the rest function (> 0)
861 * is allowed to leave the bit to 0.
862 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
864 * So OS (at least Linux) checks the bit of only function 0,
865 * and doesn't see the bit of function > 0.
867 * The below check allows both interpretation.
869 if (PCI_FUNC(dev
->devfn
)) {
870 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
871 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
872 /* function 0 should set multifunction bit */
873 error_setg(errp
, "PCI: single function device can't be populated "
874 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
880 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
883 /* function 0 indicates single function, so function > 0 must be NULL */
884 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
885 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
886 error_setg(errp
, "PCI: %x.0 indicates single function, "
887 "but %x.%x is already populated.",
894 static void pci_config_alloc(PCIDevice
*pci_dev
)
896 int config_size
= pci_config_size(pci_dev
);
898 pci_dev
->config
= g_malloc0(config_size
);
899 pci_dev
->cmask
= g_malloc0(config_size
);
900 pci_dev
->wmask
= g_malloc0(config_size
);
901 pci_dev
->w1cmask
= g_malloc0(config_size
);
902 pci_dev
->used
= g_malloc0(config_size
);
905 static void pci_config_free(PCIDevice
*pci_dev
)
907 g_free(pci_dev
->config
);
908 g_free(pci_dev
->cmask
);
909 g_free(pci_dev
->wmask
);
910 g_free(pci_dev
->w1cmask
);
911 g_free(pci_dev
->used
);
914 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
916 pci_get_bus(pci_dev
)->devices
[pci_dev
->devfn
] = NULL
;
917 pci_config_free(pci_dev
);
919 if (memory_region_is_mapped(&pci_dev
->bus_master_enable_region
)) {
920 memory_region_del_subregion(&pci_dev
->bus_master_container_region
,
921 &pci_dev
->bus_master_enable_region
);
923 address_space_destroy(&pci_dev
->bus_master_as
);
926 /* Extract PCIReqIDCache into BDF format */
927 static uint16_t pci_req_id_cache_extract(PCIReqIDCache
*cache
)
932 switch (cache
->type
) {
934 result
= pci_get_bdf(cache
->dev
);
936 case PCI_REQ_ID_SECONDARY_BUS
:
937 bus_n
= pci_dev_bus_num(cache
->dev
);
938 result
= PCI_BUILD_BDF(bus_n
, 0);
941 error_report("Invalid PCI requester ID cache type: %d",
950 /* Parse bridges up to the root complex and return requester ID
951 * cache for specific device. For full PCIe topology, the cache
952 * result would be exactly the same as getting BDF of the device.
953 * However, several tricks are required when system mixed up with
954 * legacy PCI devices and PCIe-to-PCI bridges.
956 * Here we cache the proxy device (and type) not requester ID since
957 * bus number might change from time to time.
959 static PCIReqIDCache
pci_req_id_cache_get(PCIDevice
*dev
)
962 PCIReqIDCache cache
= {
964 .type
= PCI_REQ_ID_BDF
,
967 while (!pci_bus_is_root(pci_get_bus(dev
))) {
968 /* We are under PCI/PCIe bridges */
969 parent
= pci_get_bus(dev
)->parent_dev
;
970 if (pci_is_express(parent
)) {
971 if (pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
972 /* When we pass through PCIe-to-PCI/PCIX bridges, we
973 * override the requester ID using secondary bus
974 * number of parent bridge with zeroed devfn
975 * (pcie-to-pci bridge spec chap 2.3). */
976 cache
.type
= PCI_REQ_ID_SECONDARY_BUS
;
980 /* Legacy PCI, override requester ID with the bridge's
981 * BDF upstream. When the root complex connects to
982 * legacy PCI devices (including buses), it can only
983 * obtain requester ID info from directly attached
984 * devices. If devices are attached under bridges, only
985 * the requester ID of the bridge that is directly
986 * attached to the root complex can be recognized. */
987 cache
.type
= PCI_REQ_ID_BDF
;
996 uint16_t pci_requester_id(PCIDevice
*dev
)
998 return pci_req_id_cache_extract(&dev
->requester_id_cache
);
1001 static bool pci_bus_devfn_available(PCIBus
*bus
, int devfn
)
1003 return !(bus
->devices
[devfn
]);
1006 static bool pci_bus_devfn_reserved(PCIBus
*bus
, int devfn
)
1008 return bus
->slot_reserved_mask
& (1UL << PCI_SLOT(devfn
));
1011 /* -1 for devfn means auto assign */
1012 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
,
1013 const char *name
, int devfn
,
1016 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1017 PCIConfigReadFunc
*config_read
= pc
->config_read
;
1018 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
1019 Error
*local_err
= NULL
;
1020 DeviceState
*dev
= DEVICE(pci_dev
);
1021 PCIBus
*bus
= pci_get_bus(pci_dev
);
1023 /* Only pci bridges can be attached to extra PCI root buses */
1024 if (pci_bus_is_root(bus
) && bus
->parent_dev
&& !pc
->is_bridge
) {
1026 "PCI: Only PCI/PCIe bridges can be plugged into %s",
1027 bus
->parent_dev
->name
);
1032 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
1033 devfn
+= PCI_FUNC_MAX
) {
1034 if (pci_bus_devfn_available(bus
, devfn
) &&
1035 !pci_bus_devfn_reserved(bus
, devfn
)) {
1039 error_setg(errp
, "PCI: no slot/function available for %s, all in use "
1040 "or reserved", name
);
1043 } else if (pci_bus_devfn_reserved(bus
, devfn
)) {
1044 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1046 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
);
1048 } else if (!pci_bus_devfn_available(bus
, devfn
)) {
1049 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1051 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
,
1052 bus
->devices
[devfn
]->name
);
1054 } else if (dev
->hotplugged
&&
1055 pci_get_function_0(pci_dev
)) {
1056 error_setg(errp
, "PCI: slot %d function 0 already occupied by %s,"
1057 " new func %s cannot be exposed to guest.",
1058 PCI_SLOT(pci_get_function_0(pci_dev
)->devfn
),
1059 pci_get_function_0(pci_dev
)->name
,
1065 pci_dev
->devfn
= devfn
;
1066 pci_dev
->requester_id_cache
= pci_req_id_cache_get(pci_dev
);
1067 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
1069 memory_region_init(&pci_dev
->bus_master_container_region
, OBJECT(pci_dev
),
1070 "bus master container", UINT64_MAX
);
1071 address_space_init(&pci_dev
->bus_master_as
,
1072 &pci_dev
->bus_master_container_region
, pci_dev
->name
);
1074 if (phase_check(PHASE_MACHINE_READY
)) {
1075 pci_init_bus_master(pci_dev
);
1077 pci_dev
->irq_state
= 0;
1078 pci_config_alloc(pci_dev
);
1080 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
1081 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
1082 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
1083 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
1085 if (!pc
->is_bridge
) {
1086 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
1087 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
1088 pc
->subsystem_vendor_id
);
1089 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
1092 pci_set_default_subsystem_id(pci_dev
);
1095 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1096 assert(!pc
->subsystem_vendor_id
);
1097 assert(!pc
->subsystem_id
);
1099 pci_init_cmask(pci_dev
);
1100 pci_init_wmask(pci_dev
);
1101 pci_init_w1cmask(pci_dev
);
1102 if (pc
->is_bridge
) {
1103 pci_init_mask_bridge(pci_dev
);
1105 pci_init_multifunction(bus
, pci_dev
, &local_err
);
1107 error_propagate(errp
, local_err
);
1108 do_pci_unregister_device(pci_dev
);
1113 config_read
= pci_default_read_config
;
1115 config_write
= pci_default_write_config
;
1116 pci_dev
->config_read
= config_read
;
1117 pci_dev
->config_write
= config_write
;
1118 bus
->devices
[devfn
] = pci_dev
;
1119 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
1123 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
1128 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1129 r
= &pci_dev
->io_regions
[i
];
1130 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
1132 memory_region_del_subregion(r
->address_space
, r
->memory
);
1135 pci_unregister_vga(pci_dev
);
1138 static void pci_qdev_unrealize(DeviceState
*dev
)
1140 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
1141 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1143 pci_unregister_io_regions(pci_dev
);
1144 pci_del_option_rom(pci_dev
);
1150 pci_device_deassert_intx(pci_dev
);
1151 do_pci_unregister_device(pci_dev
);
1154 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
1155 uint8_t type
, MemoryRegion
*memory
)
1158 uint32_t addr
; /* offset in pci config space */
1160 pcibus_t size
= memory_region_size(memory
);
1163 assert(region_num
>= 0);
1164 assert(region_num
< PCI_NUM_REGIONS
);
1165 assert(is_power_of_2(size
));
1167 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */
1169 pci_dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1170 assert(hdr_type
!= PCI_HEADER_TYPE_BRIDGE
|| region_num
< 2);
1172 r
= &pci_dev
->io_regions
[region_num
];
1173 r
->addr
= PCI_BAR_UNMAPPED
;
1177 r
->address_space
= type
& PCI_BASE_ADDRESS_SPACE_IO
1178 ? pci_get_bus(pci_dev
)->address_space_io
1179 : pci_get_bus(pci_dev
)->address_space_mem
;
1181 wmask
= ~(size
- 1);
1182 if (region_num
== PCI_ROM_SLOT
) {
1183 /* ROM enable bit is writable */
1184 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
1187 addr
= pci_bar(pci_dev
, region_num
);
1188 pci_set_long(pci_dev
->config
+ addr
, type
);
1190 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
1191 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1192 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
1193 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
1195 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
1196 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
1200 static void pci_update_vga(PCIDevice
*pci_dev
)
1204 if (!pci_dev
->has_vga
) {
1208 cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
1210 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
],
1211 cmd
& PCI_COMMAND_MEMORY
);
1212 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
],
1213 cmd
& PCI_COMMAND_IO
);
1214 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
],
1215 cmd
& PCI_COMMAND_IO
);
1218 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
1219 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
)
1221 PCIBus
*bus
= pci_get_bus(pci_dev
);
1223 assert(!pci_dev
->has_vga
);
1225 assert(memory_region_size(mem
) == QEMU_PCI_VGA_MEM_SIZE
);
1226 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
] = mem
;
1227 memory_region_add_subregion_overlap(bus
->address_space_mem
,
1228 QEMU_PCI_VGA_MEM_BASE
, mem
, 1);
1230 assert(memory_region_size(io_lo
) == QEMU_PCI_VGA_IO_LO_SIZE
);
1231 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
] = io_lo
;
1232 memory_region_add_subregion_overlap(bus
->address_space_io
,
1233 QEMU_PCI_VGA_IO_LO_BASE
, io_lo
, 1);
1235 assert(memory_region_size(io_hi
) == QEMU_PCI_VGA_IO_HI_SIZE
);
1236 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
] = io_hi
;
1237 memory_region_add_subregion_overlap(bus
->address_space_io
,
1238 QEMU_PCI_VGA_IO_HI_BASE
, io_hi
, 1);
1239 pci_dev
->has_vga
= true;
1241 pci_update_vga(pci_dev
);
1244 void pci_unregister_vga(PCIDevice
*pci_dev
)
1246 PCIBus
*bus
= pci_get_bus(pci_dev
);
1248 if (!pci_dev
->has_vga
) {
1252 memory_region_del_subregion(bus
->address_space_mem
,
1253 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
]);
1254 memory_region_del_subregion(bus
->address_space_io
,
1255 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
]);
1256 memory_region_del_subregion(bus
->address_space_io
,
1257 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
]);
1258 pci_dev
->has_vga
= false;
1261 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
1263 return pci_dev
->io_regions
[region_num
].addr
;
1266 static pcibus_t
pci_bar_address(PCIDevice
*d
,
1267 int reg
, uint8_t type
, pcibus_t size
)
1269 pcibus_t new_addr
, last_addr
;
1270 int bar
= pci_bar(d
, reg
);
1271 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1272 Object
*machine
= qdev_get_machine();
1273 ObjectClass
*oc
= object_get_class(machine
);
1274 MachineClass
*mc
= MACHINE_CLASS(oc
);
1275 bool allow_0_address
= mc
->pci_allow_0_address
;
1277 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1278 if (!(cmd
& PCI_COMMAND_IO
)) {
1279 return PCI_BAR_UNMAPPED
;
1281 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
1282 last_addr
= new_addr
+ size
- 1;
1283 /* Check if 32 bit BAR wraps around explicitly.
1284 * TODO: make priorities correct and remove this work around.
1286 if (last_addr
<= new_addr
|| last_addr
>= UINT32_MAX
||
1287 (!allow_0_address
&& new_addr
== 0)) {
1288 return PCI_BAR_UNMAPPED
;
1293 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1294 return PCI_BAR_UNMAPPED
;
1296 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1297 new_addr
= pci_get_quad(d
->config
+ bar
);
1299 new_addr
= pci_get_long(d
->config
+ bar
);
1301 /* the ROM slot has a specific enable bit */
1302 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1303 return PCI_BAR_UNMAPPED
;
1305 new_addr
&= ~(size
- 1);
1306 last_addr
= new_addr
+ size
- 1;
1307 /* NOTE: we do not support wrapping */
1308 /* XXX: as we cannot support really dynamic
1309 mappings, we handle specific values as invalid
1311 if (last_addr
<= new_addr
|| last_addr
== PCI_BAR_UNMAPPED
||
1312 (!allow_0_address
&& new_addr
== 0)) {
1313 return PCI_BAR_UNMAPPED
;
1316 /* Now pcibus_t is 64bit.
1317 * Check if 32 bit BAR wraps around explicitly.
1318 * Without this, PC ide doesn't work well.
1319 * TODO: remove this work around.
1321 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1322 return PCI_BAR_UNMAPPED
;
1326 * OS is allowed to set BAR beyond its addressable
1327 * bits. For example, 32 bit OS can set 64bit bar
1328 * to >4G. Check it. TODO: we might need to support
1329 * it in the future for e.g. PAE.
1331 if (last_addr
>= HWADDR_MAX
) {
1332 return PCI_BAR_UNMAPPED
;
1338 static void pci_update_mappings(PCIDevice
*d
)
1344 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1345 r
= &d
->io_regions
[i
];
1347 /* this region isn't registered */
1351 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1353 /* This bar isn't changed */
1354 if (new_addr
== r
->addr
)
1357 /* now do the real mapping */
1358 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1359 trace_pci_update_mappings_del(d
, pci_dev_bus_num(d
),
1362 i
, r
->addr
, r
->size
);
1363 memory_region_del_subregion(r
->address_space
, r
->memory
);
1366 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1367 trace_pci_update_mappings_add(d
, pci_dev_bus_num(d
),
1370 i
, r
->addr
, r
->size
);
1371 memory_region_add_subregion_overlap(r
->address_space
,
1372 r
->addr
, r
->memory
, 1);
1379 static inline int pci_irq_disabled(PCIDevice
*d
)
1381 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1384 /* Called after interrupt disabled field update in config space,
1385 * assert/deassert interrupts if necessary.
1386 * Gets original interrupt disable bit value (before update). */
1387 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1389 int i
, disabled
= pci_irq_disabled(d
);
1390 if (disabled
== was_irq_disabled
)
1392 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1393 int state
= pci_irq_state(d
, i
);
1394 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1398 uint32_t pci_default_read_config(PCIDevice
*d
,
1399 uint32_t address
, int len
)
1403 assert(address
+ len
<= pci_config_size(d
));
1405 if (pci_is_express_downstream_port(d
) &&
1406 ranges_overlap(address
, len
, d
->exp
.exp_cap
+ PCI_EXP_LNKSTA
, 2)) {
1407 pcie_sync_bridge_lnk(d
);
1409 memcpy(&val
, d
->config
+ address
, len
);
1410 return le32_to_cpu(val
);
1413 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val_in
, int l
)
1415 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1416 uint32_t val
= val_in
;
1418 assert(addr
+ l
<= pci_config_size(d
));
1420 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1421 uint8_t wmask
= d
->wmask
[addr
+ i
];
1422 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1423 assert(!(wmask
& w1cmask
));
1424 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1425 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1427 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1428 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1429 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1430 range_covers_byte(addr
, l
, PCI_COMMAND
))
1431 pci_update_mappings(d
);
1433 if (range_covers_byte(addr
, l
, PCI_COMMAND
)) {
1434 pci_update_irq_disabled(d
, was_irq_disabled
);
1435 memory_region_set_enabled(&d
->bus_master_enable_region
,
1436 pci_get_word(d
->config
+ PCI_COMMAND
)
1437 & PCI_COMMAND_MASTER
);
1440 msi_write_config(d
, addr
, val_in
, l
);
1441 msix_write_config(d
, addr
, val_in
, l
);
1444 /***********************************************************/
1445 /* generic PCI irq support */
1447 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1448 static void pci_irq_handler(void *opaque
, int irq_num
, int level
)
1450 PCIDevice
*pci_dev
= opaque
;
1453 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1457 pci_set_irq_state(pci_dev
, irq_num
, level
);
1458 pci_update_irq_status(pci_dev
);
1459 if (pci_irq_disabled(pci_dev
))
1461 pci_change_irq_level(pci_dev
, irq_num
, change
);
1464 static inline int pci_intx(PCIDevice
*pci_dev
)
1466 return pci_get_byte(pci_dev
->config
+ PCI_INTERRUPT_PIN
) - 1;
1469 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
)
1471 int intx
= pci_intx(pci_dev
);
1473 return qemu_allocate_irq(pci_irq_handler
, pci_dev
, intx
);
1476 void pci_set_irq(PCIDevice
*pci_dev
, int level
)
1478 int intx
= pci_intx(pci_dev
);
1479 pci_irq_handler(pci_dev
, intx
, level
);
1482 /* Special hooks used by device assignment */
1483 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1485 assert(pci_bus_is_root(bus
));
1486 bus
->route_intx_to_irq
= route_intx_to_irq
;
1489 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1494 bus
= pci_get_bus(dev
);
1495 pin
= bus
->map_irq(dev
, pin
);
1496 dev
= bus
->parent_dev
;
1499 if (!bus
->route_intx_to_irq
) {
1500 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1501 object_get_typename(OBJECT(bus
->qbus
.parent
)));
1502 return (PCIINTxRoute
) { PCI_INTX_DISABLED
, -1 };
1505 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1508 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new)
1510 return old
->mode
!= new->mode
|| old
->irq
!= new->irq
;
1513 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1519 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1520 dev
= bus
->devices
[i
];
1521 if (dev
&& dev
->intx_routing_notifier
) {
1522 dev
->intx_routing_notifier(dev
);
1526 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1527 pci_bus_fire_intx_routing_notifier(sec
);
1531 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1532 PCIINTxRoutingNotifier notifier
)
1534 dev
->intx_routing_notifier
= notifier
;
1538 * PCI-to-PCI bridge specification
1539 * 9.1: Interrupt routing. Table 9-1
1541 * the PCI Express Base Specification, Revision 2.1
1542 * 2.2.8.1: INTx interrutp signaling - Rules
1543 * the Implementation Note
1547 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1548 * 0-origin unlike PCI interrupt pin register.
1550 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
)
1552 return pci_swizzle(PCI_SLOT(pci_dev
->devfn
), pin
);
1555 /***********************************************************/
1556 /* monitor info on PCI */
1561 const char *fw_name
;
1562 uint16_t fw_ign_bits
;
1565 static const pci_class_desc pci_class_descriptions
[] =
1567 { 0x0001, "VGA controller", "display"},
1568 { 0x0100, "SCSI controller", "scsi"},
1569 { 0x0101, "IDE controller", "ide"},
1570 { 0x0102, "Floppy controller", "fdc"},
1571 { 0x0103, "IPI controller", "ipi"},
1572 { 0x0104, "RAID controller", "raid"},
1573 { 0x0106, "SATA controller"},
1574 { 0x0107, "SAS controller"},
1575 { 0x0180, "Storage controller"},
1576 { 0x0200, "Ethernet controller", "ethernet"},
1577 { 0x0201, "Token Ring controller", "token-ring"},
1578 { 0x0202, "FDDI controller", "fddi"},
1579 { 0x0203, "ATM controller", "atm"},
1580 { 0x0280, "Network controller"},
1581 { 0x0300, "VGA controller", "display", 0x00ff},
1582 { 0x0301, "XGA controller"},
1583 { 0x0302, "3D controller"},
1584 { 0x0380, "Display controller"},
1585 { 0x0400, "Video controller", "video"},
1586 { 0x0401, "Audio controller", "sound"},
1588 { 0x0403, "Audio controller", "sound"},
1589 { 0x0480, "Multimedia controller"},
1590 { 0x0500, "RAM controller", "memory"},
1591 { 0x0501, "Flash controller", "flash"},
1592 { 0x0580, "Memory controller"},
1593 { 0x0600, "Host bridge", "host"},
1594 { 0x0601, "ISA bridge", "isa"},
1595 { 0x0602, "EISA bridge", "eisa"},
1596 { 0x0603, "MC bridge", "mca"},
1597 { 0x0604, "PCI bridge", "pci-bridge"},
1598 { 0x0605, "PCMCIA bridge", "pcmcia"},
1599 { 0x0606, "NUBUS bridge", "nubus"},
1600 { 0x0607, "CARDBUS bridge", "cardbus"},
1601 { 0x0608, "RACEWAY bridge"},
1602 { 0x0680, "Bridge"},
1603 { 0x0700, "Serial port", "serial"},
1604 { 0x0701, "Parallel port", "parallel"},
1605 { 0x0800, "Interrupt controller", "interrupt-controller"},
1606 { 0x0801, "DMA controller", "dma-controller"},
1607 { 0x0802, "Timer", "timer"},
1608 { 0x0803, "RTC", "rtc"},
1609 { 0x0900, "Keyboard", "keyboard"},
1610 { 0x0901, "Pen", "pen"},
1611 { 0x0902, "Mouse", "mouse"},
1612 { 0x0A00, "Dock station", "dock", 0x00ff},
1613 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1614 { 0x0c00, "Fireware contorller", "fireware"},
1615 { 0x0c01, "Access bus controller", "access-bus"},
1616 { 0x0c02, "SSA controller", "ssa"},
1617 { 0x0c03, "USB controller", "usb"},
1618 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1623 static void pci_for_each_device_under_bus_reverse(PCIBus
*bus
,
1624 void (*fn
)(PCIBus
*b
,
1632 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1633 d
= bus
->devices
[ARRAY_SIZE(bus
->devices
) - 1 - devfn
];
1640 void pci_for_each_device_reverse(PCIBus
*bus
, int bus_num
,
1641 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1644 bus
= pci_find_bus_nr(bus
, bus_num
);
1647 pci_for_each_device_under_bus_reverse(bus
, fn
, opaque
);
1651 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1652 void (*fn
)(PCIBus
*b
, PCIDevice
*d
,
1659 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1660 d
= bus
->devices
[devfn
];
1667 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1668 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1671 bus
= pci_find_bus_nr(bus
, bus_num
);
1674 pci_for_each_device_under_bus(bus
, fn
, opaque
);
1678 static const pci_class_desc
*get_class_desc(int class)
1680 const pci_class_desc
*desc
;
1682 desc
= pci_class_descriptions
;
1683 while (desc
->desc
&& class != desc
->class) {
1690 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1692 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1694 PciMemoryRegionList
*head
= NULL
, **tail
= &head
;
1697 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1698 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1699 PciMemoryRegion
*region
;
1705 region
= g_malloc0(sizeof(*region
));
1707 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1708 region
->type
= g_strdup("io");
1710 region
->type
= g_strdup("memory");
1711 region
->has_prefetch
= true;
1712 region
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1713 region
->has_mem_type_64
= true;
1714 region
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1718 region
->address
= r
->addr
;
1719 region
->size
= r
->size
;
1721 QAPI_LIST_APPEND(tail
, region
);
1727 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1730 PciBridgeInfo
*info
;
1731 PciMemoryRange
*range
;
1733 info
= g_new0(PciBridgeInfo
, 1);
1735 info
->bus
= g_new0(PciBusInfo
, 1);
1736 info
->bus
->number
= dev
->config
[PCI_PRIMARY_BUS
];
1737 info
->bus
->secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1738 info
->bus
->subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1740 range
= info
->bus
->io_range
= g_new0(PciMemoryRange
, 1);
1741 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1742 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1744 range
= info
->bus
->memory_range
= g_new0(PciMemoryRange
, 1);
1745 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1746 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1748 range
= info
->bus
->prefetchable_range
= g_new0(PciMemoryRange
, 1);
1749 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1750 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1752 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1753 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1755 info
->has_devices
= true;
1756 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1763 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1766 const pci_class_desc
*desc
;
1767 PciDeviceInfo
*info
;
1771 info
= g_new0(PciDeviceInfo
, 1);
1772 info
->bus
= bus_num
;
1773 info
->slot
= PCI_SLOT(dev
->devfn
);
1774 info
->function
= PCI_FUNC(dev
->devfn
);
1776 info
->class_info
= g_new0(PciDeviceClass
, 1);
1777 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1778 info
->class_info
->q_class
= class;
1779 desc
= get_class_desc(class);
1781 info
->class_info
->has_desc
= true;
1782 info
->class_info
->desc
= g_strdup(desc
->desc
);
1785 info
->id
= g_new0(PciDeviceId
, 1);
1786 info
->id
->vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1787 info
->id
->device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1788 info
->regions
= qmp_query_pci_regions(dev
);
1789 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1791 info
->irq_pin
= dev
->config
[PCI_INTERRUPT_PIN
];
1792 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1793 info
->has_irq
= true;
1794 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1797 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1798 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1799 info
->has_pci_bridge
= true;
1800 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1801 } else if (type
== PCI_HEADER_TYPE_NORMAL
) {
1802 info
->id
->has_subsystem
= info
->id
->has_subsystem_vendor
= true;
1803 info
->id
->subsystem
= pci_get_word(dev
->config
+ PCI_SUBSYSTEM_ID
);
1804 info
->id
->subsystem_vendor
=
1805 pci_get_word(dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
);
1806 } else if (type
== PCI_HEADER_TYPE_CARDBUS
) {
1807 info
->id
->has_subsystem
= info
->id
->has_subsystem_vendor
= true;
1808 info
->id
->subsystem
= pci_get_word(dev
->config
+ PCI_CB_SUBSYSTEM_ID
);
1809 info
->id
->subsystem_vendor
=
1810 pci_get_word(dev
->config
+ PCI_CB_SUBSYSTEM_VENDOR_ID
);
1816 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1818 PciDeviceInfoList
*head
= NULL
, **tail
= &head
;
1822 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1823 dev
= bus
->devices
[devfn
];
1825 QAPI_LIST_APPEND(tail
, qmp_query_pci_device(dev
, bus
, bus_num
));
1832 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1834 PciInfo
*info
= NULL
;
1836 bus
= pci_find_bus_nr(bus
, bus_num
);
1838 info
= g_malloc0(sizeof(*info
));
1839 info
->bus
= bus_num
;
1840 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1846 PciInfoList
*qmp_query_pci(Error
**errp
)
1848 PciInfoList
*head
= NULL
, **tail
= &head
;
1849 PCIHostState
*host_bridge
;
1851 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
1852 QAPI_LIST_APPEND(tail
,
1853 qmp_query_pci_bus(host_bridge
->bus
,
1854 pci_bus_num(host_bridge
->bus
)));
1860 /* Initialize a PCI NIC. */
1861 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
1862 const char *default_model
,
1863 const char *default_devaddr
)
1865 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1867 GPtrArray
*pci_nic_models
;
1876 if (nd
->model
&& !strcmp(nd
->model
, "virtio")) {
1878 nd
->model
= g_strdup("virtio-net-pci");
1881 list
= object_class_get_list_sorted(TYPE_PCI_DEVICE
, false);
1882 pci_nic_models
= g_ptr_array_new();
1884 DeviceClass
*dc
= OBJECT_CLASS_CHECK(DeviceClass
, list
->data
,
1887 if (test_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
) &&
1888 dc
->user_creatable
) {
1889 const char *name
= object_class_get_name(list
->data
);
1891 * A network device might also be something else than a NIC, see
1892 * e.g. the "rocker" device. Thus we have to look for the "netdev"
1893 * property, too. Unfortunately, some devices like virtio-net only
1894 * create this property during instance_init, so we have to create
1895 * a temporary instance here to be able to check it.
1897 Object
*obj
= object_new_with_class(OBJECT_CLASS(dc
));
1898 if (object_property_find(obj
, "netdev")) {
1899 g_ptr_array_add(pci_nic_models
, (gpointer
)name
);
1904 g_slist_free_1(list
);
1907 g_ptr_array_add(pci_nic_models
, NULL
);
1909 if (qemu_show_nic_models(nd
->model
, (const char **)pci_nic_models
->pdata
)) {
1913 i
= qemu_find_nic_model(nd
, (const char **)pci_nic_models
->pdata
,
1920 error_report("No primary PCI bus");
1924 assert(!rootbus
->parent_dev
);
1930 if (pci_parse_devaddr(devaddr
, &dom
, &busnr
, &slot
, NULL
) < 0) {
1931 error_report("Invalid PCI device address %s for device %s",
1932 devaddr
, nd
->model
);
1937 error_report("No support for non-zero PCI domains");
1941 devfn
= PCI_DEVFN(slot
, 0);
1944 bus
= pci_find_bus_nr(rootbus
, busnr
);
1946 error_report("Invalid PCI device address %s for device %s",
1947 devaddr
, nd
->model
);
1951 pci_dev
= pci_new(devfn
, nd
->model
);
1952 dev
= &pci_dev
->qdev
;
1953 qdev_set_nic_properties(dev
, nd
);
1954 pci_realize_and_unref(pci_dev
, bus
, &error_fatal
);
1955 g_ptr_array_free(pci_nic_models
, true);
1959 PCIDevice
*pci_vga_init(PCIBus
*bus
)
1961 switch (vga_interface_type
) {
1963 return pci_create_simple(bus
, -1, "cirrus-vga");
1965 return pci_create_simple(bus
, -1, "qxl-vga");
1967 return pci_create_simple(bus
, -1, "VGA");
1969 return pci_create_simple(bus
, -1, "vmware-svga");
1971 return pci_create_simple(bus
, -1, "virtio-vga");
1973 default: /* Other non-PCI types. Checking for unsupported types is already
1979 /* Whether a given bus number is in range of the secondary
1980 * bus of the given bridge device. */
1981 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1983 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1984 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1985 dev
->config
[PCI_SECONDARY_BUS
] <= bus_num
&&
1986 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1989 /* Whether a given bus number is in a range of a root bus */
1990 static bool pci_root_bus_in_range(PCIBus
*bus
, int bus_num
)
1994 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1995 PCIDevice
*dev
= bus
->devices
[i
];
1997 if (dev
&& PCI_DEVICE_GET_CLASS(dev
)->is_bridge
) {
1998 if (pci_secondary_bus_in_range(dev
, bus_num
)) {
2007 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
2015 if (pci_bus_num(bus
) == bus_num
) {
2019 /* Consider all bus numbers in range for the host pci bridge. */
2020 if (!pci_bus_is_root(bus
) &&
2021 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
2026 for (; bus
; bus
= sec
) {
2027 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2028 if (pci_bus_num(sec
) == bus_num
) {
2031 /* PXB buses assumed to be children of bus 0 */
2032 if (pci_bus_is_root(sec
)) {
2033 if (pci_root_bus_in_range(sec
, bus_num
)) {
2037 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
2047 void pci_for_each_bus_depth_first(PCIBus
*bus
,
2048 void *(*begin
)(PCIBus
*bus
, void *parent_state
),
2049 void (*end
)(PCIBus
*bus
, void *state
),
2060 state
= begin(bus
, parent_state
);
2062 state
= parent_state
;
2065 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2066 pci_for_each_bus_depth_first(sec
, begin
, end
, state
);
2075 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
2077 bus
= pci_find_bus_nr(bus
, bus_num
);
2082 return bus
->devices
[devfn
];
2085 static void pci_qdev_realize(DeviceState
*qdev
, Error
**errp
)
2087 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
2088 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
2089 ObjectClass
*klass
= OBJECT_CLASS(pc
);
2090 Error
*local_err
= NULL
;
2091 bool is_default_rom
;
2094 if (pci_dev
->romsize
!= -1 && !is_power_of_2(pci_dev
->romsize
)) {
2095 error_setg(errp
, "ROM size %u is not a power of two", pci_dev
->romsize
);
2099 /* initialize cap_present for pci_is_express() and pci_config_size(),
2100 * Note that hybrid PCIs are not set automatically and need to manage
2101 * QEMU_PCI_CAP_EXPRESS manually */
2102 if (object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
) &&
2103 !object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
)) {
2104 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2107 pci_dev
= do_pci_register_device(pci_dev
,
2108 object_get_typename(OBJECT(qdev
)),
2109 pci_dev
->devfn
, errp
);
2110 if (pci_dev
== NULL
)
2114 pc
->realize(pci_dev
, &local_err
);
2116 error_propagate(errp
, local_err
);
2117 do_pci_unregister_device(pci_dev
);
2122 if (pci_dev
->failover_pair_id
) {
2123 if (!pci_bus_is_express(pci_get_bus(pci_dev
))) {
2124 error_setg(errp
, "failover primary device must be on "
2126 pci_qdev_unrealize(DEVICE(pci_dev
));
2129 class_id
= pci_get_word(pci_dev
->config
+ PCI_CLASS_DEVICE
);
2130 if (class_id
!= PCI_CLASS_NETWORK_ETHERNET
) {
2131 error_setg(errp
, "failover primary device is not an "
2133 pci_qdev_unrealize(DEVICE(pci_dev
));
2136 if ((pci_dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)
2137 || (PCI_FUNC(pci_dev
->devfn
) != 0)) {
2138 error_setg(errp
, "failover: primary device must be in its own "
2140 pci_qdev_unrealize(DEVICE(pci_dev
));
2143 qdev
->allow_unplug_during_migration
= true;
2147 is_default_rom
= false;
2148 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
2149 pci_dev
->romfile
= g_strdup(pc
->romfile
);
2150 is_default_rom
= true;
2153 pci_add_option_rom(pci_dev
, is_default_rom
, &local_err
);
2155 error_propagate(errp
, local_err
);
2156 pci_qdev_unrealize(DEVICE(pci_dev
));
2161 PCIDevice
*pci_new_multifunction(int devfn
, bool multifunction
,
2166 dev
= qdev_new(name
);
2167 qdev_prop_set_int32(dev
, "addr", devfn
);
2168 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
2169 return PCI_DEVICE(dev
);
2172 PCIDevice
*pci_new(int devfn
, const char *name
)
2174 return pci_new_multifunction(devfn
, false, name
);
2177 bool pci_realize_and_unref(PCIDevice
*dev
, PCIBus
*bus
, Error
**errp
)
2179 return qdev_realize_and_unref(&dev
->qdev
, &bus
->qbus
, errp
);
2182 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
2186 PCIDevice
*dev
= pci_new_multifunction(devfn
, multifunction
, name
);
2187 pci_realize_and_unref(dev
, bus
, &error_fatal
);
2191 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
2193 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
2196 static uint8_t pci_find_space(PCIDevice
*pdev
, uint8_t size
)
2198 int offset
= PCI_CONFIG_HEADER_SIZE
;
2200 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
) {
2203 else if (i
- offset
+ 1 == size
)
2209 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
2214 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
2217 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2218 prev
= next
+ PCI_CAP_LIST_NEXT
)
2219 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
2227 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
2229 uint8_t next
, prev
, found
= 0;
2231 if (!(pdev
->used
[offset
])) {
2235 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
2237 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2238 prev
= next
+ PCI_CAP_LIST_NEXT
) {
2239 if (next
<= offset
&& next
> found
) {
2246 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2247 This is needed for an option rom which is used for more than one device. */
2248 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, uint32_t size
)
2252 uint16_t rom_vendor_id
;
2253 uint16_t rom_device_id
;
2255 uint16_t pcir_offset
;
2258 /* Words in rom data are little endian (like in PCI configuration),
2259 so they can be read / written with pci_get_word / pci_set_word. */
2261 /* Only a valid rom will be patched. */
2262 rom_magic
= pci_get_word(ptr
);
2263 if (rom_magic
!= 0xaa55) {
2264 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
2267 pcir_offset
= pci_get_word(ptr
+ 0x18);
2268 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
2269 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
2273 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
2274 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
2275 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
2276 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
2278 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
2279 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
2283 if (vendor_id
!= rom_vendor_id
) {
2284 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2285 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
2286 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
2287 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2289 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
2292 if (device_id
!= rom_device_id
) {
2293 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2294 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
2295 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
2296 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2298 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
2302 /* Add an option rom for the device */
2303 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
,
2310 const VMStateDescription
*vmsd
;
2314 if (strlen(pdev
->romfile
) == 0)
2317 if (!pdev
->rom_bar
) {
2319 * Load rom via fw_cfg instead of creating a rom bar,
2320 * for 0.11 compatibility.
2322 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
2325 * Hot-plugged devices can't use the option ROM
2326 * if the rom bar is disabled.
2328 if (DEVICE(pdev
)->hotplugged
) {
2329 error_setg(errp
, "Hot-plugged device without ROM bar"
2330 " can't have an option ROM");
2334 if (class == 0x0300) {
2335 rom_add_vga(pdev
->romfile
);
2337 rom_add_option(pdev
->romfile
, -1);
2342 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
2344 path
= g_strdup(pdev
->romfile
);
2347 size
= get_image_size(path
);
2349 error_setg(errp
, "failed to find romfile \"%s\"", pdev
->romfile
);
2352 } else if (size
== 0) {
2353 error_setg(errp
, "romfile \"%s\" is empty", pdev
->romfile
);
2356 } else if (size
> 2 * GiB
) {
2357 error_setg(errp
, "romfile \"%s\" too large (size cannot exceed 2 GiB)",
2362 if (pdev
->romsize
!= -1) {
2363 if (size
> pdev
->romsize
) {
2364 error_setg(errp
, "romfile \"%s\" (%u bytes) is too large for ROM size %u",
2365 pdev
->romfile
, (uint32_t)size
, pdev
->romsize
);
2370 pdev
->romsize
= pow2ceil(size
);
2373 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
2376 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
2378 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
2380 pdev
->has_rom
= true;
2381 memory_region_init_rom(&pdev
->rom
, OBJECT(pdev
), name
, pdev
->romsize
, &error_fatal
);
2382 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
2383 if (load_image_size(path
, ptr
, size
) < 0) {
2384 error_setg(errp
, "failed to load romfile \"%s\"", pdev
->romfile
);
2390 if (is_default_rom
) {
2391 /* Only the default rom images will be patched (if needed). */
2392 pci_patch_ids(pdev
, ptr
, size
);
2395 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
2398 static void pci_del_option_rom(PCIDevice
*pdev
)
2403 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
2404 pdev
->has_rom
= false;
2408 * On success, pci_add_capability() returns a positive value
2409 * that the offset of the pci capability.
2410 * On failure, it sets an error and returns a negative error
2413 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
2414 uint8_t offset
, uint8_t size
,
2418 int i
, overlapping_cap
;
2421 offset
= pci_find_space(pdev
, size
);
2422 /* out of PCI config space is programming error */
2425 /* Verify that capabilities don't overlap. Note: device assignment
2426 * depends on this check to verify that the device is not broken.
2427 * Should never trigger for emulated devices, but it's helpful
2428 * for debugging these. */
2429 for (i
= offset
; i
< offset
+ size
; i
++) {
2430 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
2431 if (overlapping_cap
) {
2432 error_setg(errp
, "%s:%02x:%02x.%x "
2433 "Attempt to add PCI capability %x at offset "
2434 "%x overlaps existing capability %x at offset %x",
2435 pci_root_bus_path(pdev
), pci_dev_bus_num(pdev
),
2436 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
2437 cap_id
, offset
, overlapping_cap
, i
);
2443 config
= pdev
->config
+ offset
;
2444 config
[PCI_CAP_LIST_ID
] = cap_id
;
2445 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2446 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2447 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2448 memset(pdev
->used
+ offset
, 0xFF, QEMU_ALIGN_UP(size
, 4));
2449 /* Make capability read-only by default */
2450 memset(pdev
->wmask
+ offset
, 0, size
);
2451 /* Check capability by default */
2452 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2456 /* Unlink capability from the pci config space. */
2457 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2459 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2462 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2463 /* Make capability writable again */
2464 memset(pdev
->wmask
+ offset
, 0xff, size
);
2465 memset(pdev
->w1cmask
+ offset
, 0, size
);
2466 /* Clear cmask as device-specific registers can't be checked */
2467 memset(pdev
->cmask
+ offset
, 0, size
);
2468 memset(pdev
->used
+ offset
, 0, QEMU_ALIGN_UP(size
, 4));
2470 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2471 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2474 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2476 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2479 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2481 PCIDevice
*d
= (PCIDevice
*)dev
;
2482 const pci_class_desc
*desc
;
2487 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2488 desc
= pci_class_descriptions
;
2489 while (desc
->desc
&& class != desc
->class)
2492 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2494 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2497 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2498 "pci id %04x:%04x (sub %04x:%04x)\n",
2499 indent
, "", ctxt
, pci_dev_bus_num(d
),
2500 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2501 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2502 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2503 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2504 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2505 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2506 r
= &d
->io_regions
[i
];
2509 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2510 " [0x%"FMT_PCIBUS
"]\n",
2512 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2513 r
->addr
, r
->addr
+ r
->size
- 1);
2517 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2519 PCIDevice
*d
= (PCIDevice
*)dev
;
2520 const char *name
= NULL
;
2521 const pci_class_desc
*desc
= pci_class_descriptions
;
2522 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2524 while (desc
->desc
&&
2525 (class & ~desc
->fw_ign_bits
) !=
2526 (desc
->class & ~desc
->fw_ign_bits
)) {
2531 name
= desc
->fw_name
;
2535 pstrcpy(buf
, len
, name
);
2537 snprintf(buf
, len
, "pci%04x,%04x",
2538 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2539 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2545 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2547 PCIDevice
*d
= (PCIDevice
*)dev
;
2548 char path
[50], name
[33];
2551 off
= snprintf(path
, sizeof(path
), "%s@%x",
2552 pci_dev_fw_name(dev
, name
, sizeof name
),
2553 PCI_SLOT(d
->devfn
));
2554 if (PCI_FUNC(d
->devfn
))
2555 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2556 return g_strdup(path
);
2559 static char *pcibus_get_dev_path(DeviceState
*dev
)
2561 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2564 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2565 * 00 is added here to make this format compatible with
2566 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2567 * Slot.Function list specifies the slot and function numbers for all
2568 * devices on the path from root to the specific device. */
2569 const char *root_bus_path
;
2571 char slot
[] = ":SS.F";
2572 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2577 root_bus_path
= pci_root_bus_path(d
);
2578 root_bus_len
= strlen(root_bus_path
);
2580 /* Calculate # of slots on path between device and root. */;
2582 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2586 path_len
= root_bus_len
+ slot_len
* slot_depth
;
2588 /* Allocate memory, fill in the terminating null byte. */
2589 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2590 path
[path_len
] = '\0';
2592 memcpy(path
, root_bus_path
, root_bus_len
);
2594 /* Fill in slot numbers. We walk up from device to root, so need to print
2595 * them in the reverse order, last to first. */
2596 p
= path
+ path_len
;
2597 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2599 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2600 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2601 assert(s
== slot_len
);
2602 memcpy(p
, slot
, slot_len
);
2608 static int pci_qdev_find_recursive(PCIBus
*bus
,
2609 const char *id
, PCIDevice
**pdev
)
2611 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2616 /* roughly check if given qdev is pci device */
2617 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2618 *pdev
= PCI_DEVICE(qdev
);
2624 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2626 PCIHostState
*host_bridge
;
2629 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
2630 int tmp
= pci_qdev_find_recursive(host_bridge
->bus
, id
, pdev
);
2635 if (tmp
!= -ENODEV
) {
2643 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2645 return pci_get_bus(dev
)->address_space_mem
;
2648 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2650 return pci_get_bus(dev
)->address_space_io
;
2653 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2655 DeviceClass
*k
= DEVICE_CLASS(klass
);
2657 k
->realize
= pci_qdev_realize
;
2658 k
->unrealize
= pci_qdev_unrealize
;
2659 k
->bus_type
= TYPE_PCI_BUS
;
2660 device_class_set_props(k
, pci_props
);
2663 static void pci_device_class_base_init(ObjectClass
*klass
, void *data
)
2665 if (!object_class_is_abstract(klass
)) {
2666 ObjectClass
*conventional
=
2667 object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
);
2669 object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
);
2670 assert(conventional
|| pcie
);
2674 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
)
2676 PCIBus
*bus
= pci_get_bus(dev
);
2677 PCIBus
*iommu_bus
= bus
;
2678 uint8_t devfn
= dev
->devfn
;
2680 while (iommu_bus
&& !iommu_bus
->iommu_fn
&& iommu_bus
->parent_dev
) {
2681 PCIBus
*parent_bus
= pci_get_bus(iommu_bus
->parent_dev
);
2684 * The requester ID of the provided device may be aliased, as seen from
2685 * the IOMMU, due to topology limitations. The IOMMU relies on a
2686 * requester ID to provide a unique AddressSpace for devices, but
2687 * conventional PCI buses pre-date such concepts. Instead, the PCIe-
2688 * to-PCI bridge creates and accepts transactions on behalf of down-
2689 * stream devices. When doing so, all downstream devices are masked
2690 * (aliased) behind a single requester ID. The requester ID used
2691 * depends on the format of the bridge devices. Proper PCIe-to-PCI
2692 * bridges, with a PCIe capability indicating such, follow the
2693 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification,
2694 * where the bridge uses the seconary bus as the bridge portion of the
2695 * requester ID and devfn of 00.0. For other bridges, typically those
2696 * found on the root complex such as the dmi-to-pci-bridge, we follow
2697 * the convention of typical bare-metal hardware, which uses the
2698 * requester ID of the bridge itself. There are device specific
2699 * exceptions to these rules, but these are the defaults that the
2700 * Linux kernel uses when determining DMA aliases itself and believed
2701 * to be true for the bare metal equivalents of the devices emulated
2704 if (!pci_bus_is_express(iommu_bus
)) {
2705 PCIDevice
*parent
= iommu_bus
->parent_dev
;
2707 if (pci_is_express(parent
) &&
2708 pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2709 devfn
= PCI_DEVFN(0, 0);
2712 devfn
= parent
->devfn
;
2717 iommu_bus
= parent_bus
;
2719 if (iommu_bus
&& iommu_bus
->iommu_fn
) {
2720 return iommu_bus
->iommu_fn(bus
, iommu_bus
->iommu_opaque
, devfn
);
2722 return &address_space_memory
;
2725 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
)
2728 bus
->iommu_opaque
= opaque
;
2731 static void pci_dev_get_w64(PCIBus
*b
, PCIDevice
*dev
, void *opaque
)
2733 Range
*range
= opaque
;
2734 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
2735 uint16_t cmd
= pci_get_word(dev
->config
+ PCI_COMMAND
);
2738 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
2742 if (pc
->is_bridge
) {
2743 pcibus_t base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2744 pcibus_t limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2746 base
= MAX(base
, 0x1ULL
<< 32);
2748 if (limit
>= base
) {
2750 range_set_bounds(&pref_range
, base
, limit
);
2751 range_extend(range
, &pref_range
);
2754 for (i
= 0; i
< PCI_NUM_REGIONS
; ++i
) {
2755 PCIIORegion
*r
= &dev
->io_regions
[i
];
2760 (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) ||
2761 !(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
2765 lob
= pci_bar_address(dev
, i
, r
->type
, r
->size
);
2766 upb
= lob
+ r
->size
- 1;
2767 if (lob
== PCI_BAR_UNMAPPED
) {
2771 lob
= MAX(lob
, 0x1ULL
<< 32);
2774 range_set_bounds(®ion_range
, lob
, upb
);
2775 range_extend(range
, ®ion_range
);
2780 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
)
2782 range_make_empty(range
);
2783 pci_for_each_device_under_bus(bus
, pci_dev_get_w64
, range
);
2786 static bool pcie_has_upstream_port(PCIDevice
*dev
)
2788 PCIDevice
*parent_dev
= pci_bridge_get_device(pci_get_bus(dev
));
2790 /* Device associated with an upstream port.
2791 * As there are several types of these, it's easier to check the
2792 * parent device: upstream ports are always connected to
2793 * root or downstream ports.
2795 return parent_dev
&&
2796 pci_is_express(parent_dev
) &&
2797 parent_dev
->exp
.exp_cap
&&
2798 (pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_ROOT_PORT
||
2799 pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_DOWNSTREAM
);
2802 PCIDevice
*pci_get_function_0(PCIDevice
*pci_dev
)
2804 PCIBus
*bus
= pci_get_bus(pci_dev
);
2806 if(pcie_has_upstream_port(pci_dev
)) {
2807 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2808 return bus
->devices
[0];
2810 /* Other bus types might support multiple devices at slots 0-31 */
2811 return bus
->devices
[PCI_DEVFN(PCI_SLOT(pci_dev
->devfn
), 0)];
2815 MSIMessage
pci_get_msi_message(PCIDevice
*dev
, int vector
)
2818 if (msix_enabled(dev
)) {
2819 msg
= msix_get_message(dev
, vector
);
2820 } else if (msi_enabled(dev
)) {
2821 msg
= msi_get_message(dev
, vector
);
2823 /* Should never happen */
2824 error_report("%s: unknown interrupt type", __func__
);
2830 static const TypeInfo pci_device_type_info
= {
2831 .name
= TYPE_PCI_DEVICE
,
2832 .parent
= TYPE_DEVICE
,
2833 .instance_size
= sizeof(PCIDevice
),
2835 .class_size
= sizeof(PCIDeviceClass
),
2836 .class_init
= pci_device_class_init
,
2837 .class_base_init
= pci_device_class_base_init
,
2840 static void pci_register_types(void)
2842 type_register_static(&pci_bus_info
);
2843 type_register_static(&pcie_bus_info
);
2844 type_register_static(&conventional_pci_interface_info
);
2845 type_register_static(&pcie_interface_info
);
2846 type_register_static(&pci_device_type_info
);
2849 type_init(pci_register_types
)