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ppc4xx: Disable debug logging by default
[qemu/ar7.git] / hw / ppc / ppc4xx_devs.c
blob9b6e4c60fa7ee7c4fb589d23a1652f404eb58666
1 /*
2 * QEMU PowerPC 4xx embedded processors shared devices emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "cpu.h"
27 #include "hw/hw.h"
28 #include "hw/ppc/ppc.h"
29 #include "hw/ppc/ppc4xx.h"
30 #include "hw/boards.h"
31 #include "qemu/log.h"
32 #include "exec/address-spaces.h"
33 #include "qemu/error-report.h"
34
35 /*#define DEBUG_UIC*/
36
37 #ifdef DEBUG_UIC
38 # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
39 #else
40 # define LOG_UIC(...) do { } while (0)
41 #endif
42
43 static void ppc4xx_reset(void *opaque)
44 {
45 PowerPCCPU *cpu = opaque;
46
47 cpu_reset(CPU(cpu));
48 }
49
50 /*****************************************************************************/
51 /* Generic PowerPC 4xx processor instantiation */
52 PowerPCCPU *ppc4xx_init(const char *cpu_type,
53 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
54 uint32_t sysclk)
55 {
56 PowerPCCPU *cpu;
57 CPUPPCState *env;
58
59 /* init CPUs */
60 cpu = POWERPC_CPU(cpu_create(cpu_type));
61 env = &cpu->env;
62
63 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
64 cpu_clk->opaque = env;
65 /* Set time-base frequency to sysclk */
66 tb_clk->cb = ppc_40x_timers_init(env, sysclk, PPC_INTERRUPT_PIT);
67 tb_clk->opaque = env;
68 ppc_dcr_init(env, NULL, NULL);
69 /* Register qemu callbacks */
70 qemu_register_reset(ppc4xx_reset, cpu);
71
72 return cpu;
73 }
74
75 /*****************************************************************************/
76 /* "Universal" Interrupt controller */
77 enum {
78 DCR_UICSR = 0x000,
79 DCR_UICSRS = 0x001,
80 DCR_UICER = 0x002,
81 DCR_UICCR = 0x003,
82 DCR_UICPR = 0x004,
83 DCR_UICTR = 0x005,
84 DCR_UICMSR = 0x006,
85 DCR_UICVR = 0x007,
86 DCR_UICVCR = 0x008,
87 DCR_UICMAX = 0x009,
88 };
89
90 #define UIC_MAX_IRQ 32
91 typedef struct ppcuic_t ppcuic_t;
92 struct ppcuic_t {
93 uint32_t dcr_base;
94 int use_vectors;
95 uint32_t level; /* Remembers the state of level-triggered interrupts. */
96 uint32_t uicsr; /* Status register */
97 uint32_t uicer; /* Enable register */
98 uint32_t uiccr; /* Critical register */
99 uint32_t uicpr; /* Polarity register */
100 uint32_t uictr; /* Triggering register */
101 uint32_t uicvcr; /* Vector configuration register */
102 uint32_t uicvr;
103 qemu_irq *irqs;
104 };
105
106 static void ppcuic_trigger_irq (ppcuic_t *uic)
107 {
108 uint32_t ir, cr;
109 int start, end, inc, i;
110
111 /* Trigger interrupt if any is pending */
112 ir = uic->uicsr & uic->uicer & (~uic->uiccr);
113 cr = uic->uicsr & uic->uicer & uic->uiccr;
114 LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
115 " uiccr %08" PRIx32 "\n"
116 " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
117 __func__, uic->uicsr, uic->uicer, uic->uiccr,
118 uic->uicsr & uic->uicer, ir, cr);
119 if (ir != 0x0000000) {
120 LOG_UIC("Raise UIC interrupt\n");
121 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
122 } else {
123 LOG_UIC("Lower UIC interrupt\n");
124 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
125 }
126 /* Trigger critical interrupt if any is pending and update vector */
127 if (cr != 0x0000000) {
128 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
129 if (uic->use_vectors) {
130 /* Compute critical IRQ vector */
131 if (uic->uicvcr & 1) {
132 start = 31;
133 end = 0;
134 inc = -1;
135 } else {
136 start = 0;
137 end = 31;
138 inc = 1;
139 }
140 uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
141 for (i = start; i <= end; i += inc) {
142 if (cr & (1 << i)) {
143 uic->uicvr += (i - start) * 512 * inc;
144 break;
145 }
146 }
147 }
148 LOG_UIC("Raise UIC critical interrupt - "
149 "vector %08" PRIx32 "\n", uic->uicvr);
150 } else {
151 LOG_UIC("Lower UIC critical interrupt\n");
152 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
153 uic->uicvr = 0x00000000;
154 }
155 }
156
157 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
158 {
159 ppcuic_t *uic;
160 uint32_t mask, sr;
161
162 uic = opaque;
163 mask = 1U << (31-irq_num);
164 LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
165 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
166 __func__, irq_num, level,
167 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
168 if (irq_num < 0 || irq_num > 31)
169 return;
170 sr = uic->uicsr;
171
172 /* Update status register */
173 if (uic->uictr & mask) {
174 /* Edge sensitive interrupt */
175 if (level == 1)
176 uic->uicsr |= mask;
177 } else {
178 /* Level sensitive interrupt */
179 if (level == 1) {
180 uic->uicsr |= mask;
181 uic->level |= mask;
182 } else {
183 uic->uicsr &= ~mask;
184 uic->level &= ~mask;
185 }
186 }
187 LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
188 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
189 if (sr != uic->uicsr)
190 ppcuic_trigger_irq(uic);
191 }
192
193 static uint32_t dcr_read_uic (void *opaque, int dcrn)
194 {
195 ppcuic_t *uic;
196 uint32_t ret;
197
198 uic = opaque;
199 dcrn -= uic->dcr_base;
200 switch (dcrn) {
201 case DCR_UICSR:
202 case DCR_UICSRS:
203 ret = uic->uicsr;
204 break;
205 case DCR_UICER:
206 ret = uic->uicer;
207 break;
208 case DCR_UICCR:
209 ret = uic->uiccr;
210 break;
211 case DCR_UICPR:
212 ret = uic->uicpr;
213 break;
214 case DCR_UICTR:
215 ret = uic->uictr;
216 break;
217 case DCR_UICMSR:
218 ret = uic->uicsr & uic->uicer;
219 break;
220 case DCR_UICVR:
221 if (!uic->use_vectors)
222 goto no_read;
223 ret = uic->uicvr;
224 break;
225 case DCR_UICVCR:
226 if (!uic->use_vectors)
227 goto no_read;
228 ret = uic->uicvcr;
229 break;
230 default:
231 no_read:
232 ret = 0x00000000;
233 break;
234 }
235
236 return ret;
237 }
238
239 static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
240 {
241 ppcuic_t *uic;
242
243 uic = opaque;
244 dcrn -= uic->dcr_base;
245 LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
246 switch (dcrn) {
247 case DCR_UICSR:
248 uic->uicsr &= ~val;
249 uic->uicsr |= uic->level;
250 ppcuic_trigger_irq(uic);
251 break;
252 case DCR_UICSRS:
253 uic->uicsr |= val;
254 ppcuic_trigger_irq(uic);
255 break;
256 case DCR_UICER:
257 uic->uicer = val;
258 ppcuic_trigger_irq(uic);
259 break;
260 case DCR_UICCR:
261 uic->uiccr = val;
262 ppcuic_trigger_irq(uic);
263 break;
264 case DCR_UICPR:
265 uic->uicpr = val;
266 break;
267 case DCR_UICTR:
268 uic->uictr = val;
269 ppcuic_trigger_irq(uic);
270 break;
271 case DCR_UICMSR:
272 break;
273 case DCR_UICVR:
274 break;
275 case DCR_UICVCR:
276 uic->uicvcr = val & 0xFFFFFFFD;
277 ppcuic_trigger_irq(uic);
278 break;
279 }
280 }
281
282 static void ppcuic_reset (void *opaque)
283 {
284 ppcuic_t *uic;
285
286 uic = opaque;
287 uic->uiccr = 0x00000000;
288 uic->uicer = 0x00000000;
289 uic->uicpr = 0x00000000;
290 uic->uicsr = 0x00000000;
291 uic->uictr = 0x00000000;
292 if (uic->use_vectors) {
293 uic->uicvcr = 0x00000000;
294 uic->uicvr = 0x0000000;
295 }
296 }
297
298 qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
299 uint32_t dcr_base, int has_ssr, int has_vr)
300 {
301 ppcuic_t *uic;
302 int i;
303
304 uic = g_malloc0(sizeof(ppcuic_t));
305 uic->dcr_base = dcr_base;
306 uic->irqs = irqs;
307 if (has_vr)
308 uic->use_vectors = 1;
309 for (i = 0; i < DCR_UICMAX; i++) {
310 ppc_dcr_register(env, dcr_base + i, uic,
311 &dcr_read_uic, &dcr_write_uic);
312 }
313 qemu_register_reset(ppcuic_reset, uic);
314
315 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
316 }
317
318 /*****************************************************************************/
319 /* SDRAM controller */
320 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
321 struct ppc4xx_sdram_t {
322 uint32_t addr;
323 int nbanks;
324 MemoryRegion containers[4]; /* used for clipping */
325 MemoryRegion *ram_memories;
326 hwaddr ram_bases[4];
327 hwaddr ram_sizes[4];
328 uint32_t besr0;
329 uint32_t besr1;
330 uint32_t bear;
331 uint32_t cfg;
332 uint32_t status;
333 uint32_t rtr;
334 uint32_t pmit;
335 uint32_t bcr[4];
336 uint32_t tr;
337 uint32_t ecccfg;
338 uint32_t eccesr;
339 qemu_irq irq;
340 };
341
342 enum {
343 SDRAM0_CFGADDR = 0x010,
344 SDRAM0_CFGDATA = 0x011,
345 };
346
347 /* XXX: TOFIX: some patches have made this code become inconsistent:
348 * there are type inconsistencies, mixing hwaddr, target_ulong
349 * and uint32_t
350 */
351 static uint32_t sdram_bcr (hwaddr ram_base,
352 hwaddr ram_size)
353 {
354 uint32_t bcr;
355
356 switch (ram_size) {
357 case 4 * MiB:
358 bcr = 0x00000000;
359 break;
360 case 8 * MiB:
361 bcr = 0x00020000;
362 break;
363 case 16 * MiB:
364 bcr = 0x00040000;
365 break;
366 case 32 * MiB:
367 bcr = 0x00060000;
368 break;
369 case 64 * MiB:
370 bcr = 0x00080000;
371 break;
372 case 128 * MiB:
373 bcr = 0x000A0000;
374 break;
375 case 256 * MiB:
376 bcr = 0x000C0000;
377 break;
378 default:
379 printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
380 ram_size);
381 return 0x00000000;
382 }
383 bcr |= ram_base & 0xFF800000;
384 bcr |= 1;
385
386 return bcr;
387 }
388
389 static inline hwaddr sdram_base(uint32_t bcr)
390 {
391 return bcr & 0xFF800000;
392 }
393
394 static target_ulong sdram_size (uint32_t bcr)
395 {
396 target_ulong size;
397 int sh;
398
399 sh = (bcr >> 17) & 0x7;
400 if (sh == 7)
401 size = -1;
402 else
403 size = (4 * MiB) << sh;
404
405 return size;
406 }
407
408 static void sdram_set_bcr(ppc4xx_sdram_t *sdram,
409 uint32_t *bcrp, uint32_t bcr, int enabled)
410 {
411 unsigned n = bcrp - sdram->bcr;
412
413 if (*bcrp & 0x00000001) {
414 /* Unmap RAM */
415 #ifdef DEBUG_SDRAM
416 printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
417 __func__, sdram_base(*bcrp), sdram_size(*bcrp));
418 #endif
419 memory_region_del_subregion(get_system_memory(),
420 &sdram->containers[n]);
421 memory_region_del_subregion(&sdram->containers[n],
422 &sdram->ram_memories[n]);
423 object_unparent(OBJECT(&sdram->containers[n]));
424 }
425 *bcrp = bcr & 0xFFDEE001;
426 if (enabled && (bcr & 0x00000001)) {
427 #ifdef DEBUG_SDRAM
428 printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
429 __func__, sdram_base(bcr), sdram_size(bcr));
430 #endif
431 memory_region_init(&sdram->containers[n], NULL, "sdram-containers",
432 sdram_size(bcr));
433 memory_region_add_subregion(&sdram->containers[n], 0,
434 &sdram->ram_memories[n]);
435 memory_region_add_subregion(get_system_memory(),
436 sdram_base(bcr),
437 &sdram->containers[n]);
438 }
439 }
440
441 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
442 {
443 int i;
444
445 for (i = 0; i < sdram->nbanks; i++) {
446 if (sdram->ram_sizes[i] != 0) {
447 sdram_set_bcr(sdram,
448 &sdram->bcr[i],
449 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
450 1);
451 } else {
452 sdram_set_bcr(sdram, &sdram->bcr[i], 0x00000000, 0);
453 }
454 }
455 }
456
457 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
458 {
459 int i;
460
461 for (i = 0; i < sdram->nbanks; i++) {
462 #ifdef DEBUG_SDRAM
463 printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
464 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
465 #endif
466 memory_region_del_subregion(get_system_memory(),
467 &sdram->ram_memories[i]);
468 }
469 }
470
471 static uint32_t dcr_read_sdram (void *opaque, int dcrn)
472 {
473 ppc4xx_sdram_t *sdram;
474 uint32_t ret;
475
476 sdram = opaque;
477 switch (dcrn) {
478 case SDRAM0_CFGADDR:
479 ret = sdram->addr;
480 break;
481 case SDRAM0_CFGDATA:
482 switch (sdram->addr) {
483 case 0x00: /* SDRAM_BESR0 */
484 ret = sdram->besr0;
485 break;
486 case 0x08: /* SDRAM_BESR1 */
487 ret = sdram->besr1;
488 break;
489 case 0x10: /* SDRAM_BEAR */
490 ret = sdram->bear;
491 break;
492 case 0x20: /* SDRAM_CFG */
493 ret = sdram->cfg;
494 break;
495 case 0x24: /* SDRAM_STATUS */
496 ret = sdram->status;
497 break;
498 case 0x30: /* SDRAM_RTR */
499 ret = sdram->rtr;
500 break;
501 case 0x34: /* SDRAM_PMIT */
502 ret = sdram->pmit;
503 break;
504 case 0x40: /* SDRAM_B0CR */
505 ret = sdram->bcr[0];
506 break;
507 case 0x44: /* SDRAM_B1CR */
508 ret = sdram->bcr[1];
509 break;
510 case 0x48: /* SDRAM_B2CR */
511 ret = sdram->bcr[2];
512 break;
513 case 0x4C: /* SDRAM_B3CR */
514 ret = sdram->bcr[3];
515 break;
516 case 0x80: /* SDRAM_TR */
517 ret = -1; /* ? */
518 break;
519 case 0x94: /* SDRAM_ECCCFG */
520 ret = sdram->ecccfg;
521 break;
522 case 0x98: /* SDRAM_ECCESR */
523 ret = sdram->eccesr;
524 break;
525 default: /* Error */
526 ret = -1;
527 break;
528 }
529 break;
530 default:
531 /* Avoid gcc warning */
532 ret = 0x00000000;
533 break;
534 }
535
536 return ret;
537 }
538
539 static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
540 {
541 ppc4xx_sdram_t *sdram;
542
543 sdram = opaque;
544 switch (dcrn) {
545 case SDRAM0_CFGADDR:
546 sdram->addr = val;
547 break;
548 case SDRAM0_CFGDATA:
549 switch (sdram->addr) {
550 case 0x00: /* SDRAM_BESR0 */
551 sdram->besr0 &= ~val;
552 break;
553 case 0x08: /* SDRAM_BESR1 */
554 sdram->besr1 &= ~val;
555 break;
556 case 0x10: /* SDRAM_BEAR */
557 sdram->bear = val;
558 break;
559 case 0x20: /* SDRAM_CFG */
560 val &= 0xFFE00000;
561 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
562 #ifdef DEBUG_SDRAM
563 printf("%s: enable SDRAM controller\n", __func__);
564 #endif
565 /* validate all RAM mappings */
566 sdram_map_bcr(sdram);
567 sdram->status &= ~0x80000000;
568 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
569 #ifdef DEBUG_SDRAM
570 printf("%s: disable SDRAM controller\n", __func__);
571 #endif
572 /* invalidate all RAM mappings */
573 sdram_unmap_bcr(sdram);
574 sdram->status |= 0x80000000;
575 }
576 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
577 sdram->status |= 0x40000000;
578 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
579 sdram->status &= ~0x40000000;
580 sdram->cfg = val;
581 break;
582 case 0x24: /* SDRAM_STATUS */
583 /* Read-only register */
584 break;
585 case 0x30: /* SDRAM_RTR */
586 sdram->rtr = val & 0x3FF80000;
587 break;
588 case 0x34: /* SDRAM_PMIT */
589 sdram->pmit = (val & 0xF8000000) | 0x07C00000;
590 break;
591 case 0x40: /* SDRAM_B0CR */
592 sdram_set_bcr(sdram, &sdram->bcr[0], val, sdram->cfg & 0x80000000);
593 break;
594 case 0x44: /* SDRAM_B1CR */
595 sdram_set_bcr(sdram, &sdram->bcr[1], val, sdram->cfg & 0x80000000);
596 break;
597 case 0x48: /* SDRAM_B2CR */
598 sdram_set_bcr(sdram, &sdram->bcr[2], val, sdram->cfg & 0x80000000);
599 break;
600 case 0x4C: /* SDRAM_B3CR */
601 sdram_set_bcr(sdram, &sdram->bcr[3], val, sdram->cfg & 0x80000000);
602 break;
603 case 0x80: /* SDRAM_TR */
604 sdram->tr = val & 0x018FC01F;
605 break;
606 case 0x94: /* SDRAM_ECCCFG */
607 sdram->ecccfg = val & 0x00F00000;
608 break;
609 case 0x98: /* SDRAM_ECCESR */
610 val &= 0xFFF0F000;
611 if (sdram->eccesr == 0 && val != 0)
612 qemu_irq_raise(sdram->irq);
613 else if (sdram->eccesr != 0 && val == 0)
614 qemu_irq_lower(sdram->irq);
615 sdram->eccesr = val;
616 break;
617 default: /* Error */
618 break;
619 }
620 break;
621 }
622 }
623
624 static void sdram_reset (void *opaque)
625 {
626 ppc4xx_sdram_t *sdram;
627
628 sdram = opaque;
629 sdram->addr = 0x00000000;
630 sdram->bear = 0x00000000;
631 sdram->besr0 = 0x00000000; /* No error */
632 sdram->besr1 = 0x00000000; /* No error */
633 sdram->cfg = 0x00000000;
634 sdram->ecccfg = 0x00000000; /* No ECC */
635 sdram->eccesr = 0x00000000; /* No error */
636 sdram->pmit = 0x07C00000;
637 sdram->rtr = 0x05F00000;
638 sdram->tr = 0x00854009;
639 /* We pre-initialize RAM banks */
640 sdram->status = 0x00000000;
641 sdram->cfg = 0x00800000;
642 }
643
644 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
645 MemoryRegion *ram_memories,
646 hwaddr *ram_bases,
647 hwaddr *ram_sizes,
648 int do_init)
649 {
650 ppc4xx_sdram_t *sdram;
651
652 sdram = g_malloc0(sizeof(ppc4xx_sdram_t));
653 sdram->irq = irq;
654 sdram->nbanks = nbanks;
655 sdram->ram_memories = ram_memories;
656 memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
657 memcpy(sdram->ram_bases, ram_bases,
658 nbanks * sizeof(hwaddr));
659 memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
660 memcpy(sdram->ram_sizes, ram_sizes,
661 nbanks * sizeof(hwaddr));
662 qemu_register_reset(&sdram_reset, sdram);
663 ppc_dcr_register(env, SDRAM0_CFGADDR,
664 sdram, &dcr_read_sdram, &dcr_write_sdram);
665 ppc_dcr_register(env, SDRAM0_CFGDATA,
666 sdram, &dcr_read_sdram, &dcr_write_sdram);
667 if (do_init)
668 sdram_map_bcr(sdram);
669 }
670
671 /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
672 *
673 * sdram_bank_sizes[] must be 0-terminated.
674 *
675 * The 4xx SDRAM controller supports a small number of banks, and each bank
676 * must be one of a small set of sizes. The number of banks and the supported
677 * sizes varies by SoC. */
678 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
679 MemoryRegion ram_memories[],
680 hwaddr ram_bases[],
681 hwaddr ram_sizes[],
682 const unsigned int sdram_bank_sizes[])
683 {
684 MemoryRegion *ram = g_malloc0(sizeof(*ram));
685 ram_addr_t size_left = ram_size;
686 ram_addr_t base = 0;
687 unsigned int bank_size;
688 int i;
689 int j;
690
691 for (i = 0; i < nr_banks; i++) {
692 for (j = 0; sdram_bank_sizes[j] != 0; j++) {
693 bank_size = sdram_bank_sizes[j];
694 if (bank_size <= size_left) {
695 size_left -= bank_size;
696 }
697 }
698 if (!size_left) {
699 /* No need to use the remaining banks. */
700 break;
701 }
702 }
703
704 ram_size -= size_left;
705 if (size_left) {
706 error_report("Truncating memory to %" PRId64 " MiB to fit SDRAM"
707 " controller limits", ram_size / MiB);
708 }
709
710 memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size);
711
712 size_left = ram_size;
713 for (i = 0; i < nr_banks && size_left; i++) {
714 for (j = 0; sdram_bank_sizes[j] != 0; j++) {
715 bank_size = sdram_bank_sizes[j];
716
717 if (bank_size <= size_left) {
718 char name[32];
719 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
720 memory_region_init_alias(&ram_memories[i], NULL, name, ram,
721 base, bank_size);
722 ram_bases[i] = base;
723 ram_sizes[i] = bank_size;
724 base += bank_size;
725 size_left -= bank_size;
726 break;
727 }
728 }
729 }
730
731 return ram_size;
732 }
733
734 /*****************************************************************************/
735 /* MAL */
736
737 enum {
738 MAL0_CFG = 0x180,
739 MAL0_ESR = 0x181,
740 MAL0_IER = 0x182,
741 MAL0_TXCASR = 0x184,
742 MAL0_TXCARR = 0x185,
743 MAL0_TXEOBISR = 0x186,
744 MAL0_TXDEIR = 0x187,
745 MAL0_RXCASR = 0x190,
746 MAL0_RXCARR = 0x191,
747 MAL0_RXEOBISR = 0x192,
748 MAL0_RXDEIR = 0x193,
749 MAL0_TXCTP0R = 0x1A0,
750 MAL0_RXCTP0R = 0x1C0,
751 MAL0_RCBS0 = 0x1E0,
752 MAL0_RCBS1 = 0x1E1,
753 };
754
755 typedef struct ppc4xx_mal_t ppc4xx_mal_t;
756 struct ppc4xx_mal_t {
757 qemu_irq irqs[4];
758 uint32_t cfg;
759 uint32_t esr;
760 uint32_t ier;
761 uint32_t txcasr;
762 uint32_t txcarr;
763 uint32_t txeobisr;
764 uint32_t txdeir;
765 uint32_t rxcasr;
766 uint32_t rxcarr;
767 uint32_t rxeobisr;
768 uint32_t rxdeir;
769 uint32_t *txctpr;
770 uint32_t *rxctpr;
771 uint32_t *rcbs;
772 uint8_t txcnum;
773 uint8_t rxcnum;
774 };
775
776 static void ppc4xx_mal_reset(void *opaque)
777 {
778 ppc4xx_mal_t *mal;
779
780 mal = opaque;
781 mal->cfg = 0x0007C000;
782 mal->esr = 0x00000000;
783 mal->ier = 0x00000000;
784 mal->rxcasr = 0x00000000;
785 mal->rxdeir = 0x00000000;
786 mal->rxeobisr = 0x00000000;
787 mal->txcasr = 0x00000000;
788 mal->txdeir = 0x00000000;
789 mal->txeobisr = 0x00000000;
790 }
791
792 static uint32_t dcr_read_mal(void *opaque, int dcrn)
793 {
794 ppc4xx_mal_t *mal;
795 uint32_t ret;
796
797 mal = opaque;
798 switch (dcrn) {
799 case MAL0_CFG:
800 ret = mal->cfg;
801 break;
802 case MAL0_ESR:
803 ret = mal->esr;
804 break;
805 case MAL0_IER:
806 ret = mal->ier;
807 break;
808 case MAL0_TXCASR:
809 ret = mal->txcasr;
810 break;
811 case MAL0_TXCARR:
812 ret = mal->txcarr;
813 break;
814 case MAL0_TXEOBISR:
815 ret = mal->txeobisr;
816 break;
817 case MAL0_TXDEIR:
818 ret = mal->txdeir;
819 break;
820 case MAL0_RXCASR:
821 ret = mal->rxcasr;
822 break;
823 case MAL0_RXCARR:
824 ret = mal->rxcarr;
825 break;
826 case MAL0_RXEOBISR:
827 ret = mal->rxeobisr;
828 break;
829 case MAL0_RXDEIR:
830 ret = mal->rxdeir;
831 break;
832 default:
833 ret = 0;
834 break;
835 }
836 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
837 ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
838 }
839 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
840 ret = mal->rxctpr[dcrn - MAL0_RXCTP0R];
841 }
842 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
843 ret = mal->rcbs[dcrn - MAL0_RCBS0];
844 }
845
846 return ret;
847 }
848
849 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
850 {
851 ppc4xx_mal_t *mal;
852
853 mal = opaque;
854 switch (dcrn) {
855 case MAL0_CFG:
856 if (val & 0x80000000) {
857 ppc4xx_mal_reset(mal);
858 }
859 mal->cfg = val & 0x00FFC087;
860 break;
861 case MAL0_ESR:
862 /* Read/clear */
863 mal->esr &= ~val;
864 break;
865 case MAL0_IER:
866 mal->ier = val & 0x0000001F;
867 break;
868 case MAL0_TXCASR:
869 mal->txcasr = val & 0xF0000000;
870 break;
871 case MAL0_TXCARR:
872 mal->txcarr = val & 0xF0000000;
873 break;
874 case MAL0_TXEOBISR:
875 /* Read/clear */
876 mal->txeobisr &= ~val;
877 break;
878 case MAL0_TXDEIR:
879 /* Read/clear */
880 mal->txdeir &= ~val;
881 break;
882 case MAL0_RXCASR:
883 mal->rxcasr = val & 0xC0000000;
884 break;
885 case MAL0_RXCARR:
886 mal->rxcarr = val & 0xC0000000;
887 break;
888 case MAL0_RXEOBISR:
889 /* Read/clear */
890 mal->rxeobisr &= ~val;
891 break;
892 case MAL0_RXDEIR:
893 /* Read/clear */
894 mal->rxdeir &= ~val;
895 break;
896 }
897 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
898 mal->txctpr[dcrn - MAL0_TXCTP0R] = val;
899 }
900 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
901 mal->rxctpr[dcrn - MAL0_RXCTP0R] = val;
902 }
903 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
904 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;
905 }
906 }
907
908 void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
909 qemu_irq irqs[4])
910 {
911 ppc4xx_mal_t *mal;
912 int i;
913
914 assert(txcnum <= 32 && rxcnum <= 32);
915 mal = g_malloc0(sizeof(*mal));
916 mal->txcnum = txcnum;
917 mal->rxcnum = rxcnum;
918 mal->txctpr = g_new0(uint32_t, txcnum);
919 mal->rxctpr = g_new0(uint32_t, rxcnum);
920 mal->rcbs = g_new0(uint32_t, rxcnum);
921 for (i = 0; i < 4; i++) {
922 mal->irqs[i] = irqs[i];
923 }
924 qemu_register_reset(&ppc4xx_mal_reset, mal);
925 ppc_dcr_register(env, MAL0_CFG,
926 mal, &dcr_read_mal, &dcr_write_mal);
927 ppc_dcr_register(env, MAL0_ESR,
928 mal, &dcr_read_mal, &dcr_write_mal);
929 ppc_dcr_register(env, MAL0_IER,
930 mal, &dcr_read_mal, &dcr_write_mal);
931 ppc_dcr_register(env, MAL0_TXCASR,
932 mal, &dcr_read_mal, &dcr_write_mal);
933 ppc_dcr_register(env, MAL0_TXCARR,
934 mal, &dcr_read_mal, &dcr_write_mal);
935 ppc_dcr_register(env, MAL0_TXEOBISR,
936 mal, &dcr_read_mal, &dcr_write_mal);
937 ppc_dcr_register(env, MAL0_TXDEIR,
938 mal, &dcr_read_mal, &dcr_write_mal);
939 ppc_dcr_register(env, MAL0_RXCASR,
940 mal, &dcr_read_mal, &dcr_write_mal);
941 ppc_dcr_register(env, MAL0_RXCARR,
942 mal, &dcr_read_mal, &dcr_write_mal);
943 ppc_dcr_register(env, MAL0_RXEOBISR,
944 mal, &dcr_read_mal, &dcr_write_mal);
945 ppc_dcr_register(env, MAL0_RXDEIR,
946 mal, &dcr_read_mal, &dcr_write_mal);
947 for (i = 0; i < txcnum; i++) {
948 ppc_dcr_register(env, MAL0_TXCTP0R + i,
949 mal, &dcr_read_mal, &dcr_write_mal);
950 }
951 for (i = 0; i < rxcnum; i++) {
952 ppc_dcr_register(env, MAL0_RXCTP0R + i,
953 mal, &dcr_read_mal, &dcr_write_mal);
954 }
955 for (i = 0; i < rxcnum; i++) {
956 ppc_dcr_register(env, MAL0_RCBS0 + i,
957 mal, &dcr_read_mal, &dcr_write_mal);
958 }
959 }
AR7 emulation for QEMU