hw/ppc/prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/timer/m48t59.h"
  27 #include "hw/i386/pc.h"
  28 #include "hw/char/serial.h"
  29 #include "hw/block/fdc.h"
  30 #include "net/net.h"
  31 #include "sysemu/sysemu.h"
  32 #include "hw/isa/isa.h"
  33 #include "hw/pci/pci.h"
  34 #include "hw/pci/pci_host.h"
  35 #include "hw/ppc/ppc.h"
  36 #include "hw/boards.h"
  37 #include "qemu/error-report.h"
  38 #include "qemu/log.h"
  39 #include "hw/ide.h"
  40 #include "hw/loader.h"
  41 #include "hw/timer/mc146818rtc.h"
  42 #include "hw/isa/pc87312.h"
  43 #include "sysemu/block-backend.h"
  44 #include "sysemu/arch_init.h"
  45 #include "sysemu/qtest.h"
  46 #include "exec/address-spaces.h"
  47 #include "trace.h"
  48 #include "elf.h"
  49
  50 /* SMP is not enabled, for now */
  51 #define MAX_CPUS 1
  52
  53 #define MAX_IDE_BUS 2
  54
  55 #define BIOS_SIZE (1024 * 1024)
  56 #define BIOS_FILENAME "ppc_rom.bin"
  57 #define KERNEL_LOAD_ADDR 0x01000000
  58 #define INITRD_LOAD_ADDR 0x01800000
  59
  60 /* Constants for devices init */
  61 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  62 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  63 static const int ide_irq[2] = { 13, 13 };
  64
  65 #define NE2000_NB_MAX 6
  66
  67 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  68 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  69
  70 /* ISA IO ports bridge */
  71 #define PPC_IO_BASE 0x80000000
  72
  73 /* PowerPC control and status registers */
  74 #if 0 // Not used
  75 static struct {
  76     /* IDs */
  77     uint32_t veni_devi;
  78     uint32_t revi;
  79     /* Control and status */
  80     uint32_t gcsr;
  81     uint32_t xcfr;
  82     uint32_t ct32;
  83     uint32_t mcsr;
  84     /* General purpose registers */
  85     uint32_t gprg[6];
  86     /* Exceptions */
  87     uint32_t feen;
  88     uint32_t fest;
  89     uint32_t fema;
  90     uint32_t fecl;
  91     uint32_t eeen;
  92     uint32_t eest;
  93     uint32_t eecl;
  94     uint32_t eeint;
  95     uint32_t eemck0;
  96     uint32_t eemck1;
  97     /* Error diagnostic */
  98 } XCSR;
  99
 100 static void PPC_XCSR_writeb (void *opaque,
 101                              hwaddr addr, uint32_t value)
 102 {
 103     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 104            value);
 105 }
 106
 107 static void PPC_XCSR_writew (void *opaque,
 108                              hwaddr addr, uint32_t value)
 109 {
 110     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 111            value);
 112 }
 113
 114 static void PPC_XCSR_writel (void *opaque,
 115                              hwaddr addr, uint32_t value)
 116 {
 117     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 118            value);
 119 }
 120
 121 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
 122 {
 123     uint32_t retval = 0;
 124
 125     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 126            retval);
 127
 128     return retval;
 129 }
 130
 131 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
 132 {
 133     uint32_t retval = 0;
 134
 135     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 136            retval);
 137
 138     return retval;
 139 }
 140
 141 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
 142 {
 143     uint32_t retval = 0;
 144
 145     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 146            retval);
 147
 148     return retval;
 149 }
 150
 151 static const MemoryRegionOps PPC_XCSR_ops = {
 152     .old_mmio = {
 153         .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
 154         .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
 155     },
 156     .endianness = DEVICE_LITTLE_ENDIAN,
 157 };
 158
 159 #endif
 160
 161 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 162 typedef struct sysctrl_t {
 163     qemu_irq reset_irq;
 164     Nvram *nvram;
 165     uint8_t state;
 166     uint8_t syscontrol;
 167     int contiguous_map;
 168     qemu_irq contiguous_map_irq;
 169     int endian;
 170 } sysctrl_t;
 171
 172 enum {
 173     STATE_HARDFILE = 0x01,
 174 };
 175
 176 static sysctrl_t *sysctrl;
 177
 178 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 179 {
 180     sysctrl_t *sysctrl = opaque;
 181
 182     trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
 183     switch (addr) {
 184     case 0x0092:
 185         /* Special port 92 */
 186         /* Check soft reset asked */
 187         if (val & 0x01) {
 188             qemu_irq_raise(sysctrl->reset_irq);
 189         } else {
 190             qemu_irq_lower(sysctrl->reset_irq);
 191         }
 192         /* Check LE mode */
 193         if (val & 0x02) {
 194             sysctrl->endian = 1;
 195         } else {
 196             sysctrl->endian = 0;
 197         }
 198         break;
 199     case 0x0800:
 200         /* Motorola CPU configuration register : read-only */
 201         break;
 202     case 0x0802:
 203         /* Motorola base module feature register : read-only */
 204         break;
 205     case 0x0803:
 206         /* Motorola base module status register : read-only */
 207         break;
 208     case 0x0808:
 209         /* Hardfile light register */
 210         if (val & 1)
 211             sysctrl->state |= STATE_HARDFILE;
 212         else
 213             sysctrl->state &= ~STATE_HARDFILE;
 214         break;
 215     case 0x0810:
 216         /* Password protect 1 register */
 217         if (sysctrl->nvram != NULL) {
 218             NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
 219             (k->toggle_lock)(sysctrl->nvram, 1);
 220         }
 221         break;
 222     case 0x0812:
 223         /* Password protect 2 register */
 224         if (sysctrl->nvram != NULL) {
 225             NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
 226             (k->toggle_lock)(sysctrl->nvram, 2);
 227         }
 228         break;
 229     case 0x0814:
 230         /* L2 invalidate register */
 231         //        tlb_flush(first_cpu, 1);
 232         break;
 233     case 0x081C:
 234         /* system control register */
 235         sysctrl->syscontrol = val & 0x0F;
 236         break;
 237     case 0x0850:
 238         /* I/O map type register */
 239         sysctrl->contiguous_map = val & 0x01;
 240         qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
 241         break;
 242     default:
 243         printf("ERROR: unaffected IO port write: %04" PRIx32
 244                " => %02" PRIx32"\n", addr, val);
 245         break;
 246     }
 247 }
 248
 249 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 250 {
 251     sysctrl_t *sysctrl = opaque;
 252     uint32_t retval = 0xFF;
 253
 254     switch (addr) {
 255     case 0x0092:
 256         /* Special port 92 */
 257         retval = sysctrl->endian << 1;
 258         break;
 259     case 0x0800:
 260         /* Motorola CPU configuration register */
 261         retval = 0xEF; /* MPC750 */
 262         break;
 263     case 0x0802:
 264         /* Motorola Base module feature register */
 265         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 266         break;
 267     case 0x0803:
 268         /* Motorola base module status register */
 269         retval = 0xE0; /* Standard MPC750 */
 270         break;
 271     case 0x080C:
 272         /* Equipment present register:
 273          *  no L2 cache
 274          *  no upgrade processor
 275          *  no cards in PCI slots
 276          *  SCSI fuse is bad
 277          */
 278         retval = 0x3C;
 279         break;
 280     case 0x0810:
 281         /* Motorola base module extended feature register */
 282         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 283         break;
 284     case 0x0814:
 285         /* L2 invalidate: don't care */
 286         break;
 287     case 0x0818:
 288         /* Keylock */
 289         retval = 0x00;
 290         break;
 291     case 0x081C:
 292         /* system control register
 293          * 7 - 6 / 1 - 0: L2 cache enable
 294          */
 295         retval = sysctrl->syscontrol;
 296         break;
 297     case 0x0823:
 298         /* */
 299         retval = 0x03; /* no L2 cache */
 300         break;
 301     case 0x0850:
 302         /* I/O map type register */
 303         retval = sysctrl->contiguous_map;
 304         break;
 305     default:
 306         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 307         break;
 308     }
 309     trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
 310
 311     return retval;
 312 }
 313
 314
 315 #define NVRAM_SIZE        0x2000
 316
 317 static void ppc_prep_reset(void *opaque)
 318 {
 319     PowerPCCPU *cpu = opaque;
 320
 321     cpu_reset(CPU(cpu));
 322 }
 323
 324 static const MemoryRegionPortio prep_portio_list[] = {
 325     /* System control ports */
 326     { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
 327     { 0x0800, 0x52, 1,
 328       .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
 329     /* Special port to get debug messages from Open-Firmware */
 330     { 0x0F00, 4, 1, .write = PPC_debug_write, },
 331     PORTIO_END_OF_LIST(),
 332 };
 333
 334 static PortioList prep_port_list;
 335
 336 /*****************************************************************************/
 337 /* NVRAM helpers */
 338 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
 339 {
 340     NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
 341     return (k->read)(nvram, addr);
 342 }
 343
 344 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
 345 {
 346     NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
 347     (k->write)(nvram, addr, val);
 348 }
 349
 350 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
 351 {
 352     nvram_write(nvram, addr, value);
 353 }
 354
 355 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
 356 {
 357     return nvram_read(nvram, addr);
 358 }
 359
 360 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
 361 {
 362     nvram_write(nvram, addr, value >> 8);
 363     nvram_write(nvram, addr + 1, value & 0xFF);
 364 }
 365
 366 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
 367 {
 368     uint16_t tmp;
 369
 370     tmp = nvram_read(nvram, addr) << 8;
 371     tmp |= nvram_read(nvram, addr + 1);
 372
 373     return tmp;
 374 }
 375
 376 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
 377 {
 378     nvram_write(nvram, addr, value >> 24);
 379     nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
 380     nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
 381     nvram_write(nvram, addr + 3, value & 0xFF);
 382 }
 383
 384 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
 385                              uint32_t max)
 386 {
 387     int i;
 388
 389     for (i = 0; i < max && str[i] != '\0'; i++) {
 390         nvram_write(nvram, addr + i, str[i]);
 391     }
 392     nvram_write(nvram, addr + i, str[i]);
 393     nvram_write(nvram, addr + max - 1, '\0');
 394 }
 395
 396 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 397 {
 398     uint16_t tmp;
 399     uint16_t pd, pd1, pd2;
 400
 401     tmp = prev >> 8;
 402     pd = prev ^ value;
 403     pd1 = pd & 0x000F;
 404     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 405     tmp ^= (pd1 << 3) | (pd1 << 8);
 406     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 407
 408     return tmp;
 409 }
 410
 411 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
 412 {
 413     uint32_t i;
 414     uint16_t crc = 0xFFFF;
 415     int odd;
 416
 417     odd = count & 1;
 418     count &= ~1;
 419     for (i = 0; i != count; i++) {
 420         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 421     }
 422     if (odd) {
 423         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 424     }
 425
 426     return crc;
 427 }
 428
 429 #define CMDLINE_ADDR 0x017ff000
 430
 431 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
 432                           const char *arch,
 433                           uint32_t RAM_size, int boot_device,
 434                           uint32_t kernel_image, uint32_t kernel_size,
 435                           const char *cmdline,
 436                           uint32_t initrd_image, uint32_t initrd_size,
 437                           uint32_t NVRAM_image,
 438                           int width, int height, int depth)
 439 {
 440     uint16_t crc;
 441
 442     /* Set parameters for Open Hack'Ware BIOS */
 443     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 444     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 445     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 446     NVRAM_set_string(nvram, 0x20, arch, 16);
 447     NVRAM_set_lword(nvram,  0x30, RAM_size);
 448     NVRAM_set_byte(nvram,   0x34, boot_device);
 449     NVRAM_set_lword(nvram,  0x38, kernel_image);
 450     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 451     if (cmdline) {
 452         /* XXX: put the cmdline in NVRAM too ? */
 453         pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
 454                          cmdline);
 455         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 456         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 457     } else {
 458         NVRAM_set_lword(nvram,  0x40, 0);
 459         NVRAM_set_lword(nvram,  0x44, 0);
 460     }
 461     NVRAM_set_lword(nvram,  0x48, initrd_image);
 462     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 463     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 464
 465     NVRAM_set_word(nvram,   0x54, width);
 466     NVRAM_set_word(nvram,   0x56, height);
 467     NVRAM_set_word(nvram,   0x58, depth);
 468     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 469     NVRAM_set_word(nvram,   0xFC, crc);
 470
 471     return 0;
 472 }
 473
 474 /* PowerPC PREP hardware initialisation */
 475 static void ppc_prep_init(MachineState *machine)
 476 {
 477     ram_addr_t ram_size = machine->ram_size;
 478     const char *kernel_filename = machine->kernel_filename;
 479     const char *kernel_cmdline = machine->kernel_cmdline;
 480     const char *initrd_filename = machine->initrd_filename;
 481     const char *boot_device = machine->boot_order;
 482     MemoryRegion *sysmem = get_system_memory();
 483     PowerPCCPU *cpu = NULL;
 484     CPUPPCState *env = NULL;
 485     Nvram *m48t59;
 486 #if 0
 487     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 488 #endif
 489     int linux_boot, i, nb_nics1;
 490     MemoryRegion *ram = g_new(MemoryRegion, 1);
 491     uint32_t kernel_base, initrd_base;
 492     long kernel_size, initrd_size;
 493     DeviceState *dev;
 494     PCIHostState *pcihost;
 495     PCIBus *pci_bus;
 496     PCIDevice *pci;
 497     ISABus *isa_bus;
 498     ISADevice *isa;
 499     int ppc_boot_device;
 500     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 501
 502     sysctrl = g_malloc0(sizeof(sysctrl_t));
 503
 504     linux_boot = (kernel_filename != NULL);
 505
 506     /* init CPUs */
 507     if (machine->cpu_model == NULL)
 508         machine->cpu_model = "602";
 509     for (i = 0; i < smp_cpus; i++) {
 510         cpu = cpu_ppc_init(machine->cpu_model);
 511         if (cpu == NULL) {
 512             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 513             exit(1);
 514         }
 515         env = &cpu->env;
 516
 517         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 518             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 519             cpu_ppc_tb_init(env, 7812500UL);
 520         } else {
 521             /* Set time-base frequency to 100 Mhz */
 522             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 523         }
 524         qemu_register_reset(ppc_prep_reset, cpu);
 525     }
 526
 527     /* allocate RAM */
 528     memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
 529     memory_region_add_subregion(sysmem, 0, ram);
 530
 531     if (linux_boot) {
 532         kernel_base = KERNEL_LOAD_ADDR;
 533         /* now we can load the kernel */
 534         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 535                                           ram_size - kernel_base);
 536         if (kernel_size < 0) {
 537             error_report("could not load kernel '%s'", kernel_filename);
 538             exit(1);
 539         }
 540         /* load initrd */
 541         if (initrd_filename) {
 542             initrd_base = INITRD_LOAD_ADDR;
 543             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 544                                               ram_size - initrd_base);
 545             if (initrd_size < 0) {
 546                 error_report("could not load initial ram disk '%s'",
 547                              initrd_filename);
 548                 exit(1);
 549             }
 550         } else {
 551             initrd_base = 0;
 552             initrd_size = 0;
 553         }
 554         ppc_boot_device = 'm';
 555     } else {
 556         kernel_base = 0;
 557         kernel_size = 0;
 558         initrd_base = 0;
 559         initrd_size = 0;
 560         ppc_boot_device = '\0';
 561         /* For now, OHW cannot boot from the network. */
 562         for (i = 0; boot_device[i] != '\0'; i++) {
 563             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 564                 ppc_boot_device = boot_device[i];
 565                 break;
 566             }
 567         }
 568         if (ppc_boot_device == '\0') {
 569             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 570             exit(1);
 571         }
 572     }
 573
 574     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 575         error_report("Only 6xx bus is supported on PREP machine");
 576         exit(1);
 577     }
 578
 579     dev = qdev_create(NULL, "raven-pcihost");
 580     if (bios_name == NULL) {
 581         bios_name = BIOS_FILENAME;
 582     }
 583     qdev_prop_set_string(dev, "bios-name", bios_name);
 584     qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
 585     pcihost = PCI_HOST_BRIDGE(dev);
 586     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 587     qdev_init_nofail(dev);
 588     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 589     if (pci_bus == NULL) {
 590         fprintf(stderr, "Couldn't create PCI host controller.\n");
 591         exit(1);
 592     }
 593     sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
 594
 595     /* PCI -> ISA bridge */
 596     pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
 597     cpu = POWERPC_CPU(first_cpu);
 598     qdev_connect_gpio_out(&pci->qdev, 0,
 599                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
 600     sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
 601     sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
 602     sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
 603     sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
 604     isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
 605
 606     /* Super I/O (parallel + serial ports) */
 607     isa = isa_create(isa_bus, TYPE_PC87312);
 608     dev = DEVICE(isa);
 609     qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
 610     qdev_init_nofail(dev);
 611
 612     /* init basic PC hardware */
 613     pci_vga_init(pci_bus);
 614
 615     nb_nics1 = nb_nics;
 616     if (nb_nics1 > NE2000_NB_MAX)
 617         nb_nics1 = NE2000_NB_MAX;
 618     for(i = 0; i < nb_nics1; i++) {
 619         if (nd_table[i].model == NULL) {
 620             nd_table[i].model = g_strdup("ne2k_isa");
 621         }
 622         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 623             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 624                             &nd_table[i]);
 625         } else {
 626             pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 627         }
 628     }
 629
 630     ide_drive_get(hd, ARRAY_SIZE(hd));
 631     for(i = 0; i < MAX_IDE_BUS; i++) {
 632         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 633                      hd[2 * i],
 634                      hd[2 * i + 1]);
 635     }
 636     isa_create_simple(isa_bus, "i8042");
 637
 638     cpu = POWERPC_CPU(first_cpu);
 639     sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
 640
 641     portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
 642     portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
 643
 644     /* PowerPC control and status register group */
 645 #if 0
 646     memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
 647     memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
 648 #endif
 649
 650     if (usb_enabled()) {
 651         pci_create_simple(pci_bus, -1, "pci-ohci");
 652     }
 653
 654     m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
 655     if (m48t59 == NULL)
 656         return;
 657     sysctrl->nvram = m48t59;
 658
 659     /* Initialise NVRAM */
 660     PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
 661                          ppc_boot_device,
 662                          kernel_base, kernel_size,
 663                          kernel_cmdline,
 664                          initrd_base, initrd_size,
 665                          /* XXX: need an option to load a NVRAM image */
 666                          0,
 667                          graphic_width, graphic_height, graphic_depth);
 668 }
 669
 670 static void prep_machine_init(MachineClass *mc)
 671 {
 672     mc->desc = "PowerPC PREP platform";
 673     mc->init = ppc_prep_init;
 674     mc->max_cpus = MAX_CPUS;
 675     mc->default_boot_order = "cad";
 676 }
 677
 678 DEFINE_MACHINE("prep", prep_machine_init)