target/tricore/cpu.c

   1 /*
   2  *  TriCore emulation for qemu: main translation routines.
   3  *
   4  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "exec/exec-all.h"
  24 #include "qemu/error-report.h"
  25 #include "tcg/debug-assert.h"
  26
  27 static inline void set_feature(CPUTriCoreState *env, int feature)
  28 {
  29     env->features |= 1ULL << feature;
  30 }
  31
  32 static const gchar *tricore_gdb_arch_name(CPUState *cs)
  33 {
  34     return "tricore";
  35 }
  36
  37 static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
  38 {
  39     cpu_env(cs)->PC = value & ~(target_ulong)1;
  40 }
  41
  42 static vaddr tricore_cpu_get_pc(CPUState *cs)
  43 {
  44     return cpu_env(cs)->PC;
  45 }
  46
  47 static void tricore_cpu_synchronize_from_tb(CPUState *cs,
  48                                             const TranslationBlock *tb)
  49 {
  50     tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
  51     cpu_env(cs)->PC = tb->pc;
  52 }
  53
  54 static void tricore_restore_state_to_opc(CPUState *cs,
  55                                          const TranslationBlock *tb,
  56                                          const uint64_t *data)
  57 {
  58     cpu_env(cs)->PC = data[0];
  59 }
  60
  61 static void tricore_cpu_reset_hold(Object *obj, ResetType type)
  62 {
  63     CPUState *cs = CPU(obj);
  64     TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj);
  65
  66     if (tcc->parent_phases.hold) {
  67         tcc->parent_phases.hold(obj, type);
  68     }
  69
  70     cpu_state_reset(cpu_env(cs));
  71 }
  72
  73 static bool tricore_cpu_has_work(CPUState *cs)
  74 {
  75     return true;
  76 }
  77
  78 static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch)
  79 {
  80     return 0;
  81 }
  82
  83 static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
  84 {
  85     CPUState *cs = CPU(dev);
  86     TriCoreCPU *cpu = TRICORE_CPU(dev);
  87     TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
  88     CPUTriCoreState *env = &cpu->env;
  89     Error *local_err = NULL;
  90
  91     cpu_exec_realizefn(cs, &local_err);
  92     if (local_err != NULL) {
  93         error_propagate(errp, local_err);
  94         return;
  95     }
  96
  97     /* Some features automatically imply others */
  98     if (tricore_has_feature(env, TRICORE_FEATURE_162)) {
  99         set_feature(env, TRICORE_FEATURE_161);
 100     }
 101
 102     if (tricore_has_feature(env, TRICORE_FEATURE_161)) {
 103         set_feature(env, TRICORE_FEATURE_16);
 104     }
 105
 106     if (tricore_has_feature(env, TRICORE_FEATURE_16)) {
 107         set_feature(env, TRICORE_FEATURE_131);
 108     }
 109     if (tricore_has_feature(env, TRICORE_FEATURE_131)) {
 110         set_feature(env, TRICORE_FEATURE_13);
 111     }
 112     cpu_reset(cs);
 113     qemu_init_vcpu(cs);
 114
 115     tcc->parent_realize(dev, errp);
 116 }
 117
 118 static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
 119 {
 120     ObjectClass *oc;
 121     char *typename;
 122
 123     typename = g_strdup_printf(TRICORE_CPU_TYPE_NAME("%s"), cpu_model);
 124     oc = object_class_by_name(typename);
 125     g_free(typename);
 126
 127     return oc;
 128 }
 129
 130 static void tc1796_initfn(Object *obj)
 131 {
 132     TriCoreCPU *cpu = TRICORE_CPU(obj);
 133
 134     set_feature(&cpu->env, TRICORE_FEATURE_13);
 135 }
 136
 137 static void tc1797_initfn(Object *obj)
 138 {
 139     TriCoreCPU *cpu = TRICORE_CPU(obj);
 140
 141     set_feature(&cpu->env, TRICORE_FEATURE_131);
 142 }
 143
 144 static void tc27x_initfn(Object *obj)
 145 {
 146     TriCoreCPU *cpu = TRICORE_CPU(obj);
 147
 148     set_feature(&cpu->env, TRICORE_FEATURE_161);
 149 }
 150
 151 static void tc37x_initfn(Object *obj)
 152 {
 153     TriCoreCPU *cpu = TRICORE_CPU(obj);
 154
 155     set_feature(&cpu->env, TRICORE_FEATURE_162);
 156 }
 157
 158 static bool tricore_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 159 {
 160     /* Interrupts are not implemented */
 161     return false;
 162 }
 163
 164 #include "hw/core/sysemu-cpu-ops.h"
 165
 166 static const struct SysemuCPUOps tricore_sysemu_ops = {
 167     .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
 168 };
 169
 170 #include "hw/core/tcg-cpu-ops.h"
 171
 172 static const TCGCPUOps tricore_tcg_ops = {
 173     .initialize = tricore_tcg_init,
 174     .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
 175     .restore_state_to_opc = tricore_restore_state_to_opc,
 176     .tlb_fill = tricore_cpu_tlb_fill,
 177     .cpu_exec_interrupt = tricore_cpu_exec_interrupt,
 178     .cpu_exec_halt = tricore_cpu_has_work,
 179 };
 180
 181 static void tricore_cpu_class_init(ObjectClass *c, void *data)
 182 {
 183     TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c);
 184     CPUClass *cc = CPU_CLASS(c);
 185     DeviceClass *dc = DEVICE_CLASS(c);
 186     ResettableClass *rc = RESETTABLE_CLASS(c);
 187
 188     device_class_set_parent_realize(dc, tricore_cpu_realizefn,
 189                                     &mcc->parent_realize);
 190
 191     resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL,
 192                                        &mcc->parent_phases);
 193     cc->class_by_name = tricore_cpu_class_by_name;
 194     cc->has_work = tricore_cpu_has_work;
 195     cc->mmu_index = tricore_cpu_mmu_index;
 196
 197     cc->gdb_read_register = tricore_cpu_gdb_read_register;
 198     cc->gdb_write_register = tricore_cpu_gdb_write_register;
 199     cc->gdb_num_core_regs = 44;
 200     cc->gdb_arch_name = tricore_gdb_arch_name;
 201
 202     cc->dump_state = tricore_cpu_dump_state;
 203     cc->set_pc = tricore_cpu_set_pc;
 204     cc->get_pc = tricore_cpu_get_pc;
 205     cc->sysemu_ops = &tricore_sysemu_ops;
 206     cc->tcg_ops = &tricore_tcg_ops;
 207 }
 208
 209 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
 210     {                                              \
 211         .parent = TYPE_TRICORE_CPU,                \
 212         .instance_init = initfn,                   \
 213         .name = TRICORE_CPU_TYPE_NAME(cpu_model),  \
 214     }
 215
 216 static const TypeInfo tricore_cpu_type_infos[] = {
 217     {
 218         .name = TYPE_TRICORE_CPU,
 219         .parent = TYPE_CPU,
 220         .instance_size = sizeof(TriCoreCPU),
 221         .instance_align = __alignof(TriCoreCPU),
 222         .abstract = true,
 223         .class_size = sizeof(TriCoreCPUClass),
 224         .class_init = tricore_cpu_class_init,
 225     },
 226     DEFINE_TRICORE_CPU_TYPE("tc1796", tc1796_initfn),
 227     DEFINE_TRICORE_CPU_TYPE("tc1797", tc1797_initfn),
 228     DEFINE_TRICORE_CPU_TYPE("tc27x", tc27x_initfn),
 229     DEFINE_TRICORE_CPU_TYPE("tc37x", tc37x_initfn),
 230 };
 231
 232 DEFINE_TYPES(tricore_cpu_type_infos)