Merge tag 'v9.0.0-rc3'
[qemu/ar7.git] / target / i386 / cpu-dump.c
blob40697064d92ec6584720c49c0cd48b3a82ff691f
1 /*
2 * i386 CPU dump to FILE
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "qemu/qemu-print.h"
23 #ifndef CONFIG_USER_ONLY
24 #include "hw/i386/apic_internal.h"
25 #endif
27 /***********************************************************/
28 /* x86 debug */
30 static const char *cc_op_str[CC_OP_NB] = {
31 "DYNAMIC",
32 "EFLAGS",
34 "MULB",
35 "MULW",
36 "MULL",
37 "MULQ",
39 "ADDB",
40 "ADDW",
41 "ADDL",
42 "ADDQ",
44 "ADCB",
45 "ADCW",
46 "ADCL",
47 "ADCQ",
49 "SUBB",
50 "SUBW",
51 "SUBL",
52 "SUBQ",
54 "SBBB",
55 "SBBW",
56 "SBBL",
57 "SBBQ",
59 "LOGICB",
60 "LOGICW",
61 "LOGICL",
62 "LOGICQ",
64 "INCB",
65 "INCW",
66 "INCL",
67 "INCQ",
69 "DECB",
70 "DECW",
71 "DECL",
72 "DECQ",
74 "SHLB",
75 "SHLW",
76 "SHLL",
77 "SHLQ",
79 "SARB",
80 "SARW",
81 "SARL",
82 "SARQ",
84 "BMILGB",
85 "BMILGW",
86 "BMILGL",
87 "BMILGQ",
89 "ADCX",
90 "ADOX",
91 "ADCOX",
93 "CLR",
96 static void
97 cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f,
98 const char *name, struct SegmentCache *sc)
100 #ifdef TARGET_X86_64
101 if (env->hflags & HF_CS64_MASK) {
102 qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
103 sc->selector, sc->base, sc->limit,
104 sc->flags & 0x00ffff00);
105 } else
106 #endif
108 qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
109 (uint32_t)sc->base, sc->limit,
110 sc->flags & 0x00ffff00);
113 if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
114 goto done;
116 qemu_fprintf(f, " DPL=%d ",
117 (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
118 if (sc->flags & DESC_S_MASK) {
119 if (sc->flags & DESC_CS_MASK) {
120 qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
121 ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
122 qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
123 (sc->flags & DESC_R_MASK) ? 'R' : '-');
124 } else {
125 qemu_fprintf(f, (sc->flags & DESC_B_MASK
126 || env->hflags & HF_LMA_MASK)
127 ? "DS " : "DS16");
128 qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
129 (sc->flags & DESC_W_MASK) ? 'W' : '-');
131 qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
132 } else {
133 static const char *sys_type_name[2][16] = {
134 { /* 32 bit mode */
135 "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
136 "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
137 "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
138 "CallGate32", "Reserved", "IntGate32", "TrapGate32"
140 { /* 64 bit mode */
141 "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
142 "Reserved", "Reserved", "Reserved", "Reserved",
143 "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
144 "Reserved", "IntGate64", "TrapGate64"
147 qemu_fprintf(f, "%s",
148 sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
149 [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]);
151 done:
152 qemu_fprintf(f, "\n");
155 #ifndef CONFIG_USER_ONLY
157 /* ARRAY_SIZE check is not required because
158 * DeliveryMode(dm) has a size of 3 bit.
160 static inline const char *dm2str(uint32_t dm)
162 static const char *str[] = {
163 "Fixed",
164 "...",
165 "SMI",
166 "...",
167 "NMI",
168 "INIT",
169 "...",
170 "ExtINT"
172 return str[dm];
175 static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer)
177 uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT;
178 qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s",
179 name, lvt,
180 lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi",
181 lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge",
182 lvt & APIC_LVT_MASKED ? "masked" : "",
183 lvt & APIC_LVT_DELIV_STS ? "pending" : "",
184 !is_timer ?
185 "" : lvt & APIC_LVT_TIMER_PERIODIC ?
186 "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ?
187 "tsc-deadline" : "one-shot",
188 dm2str(dm));
189 if (dm != APIC_DM_NMI) {
190 qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK);
191 } else {
192 qemu_printf("\n");
196 /* ARRAY_SIZE check is not required because
197 * destination shorthand has a size of 2 bit.
199 static inline const char *shorthand2str(uint32_t shorthand)
201 const char *str[] = {
202 "no-shorthand", "self", "all-self", "all"
204 return str[shorthand];
207 static inline uint8_t divider_conf(uint32_t divide_conf)
209 uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3);
211 return divide_val == 7 ? 1 : 2 << divide_val;
214 static inline void mask2str(char *str, uint32_t val, uint8_t size)
216 while (size--) {
217 *str++ = (val >> size) & 1 ? '1' : '0';
219 *str = 0;
222 #define MAX_LOGICAL_APIC_ID_MASK_SIZE 16
224 static void dump_apic_icr(APICCommonState *s, CPUX86State *env)
226 uint32_t icr = s->icr[0], icr2 = s->icr[1];
227 uint8_t dest_shorthand = \
228 (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT;
229 bool logical_mod = icr & APIC_ICR_DEST_MOD;
230 char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1];
231 uint32_t dest_field;
232 bool x2apic;
234 qemu_printf("ICR\t 0x%08x %s %s %s %s\n",
235 icr,
236 logical_mod ? "logical" : "physical",
237 icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge",
238 icr & APIC_ICR_LEVEL ? "assert" : "de-assert",
239 shorthand2str(dest_shorthand));
241 qemu_printf("ICR2\t 0x%08x", icr2);
242 if (dest_shorthand != 0) {
243 qemu_printf("\n");
244 return;
246 x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC;
247 dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT;
249 if (!logical_mod) {
250 if (x2apic) {
251 qemu_printf(" cpu %u (X2APIC ID)\n", dest_field);
252 } else {
253 qemu_printf(" cpu %u (APIC ID)\n",
254 dest_field & APIC_LOGDEST_XAPIC_ID);
256 return;
259 if (s->dest_mode == 0xf) { /* flat mode */
260 mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8);
261 qemu_printf(" mask %s (APIC ID)\n", apic_id_str);
262 } else if (s->dest_mode == 0) { /* cluster mode */
263 if (x2apic) {
264 mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16);
265 qemu_printf(" cluster %u mask %s (X2APIC ID)\n",
266 dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str);
267 } else {
268 mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4);
269 qemu_printf(" cluster %u mask %s (APIC ID)\n",
270 dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str);
275 static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab,
276 uint32_t *tmr_tab)
278 int i, empty = true;
280 qemu_printf("%s\t ", name);
281 for (i = 0; i < 256; i++) {
282 if (apic_get_bit(ireg_tab, i)) {
283 qemu_printf("%u%s ", i,
284 apic_get_bit(tmr_tab, i) ? "(level)" : "");
285 empty = false;
288 qemu_printf("%s\n", empty ? "(none)" : "");
291 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
293 X86CPU *cpu = X86_CPU(cs);
294 APICCommonState *s = APIC_COMMON(cpu->apic_state);
295 if (!s) {
296 qemu_printf("local apic state not available\n");
297 return;
299 uint32_t *lvt = s->lvt;
301 qemu_printf("dumping local APIC state for CPU %-2u\n\n",
302 CPU(cpu)->cpu_index);
303 dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false);
304 dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false);
305 dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false);
306 dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false);
307 dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false);
308 dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true);
310 qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u"
311 " current_count = %u\n",
312 s->divide_conf & APIC_DCR_MASK,
313 divider_conf(s->divide_conf),
314 s->initial_count, apic_get_current_count(s));
316 qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n",
317 s->spurious_vec,
318 s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled",
319 s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off",
320 s->spurious_vec & APIC_VECTOR_MASK);
322 dump_apic_icr(s, &cpu->env);
324 qemu_printf("ESR\t 0x%08x\n", s->esr);
326 dump_apic_interrupt("ISR", s->isr, s->tmr);
327 dump_apic_interrupt("IRR", s->irr, s->tmr);
329 qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x",
330 s->arb_id, s->tpr, s->dest_mode, s->log_dest);
331 if (s->dest_mode == 0) {
332 qemu_printf("(cluster %u: id %u)",
333 s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT,
334 s->log_dest & APIC_LOGDEST_XAPIC_ID);
336 qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s));
339 #endif /* !CONFIG_USER_ONLY */
341 #define DUMP_CODE_BYTES_TOTAL 50
342 #define DUMP_CODE_BYTES_BACKWARD 20
344 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
346 X86CPU *cpu = X86_CPU(cs);
347 CPUX86State *env = &cpu->env;
348 int eflags, i, nb;
349 char cc_op_name[32];
350 static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
352 eflags = cpu_compute_eflags(env);
353 #ifdef TARGET_X86_64
354 if (env->hflags & HF_CS64_MASK) {
355 qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
356 "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
357 "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
358 "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
359 "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
360 env->regs[R_EAX],
361 env->regs[R_EBX],
362 env->regs[R_ECX],
363 env->regs[R_EDX],
364 env->regs[R_ESI],
365 env->regs[R_EDI],
366 env->regs[R_EBP],
367 env->regs[R_ESP],
368 env->regs[8],
369 env->regs[9],
370 env->regs[10],
371 env->regs[11],
372 env->regs[12],
373 env->regs[13],
374 env->regs[14],
375 env->regs[15],
376 env->eip, eflags,
377 eflags & DF_MASK ? 'D' : '-',
378 eflags & CC_O ? 'O' : '-',
379 eflags & CC_S ? 'S' : '-',
380 eflags & CC_Z ? 'Z' : '-',
381 eflags & CC_A ? 'A' : '-',
382 eflags & CC_P ? 'P' : '-',
383 eflags & CC_C ? 'C' : '-',
384 env->hflags & HF_CPL_MASK,
385 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
386 (env->a20_mask >> 20) & 1,
387 (env->hflags >> HF_SMM_SHIFT) & 1,
388 cs->halted);
389 } else
390 #endif
392 qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
393 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
394 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
395 (uint32_t)env->regs[R_EAX],
396 (uint32_t)env->regs[R_EBX],
397 (uint32_t)env->regs[R_ECX],
398 (uint32_t)env->regs[R_EDX],
399 (uint32_t)env->regs[R_ESI],
400 (uint32_t)env->regs[R_EDI],
401 (uint32_t)env->regs[R_EBP],
402 (uint32_t)env->regs[R_ESP],
403 (uint32_t)env->eip, eflags,
404 eflags & DF_MASK ? 'D' : '-',
405 eflags & CC_O ? 'O' : '-',
406 eflags & CC_S ? 'S' : '-',
407 eflags & CC_Z ? 'Z' : '-',
408 eflags & CC_A ? 'A' : '-',
409 eflags & CC_P ? 'P' : '-',
410 eflags & CC_C ? 'C' : '-',
411 env->hflags & HF_CPL_MASK,
412 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
413 (env->a20_mask >> 20) & 1,
414 (env->hflags >> HF_SMM_SHIFT) & 1,
415 cs->halted);
418 for(i = 0; i < 6; i++) {
419 cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]);
421 cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt);
422 cpu_x86_dump_seg_cache(env, f, "TR", &env->tr);
424 #ifdef TARGET_X86_64
425 if (env->hflags & HF_LMA_MASK) {
426 qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
427 env->gdt.base, env->gdt.limit);
428 qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
429 env->idt.base, env->idt.limit);
430 qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
431 (uint32_t)env->cr[0],
432 env->cr[2],
433 env->cr[3],
434 (uint32_t)env->cr[4]);
435 for(i = 0; i < 4; i++)
436 qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
437 qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
438 env->dr[6], env->dr[7]);
439 } else
440 #endif
442 qemu_fprintf(f, "GDT= %08x %08x\n",
443 (uint32_t)env->gdt.base, env->gdt.limit);
444 qemu_fprintf(f, "IDT= %08x %08x\n",
445 (uint32_t)env->idt.base, env->idt.limit);
446 qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
447 (uint32_t)env->cr[0],
448 (uint32_t)env->cr[2],
449 (uint32_t)env->cr[3],
450 (uint32_t)env->cr[4]);
451 for(i = 0; i < 4; i++) {
452 qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
454 qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
455 env->dr[6], env->dr[7]);
457 if (flags & CPU_DUMP_CCOP) {
458 if ((unsigned)env->cc_op < CC_OP_NB)
459 snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
460 else
461 snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
462 #ifdef TARGET_X86_64
463 if (env->hflags & HF_CS64_MASK) {
464 qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%s\n",
465 env->cc_src, env->cc_dst,
466 cc_op_name);
467 } else
468 #endif
470 qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%s\n",
471 (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
472 cc_op_name);
475 qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
476 if (flags & CPU_DUMP_FPU) {
477 int fptag;
478 const uint64_t avx512_mask = XSTATE_OPMASK_MASK | \
479 XSTATE_ZMM_Hi256_MASK | \
480 XSTATE_Hi16_ZMM_MASK | \
481 XSTATE_YMM_MASK | XSTATE_SSE_MASK,
482 avx_mask = XSTATE_YMM_MASK | XSTATE_SSE_MASK;
483 fptag = 0;
484 for(i = 0; i < 8; i++) {
485 fptag |= ((!env->fptags[i]) << i);
487 update_mxcsr_from_sse_status(env);
488 qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
489 env->fpuc,
490 (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
491 env->fpstt,
492 fptag,
493 env->mxcsr);
494 for(i=0;i<8;i++) {
495 CPU_LDoubleU u;
496 u.d = env->fpregs[i].d;
497 qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
498 i, u.l.lower, u.l.upper);
499 if ((i & 1) == 1)
500 qemu_fprintf(f, "\n");
501 else
502 qemu_fprintf(f, " ");
505 if ((env->xcr0 & avx512_mask) == avx512_mask) {
506 /* XSAVE enabled AVX512 */
507 for (i = 0; i < NB_OPMASK_REGS; i++) {
508 qemu_fprintf(f, "Opmask%02d=%016"PRIx64"%s", i,
509 env->opmask_regs[i], ((i & 3) == 3) ? "\n" : " ");
512 nb = (env->hflags & HF_CS64_MASK) ? 32 : 8;
513 for (i = 0; i < nb; i++) {
514 qemu_fprintf(f, "ZMM%02d=%016"PRIx64" %016"PRIx64" %016"PRIx64
515 " %016"PRIx64" %016"PRIx64" %016"PRIx64
516 " %016"PRIx64" %016"PRIx64"\n",
518 env->xmm_regs[i].ZMM_Q(7),
519 env->xmm_regs[i].ZMM_Q(6),
520 env->xmm_regs[i].ZMM_Q(5),
521 env->xmm_regs[i].ZMM_Q(4),
522 env->xmm_regs[i].ZMM_Q(3),
523 env->xmm_regs[i].ZMM_Q(2),
524 env->xmm_regs[i].ZMM_Q(1),
525 env->xmm_regs[i].ZMM_Q(0));
527 } else if ((env->xcr0 & avx_mask) == avx_mask) {
528 /* XSAVE enabled AVX */
529 nb = env->hflags & HF_CS64_MASK ? 16 : 8;
530 for (i = 0; i < nb; i++) {
531 qemu_fprintf(f, "YMM%02d=%016"PRIx64" %016"PRIx64" %016"PRIx64
532 " %016"PRIx64"\n", i,
533 env->xmm_regs[i].ZMM_Q(3),
534 env->xmm_regs[i].ZMM_Q(2),
535 env->xmm_regs[i].ZMM_Q(1),
536 env->xmm_regs[i].ZMM_Q(0));
538 } else { /* SSE and below cases */
539 nb = env->hflags & HF_CS64_MASK ? 16 : 8;
540 for (i = 0; i < nb; i++) {
541 qemu_fprintf(f, "XMM%02d=%016"PRIx64" %016"PRIx64"%s",
543 env->xmm_regs[i].ZMM_Q(1),
544 env->xmm_regs[i].ZMM_Q(0),
545 (i & 1) ? "\n" : " ");
549 if (flags & CPU_DUMP_CODE) {
550 target_ulong base = env->segs[R_CS].base + env->eip;
551 target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
552 uint8_t code;
553 char codestr[3];
555 qemu_fprintf(f, "Code=");
556 for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
557 if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
558 snprintf(codestr, sizeof(codestr), "%02x", code);
559 } else {
560 snprintf(codestr, sizeof(codestr), "??");
562 qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
563 i == offs ? "<" : "", codestr, i == offs ? ">" : "");
565 qemu_fprintf(f, "\n");