target/hppa/int_helper.c

   1 /*
   2  *  HPPA interrupt helper routines
   3  *
   4  *  Copyright (c) 2017 Richard Henderson
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/main-loop.h"
  22 #include "qemu/log.h"
  23 #include "cpu.h"
  24 #include "exec/helper-proto.h"
  25 #include "hw/core/cpu.h"
  26 #include "hw/hppa/hppa_hardware.h"
  27
  28 static void eval_interrupt(HPPACPU *cpu)
  29 {
  30     CPUState *cs = CPU(cpu);
  31     if (cpu->env.cr[CR_EIRR]) {
  32         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  33     } else {
  34         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  35     }
  36 }
  37
  38 /* Each CPU has a word mapped into the GSC bus.  Anything on the GSC bus
  39  * can write to this word to raise an external interrupt on the target CPU.
  40  * This includes the system controller (DINO) for regular devices, or
  41  * another CPU for SMP interprocessor interrupts.
  42  */
  43 static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size)
  44 {
  45     HPPACPU *cpu = opaque;
  46
  47     /* ??? What does a read of this register over the GSC bus do?  */
  48     return cpu->env.cr[CR_EIRR];
  49 }
  50
  51 static void io_eir_write(void *opaque, hwaddr addr,
  52                          uint64_t data, unsigned size)
  53 {
  54     HPPACPU *cpu = opaque;
  55     CPUHPPAState *env = &cpu->env;
  56     int widthm1 = 31;
  57     int le_bit;
  58
  59     /* The default PSW.W controls the width of EIRR. */
  60     if (hppa_is_pa20(env) && env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) {
  61         widthm1 = 63;
  62     }
  63     le_bit = ~data & widthm1;
  64
  65     env->cr[CR_EIRR] |= 1ull << le_bit;
  66     eval_interrupt(cpu);
  67 }
  68
  69 const MemoryRegionOps hppa_io_eir_ops = {
  70     .read = io_eir_read,
  71     .write = io_eir_write,
  72     .valid.min_access_size = 4,
  73     .valid.max_access_size = 4,
  74     .impl.min_access_size = 4,
  75     .impl.max_access_size = 4,
  76 };
  77
  78 void hppa_cpu_alarm_timer(void *opaque)
  79 {
  80     /* Raise interrupt 0.  */
  81     io_eir_write(opaque, 0, 0, 4);
  82 }
  83
  84 void HELPER(write_eirr)(CPUHPPAState *env, target_ulong val)
  85 {
  86     env->cr[CR_EIRR] &= ~val;
  87     bql_lock();
  88     eval_interrupt(env_archcpu(env));
  89     bql_unlock();
  90 }
  91
  92 void hppa_cpu_do_interrupt(CPUState *cs)
  93 {
  94     HPPACPU *cpu = HPPA_CPU(cs);
  95     CPUHPPAState *env = &cpu->env;
  96     int i = cs->exception_index;
  97     uint64_t old_psw;
  98
  99     /* As documented in pa2.0 -- interruption handling.  */
 100     /* step 1 */
 101     env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env);
 102
 103     /* step 2 -- Note PSW_W is masked out again for pa1.x */
 104     cpu_hppa_put_psw(env,
 105                      (env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W : 0) |
 106                      (i == EXCP_HPMC ? PSW_M : 0));
 107
 108     /* step 3 */
 109     /*
 110      * IIASQ is the top bits of the virtual address, or zero if translation
 111      * is disabled -- with PSW_W == 0, this will reduce to the space.
 112      */
 113     if (old_psw & PSW_C) {
 114         env->cr[CR_IIASQ] =
 115             hppa_form_gva_psw(old_psw, env->iasq_f, env->iaoq_f) >> 32;
 116         env->cr_back[0] =
 117             hppa_form_gva_psw(old_psw, env->iasq_b, env->iaoq_b) >> 32;
 118     } else {
 119         env->cr[CR_IIASQ] = 0;
 120         env->cr_back[0] = 0;
 121     }
 122     /* IIAOQ is the full offset for wide mode, or 32 bits for narrow mode. */
 123     if (old_psw & PSW_W) {
 124         env->cr[CR_IIAOQ] = env->iaoq_f;
 125         env->cr_back[1] = env->iaoq_b;
 126     } else {
 127         env->cr[CR_IIAOQ] = (uint32_t)env->iaoq_f;
 128         env->cr_back[1] = (uint32_t)env->iaoq_b;
 129     }
 130
 131     if (old_psw & PSW_Q) {
 132         /* step 5 */
 133         /* ISR and IOR will be set elsewhere.  */
 134         switch (i) {
 135         case EXCP_ILL:
 136         case EXCP_BREAK:
 137         case EXCP_PRIV_REG:
 138         case EXCP_PRIV_OPR:
 139             /* IIR set via translate.c.  */
 140             break;
 141
 142         case EXCP_OVERFLOW:
 143         case EXCP_COND:
 144         case EXCP_ASSIST:
 145         case EXCP_DTLB_MISS:
 146         case EXCP_NA_ITLB_MISS:
 147         case EXCP_NA_DTLB_MISS:
 148         case EXCP_DMAR:
 149         case EXCP_DMPI:
 150         case EXCP_UNALIGN:
 151         case EXCP_DMP:
 152         case EXCP_DMB:
 153         case EXCP_TLB_DIRTY:
 154         case EXCP_PAGE_REF:
 155         case EXCP_ASSIST_EMU:
 156             {
 157                 /* Avoid reading directly from the virtual address, lest we
 158                    raise another exception from some sort of TLB issue.  */
 159                 /* ??? An alternate fool-proof method would be to store the
 160                    instruction data into the unwind info.  That's probably
 161                    a bit too much in the way of extra storage required.  */
 162                 vaddr vaddr = env->iaoq_f & -4;
 163                 hwaddr paddr = vaddr;
 164
 165                 if (old_psw & PSW_C) {
 166                     int prot, t;
 167
 168                     vaddr = hppa_form_gva_psw(old_psw, env->iasq_f, vaddr);
 169                     t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX,
 170                                                   0, &paddr, &prot, NULL);
 171                     if (t >= 0) {
 172                         /* We can't re-load the instruction.  */
 173                         env->cr[CR_IIR] = 0;
 174                         break;
 175                     }
 176                 }
 177                 env->cr[CR_IIR] = ldl_phys(cs->as, paddr);
 178             }
 179             break;
 180
 181         default:
 182             /* Other exceptions do not set IIR.  */
 183             break;
 184         }
 185
 186         /* step 6 */
 187         env->shadow[0] = env->gr[1];
 188         env->shadow[1] = env->gr[8];
 189         env->shadow[2] = env->gr[9];
 190         env->shadow[3] = env->gr[16];
 191         env->shadow[4] = env->gr[17];
 192         env->shadow[5] = env->gr[24];
 193         env->shadow[6] = env->gr[25];
 194     }
 195
 196     /* step 7 */
 197     if (i == EXCP_TOC) {
 198         env->iaoq_f = hppa_form_gva(env, 0, FIRMWARE_START);
 199         /* help SeaBIOS and provide iaoq_b and iasq_back in shadow regs */
 200         env->gr[24] = env->cr_back[0];
 201         env->gr[25] = env->cr_back[1];
 202     } else {
 203         env->iaoq_f = hppa_form_gva(env, 0, env->cr[CR_IVA] + 32 * i);
 204     }
 205     env->iaoq_b = hppa_form_gva(env, 0, env->iaoq_f + 4);
 206     env->iasq_f = 0;
 207     env->iasq_b = 0;
 208
 209     if (qemu_loglevel_mask(CPU_LOG_INT)) {
 210         static const char * const names[] = {
 211             [EXCP_HPMC]          = "high priority machine check",
 212             [EXCP_POWER_FAIL]    = "power fail interrupt",
 213             [EXCP_RC]            = "recovery counter trap",
 214             [EXCP_EXT_INTERRUPT] = "external interrupt",
 215             [EXCP_LPMC]          = "low priority machine check",
 216             [EXCP_ITLB_MISS]     = "instruction tlb miss fault",
 217             [EXCP_IMP]           = "instruction memory protection trap",
 218             [EXCP_ILL]           = "illegal instruction trap",
 219             [EXCP_BREAK]         = "break instruction trap",
 220             [EXCP_PRIV_OPR]      = "privileged operation trap",
 221             [EXCP_PRIV_REG]      = "privileged register trap",
 222             [EXCP_OVERFLOW]      = "overflow trap",
 223             [EXCP_COND]          = "conditional trap",
 224             [EXCP_ASSIST]        = "assist exception trap",
 225             [EXCP_DTLB_MISS]     = "data tlb miss fault",
 226             [EXCP_NA_ITLB_MISS]  = "non-access instruction tlb miss",
 227             [EXCP_NA_DTLB_MISS]  = "non-access data tlb miss",
 228             [EXCP_DMP]           = "data memory protection trap",
 229             [EXCP_DMB]           = "data memory break trap",
 230             [EXCP_TLB_DIRTY]     = "tlb dirty bit trap",
 231             [EXCP_PAGE_REF]      = "page reference trap",
 232             [EXCP_ASSIST_EMU]    = "assist emulation trap",
 233             [EXCP_HPT]           = "high-privilege transfer trap",
 234             [EXCP_LPT]           = "low-privilege transfer trap",
 235             [EXCP_TB]            = "taken branch trap",
 236             [EXCP_DMAR]          = "data memory access rights trap",
 237             [EXCP_DMPI]          = "data memory protection id trap",
 238             [EXCP_UNALIGN]       = "unaligned data reference trap",
 239             [EXCP_PER_INTERRUPT] = "performance monitor interrupt",
 240             [EXCP_SYSCALL]       = "syscall",
 241             [EXCP_SYSCALL_LWS]   = "syscall-lws",
 242             [EXCP_TOC]           = "TOC (transfer of control)",
 243         };
 244         static int count;
 245         const char *name = NULL;
 246         char unknown[16];
 247
 248         if (i >= 0 && i < ARRAY_SIZE(names)) {
 249             name = names[i];
 250         }
 251         if (!name) {
 252             snprintf(unknown, sizeof(unknown), "unknown %d", i);
 253             name = unknown;
 254         }
 255         qemu_log("INT %6d: %s @ " TARGET_FMT_lx ":" TARGET_FMT_lx
 256                  " for " TARGET_FMT_lx ":" TARGET_FMT_lx "\n",
 257                  ++count, name, env->cr[CR_IIASQ], env->cr[CR_IIAOQ],
 258                  env->cr[CR_ISR], env->cr[CR_IOR]);
 259     }
 260     cs->exception_index = -1;
 261 }
 262
 263 bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 264 {
 265     HPPACPU *cpu = HPPA_CPU(cs);
 266     CPUHPPAState *env = &cpu->env;
 267
 268     if (interrupt_request & CPU_INTERRUPT_NMI) {
 269         /* Raise TOC (NMI) interrupt */
 270         cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI);
 271         cs->exception_index = EXCP_TOC;
 272         hppa_cpu_do_interrupt(cs);
 273         return true;
 274     }
 275
 276     /* If interrupts are requested and enabled, raise them.  */
 277     if ((interrupt_request & CPU_INTERRUPT_HARD)
 278         && (env->psw & PSW_I)
 279         && (env->cr[CR_EIRR] & env->cr[CR_EIEM])) {
 280         cs->exception_index = EXCP_EXT_INTERRUPT;
 281         hppa_cpu_do_interrupt(cs);
 282         return true;
 283     }
 284     return false;
 285 }