target/hexagon/translate.h

   1 /*
   2  *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_TRANSLATE_H
  19 #define HEXAGON_TRANSLATE_H
  20
  21 #include "qemu/bitmap.h"
  22 #include "qemu/log.h"
  23 #include "cpu.h"
  24 #include "exec/translator.h"
  25 #include "tcg/tcg-op.h"
  26 #include "insn.h"
  27 #include "internal.h"
  28
  29 typedef struct DisasContext {
  30     DisasContextBase base;
  31     Packet *pkt;
  32     Insn *insn;
  33     uint32_t next_PC;
  34     uint32_t mem_idx;
  35     uint32_t num_packets;
  36     uint32_t num_insns;
  37     uint32_t num_hvx_insns;
  38     int reg_log[REG_WRITES_MAX];
  39     int reg_log_idx;
  40     DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
  41     DECLARE_BITMAP(regs_read, TOTAL_PER_THREAD_REGS);
  42     DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS);
  43     int preg_log[PRED_WRITES_MAX];
  44     int preg_log_idx;
  45     DECLARE_BITMAP(pregs_written, NUM_PREGS);
  46     DECLARE_BITMAP(pregs_read, NUM_PREGS);
  47     uint8_t store_width[STORES_MAX];
  48     bool s1_store_processed;
  49     int future_vregs_idx;
  50     int future_vregs_num[VECTOR_TEMPS_MAX];
  51     int tmp_vregs_idx;
  52     int tmp_vregs_num[VECTOR_TEMPS_MAX];
  53     int vreg_log[NUM_VREGS];
  54     int vreg_log_idx;
  55     DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
  56     DECLARE_BITMAP(vregs_updated, NUM_VREGS);
  57     DECLARE_BITMAP(vregs_select, NUM_VREGS);
  58     DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
  59     DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
  60     DECLARE_BITMAP(vregs_read, NUM_VREGS);
  61     int qreg_log[NUM_QREGS];
  62     int qreg_log_idx;
  63     DECLARE_BITMAP(qregs_read, NUM_QREGS);
  64     bool pre_commit;
  65     bool need_commit;
  66     TCGCond branch_cond;
  67     target_ulong branch_dest;
  68     bool is_tight_loop;
  69     bool short_circuit;
  70     bool has_hvx_helper;
  71     TCGv new_value[TOTAL_PER_THREAD_REGS];
  72     TCGv new_pred_value[NUM_PREGS];
  73     TCGv pred_written;
  74     TCGv branch_taken;
  75     TCGv dczero_addr;
  76 } DisasContext;
  77
  78 static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
  79 {
  80     if (!test_bit(pnum, ctx->pregs_written)) {
  81         ctx->preg_log[ctx->preg_log_idx] = pnum;
  82         ctx->preg_log_idx++;
  83         set_bit(pnum, ctx->pregs_written);
  84     }
  85 }
  86
  87 static inline void ctx_log_pred_read(DisasContext *ctx, int pnum)
  88 {
  89     set_bit(pnum, ctx->pregs_read);
  90 }
  91
  92 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum,
  93                                      bool is_predicated)
  94 {
  95     if (rnum == HEX_REG_P3_0_ALIASED) {
  96         for (int i = 0; i < NUM_PREGS; i++) {
  97             ctx_log_pred_write(ctx, i);
  98         }
  99     } else {
 100         if (!test_bit(rnum, ctx->regs_written)) {
 101             ctx->reg_log[ctx->reg_log_idx] = rnum;
 102             ctx->reg_log_idx++;
 103             set_bit(rnum, ctx->regs_written);
 104         }
 105         if (is_predicated) {
 106             set_bit(rnum, ctx->predicated_regs);
 107         }
 108     }
 109 }
 110
 111 static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
 112                                           bool is_predicated)
 113 {
 114     ctx_log_reg_write(ctx, rnum, is_predicated);
 115     ctx_log_reg_write(ctx, rnum + 1, is_predicated);
 116 }
 117
 118 static inline void ctx_log_reg_read(DisasContext *ctx, int rnum)
 119 {
 120     set_bit(rnum, ctx->regs_read);
 121 }
 122
 123 static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum)
 124 {
 125     ctx_log_reg_read(ctx, rnum);
 126     ctx_log_reg_read(ctx, rnum + 1);
 127 }
 128
 129 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
 130                              int num, bool alloc_ok);
 131 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
 132                           int num, bool alloc_ok);
 133
 134 static inline void ctx_log_vreg_write(DisasContext *ctx,
 135                                       int rnum, VRegWriteType type,
 136                                       bool is_predicated)
 137 {
 138     if (type != EXT_TMP) {
 139         if (!test_bit(rnum, ctx->vregs_updated)) {
 140             ctx->vreg_log[ctx->vreg_log_idx] = rnum;
 141             ctx->vreg_log_idx++;
 142             set_bit(rnum, ctx->vregs_updated);
 143         }
 144
 145         set_bit(rnum, ctx->vregs_updated);
 146         if (is_predicated) {
 147             set_bit(rnum, ctx->predicated_future_vregs);
 148         }
 149     }
 150     if (type == EXT_NEW) {
 151         set_bit(rnum, ctx->vregs_select);
 152     }
 153     if (type == EXT_TMP) {
 154         set_bit(rnum, ctx->vregs_updated_tmp);
 155         if (is_predicated) {
 156             set_bit(rnum, ctx->predicated_tmp_vregs);
 157         }
 158     }
 159 }
 160
 161 static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
 162                                            int rnum, VRegWriteType type,
 163                                            bool is_predicated)
 164 {
 165     ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
 166     ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
 167 }
 168
 169 static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum)
 170 {
 171     set_bit(rnum, ctx->vregs_read);
 172 }
 173
 174 static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum)
 175 {
 176     ctx_log_vreg_read(ctx, rnum ^ 0);
 177     ctx_log_vreg_read(ctx, rnum ^ 1);
 178 }
 179
 180 static inline void ctx_log_qreg_write(DisasContext *ctx,
 181                                       int rnum)
 182 {
 183     ctx->qreg_log[ctx->qreg_log_idx] = rnum;
 184     ctx->qreg_log_idx++;
 185 }
 186
 187 static inline void ctx_log_qreg_read(DisasContext *ctx, int qnum)
 188 {
 189     set_bit(qnum, ctx->qregs_read);
 190 }
 191
 192 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
 193 extern TCGv hex_pred[NUM_PREGS];
 194 extern TCGv hex_slot_cancelled;
 195 extern TCGv hex_new_value_usr;
 196 extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
 197 extern TCGv hex_store_addr[STORES_MAX];
 198 extern TCGv hex_store_width[STORES_MAX];
 199 extern TCGv hex_store_val32[STORES_MAX];
 200 extern TCGv_i64 hex_store_val64[STORES_MAX];
 201 extern TCGv hex_llsc_addr;
 202 extern TCGv hex_llsc_val;
 203 extern TCGv_i64 hex_llsc_val_i64;
 204 extern TCGv hex_vstore_addr[VSTORES_MAX];
 205 extern TCGv hex_vstore_size[VSTORES_MAX];
 206 extern TCGv hex_vstore_pending[VSTORES_MAX];
 207
 208 bool is_gather_store_insn(DisasContext *ctx);
 209 void process_store(DisasContext *ctx, int slot_num);
 210
 211 FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX,       0, 2)
 212 FIELD(PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 2, 1)
 213
 214 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0,        0, 1)
 215 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1,        1, 1)
 216 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1)
 217 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED,     3, 1)
 218 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED,     4, 1)
 219 FIELD(PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX,        5, 2)
 220
 221 #endif