target/hexagon/cpu.c

   1 /*
   2  *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qemu/qemu-print.h"
  20 #include "cpu.h"
  21 #include "internal.h"
  22 #include "exec/exec-all.h"
  23 #include "qapi/error.h"
  24 #include "hw/qdev-properties.h"
  25 #include "fpu/softfloat-helpers.h"
  26 #include "tcg/tcg.h"
  27 #include "exec/gdbstub.h"
  28
  29 static void hexagon_v67_cpu_init(Object *obj) { }
  30 static void hexagon_v68_cpu_init(Object *obj) { }
  31 static void hexagon_v69_cpu_init(Object *obj) { }
  32 static void hexagon_v71_cpu_init(Object *obj) { }
  33 static void hexagon_v73_cpu_init(Object *obj) { }
  34
  35 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
  36 {
  37     ObjectClass *oc;
  38     char *typename;
  39     char **cpuname;
  40
  41     cpuname = g_strsplit(cpu_model, ",", 1);
  42     typename = g_strdup_printf(HEXAGON_CPU_TYPE_NAME("%s"), cpuname[0]);
  43     oc = object_class_by_name(typename);
  44     g_strfreev(cpuname);
  45     g_free(typename);
  46
  47     return oc;
  48 }
  49
  50 static Property hexagon_lldb_compat_property =
  51     DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false);
  52 static Property hexagon_lldb_stack_adjust_property =
  53     DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust,
  54                          0, qdev_prop_uint32, target_ulong);
  55 static Property hexagon_short_circuit_property =
  56     DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true);
  57
  58 const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {
  59    "r0", "r1",  "r2",  "r3",  "r4",   "r5",  "r6",  "r7",
  60    "r8", "r9",  "r10", "r11", "r12",  "r13", "r14", "r15",
  61   "r16", "r17", "r18", "r19", "r20",  "r21", "r22", "r23",
  62   "r24", "r25", "r26", "r27", "r28",  "r29", "r30", "r31",
  63   "sa0", "lc0", "sa1", "lc1", "p3_0", "c5",  "m0",  "m1",
  64   "usr", "pc",  "ugp", "gp",  "cs0",  "cs1", "c14", "c15",
  65   "c16", "c17", "c18", "c19", "pkt_cnt",  "insn_cnt", "hvx_cnt", "c23",
  66   "c24", "c25", "c26", "c27", "c28",  "c29", "c30", "c31",
  67 };
  68
  69 /*
  70  * One of the main debugging techniques is to use "-d cpu" and compare against
  71  * LLDB output when single stepping.  However, the target and qemu put the
  72  * stacks at different locations.  This is used to compensate so the diff is
  73  * cleaner.
  74  */
  75 static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
  76 {
  77     HexagonCPU *cpu = env_archcpu(env);
  78     target_ulong stack_adjust = cpu->lldb_stack_adjust;
  79     target_ulong stack_start = env->stack_start;
  80     target_ulong stack_size = 0x10000;
  81
  82     if (stack_adjust == 0) {
  83         return addr;
  84     }
  85
  86     if (stack_start + 0x1000 >= addr && addr >= (stack_start - stack_size)) {
  87         return addr - stack_adjust;
  88     }
  89     return addr;
  90 }
  91
  92 /* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */
  93 static target_ulong read_p3_0(CPUHexagonState *env)
  94 {
  95     int32_t control_reg = 0;
  96     int i;
  97     for (i = NUM_PREGS - 1; i >= 0; i--) {
  98         control_reg <<= 8;
  99         control_reg |= env->pred[i] & 0xff;
 100     }
 101     return control_reg;
 102 }
 103
 104 static void print_reg(FILE *f, CPUHexagonState *env, int regnum)
 105 {
 106     target_ulong value;
 107
 108     if (regnum == HEX_REG_P3_0_ALIASED) {
 109         value = read_p3_0(env);
 110     } else {
 111         value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum])
 112                             : env->gpr[regnum];
 113     }
 114
 115     qemu_fprintf(f, "  %s = 0x" TARGET_FMT_lx "\n",
 116                  hexagon_regnames[regnum], value);
 117 }
 118
 119 static void print_vreg(FILE *f, CPUHexagonState *env, int regnum,
 120                        bool skip_if_zero)
 121 {
 122     if (skip_if_zero) {
 123         bool nonzero_found = false;
 124         for (int i = 0; i < MAX_VEC_SIZE_BYTES; i++) {
 125             if (env->VRegs[regnum].ub[i] != 0) {
 126                 nonzero_found = true;
 127                 break;
 128             }
 129         }
 130         if (!nonzero_found) {
 131             return;
 132         }
 133     }
 134
 135     qemu_fprintf(f, "  v%d = ( ", regnum);
 136     qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]);
 137     for (int i = MAX_VEC_SIZE_BYTES - 2; i >= 0; i--) {
 138         qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]);
 139     }
 140     qemu_fprintf(f, " )\n");
 141 }
 142
 143 void hexagon_debug_vreg(CPUHexagonState *env, int regnum)
 144 {
 145     print_vreg(stdout, env, regnum, false);
 146 }
 147
 148 static void print_qreg(FILE *f, CPUHexagonState *env, int regnum,
 149                        bool skip_if_zero)
 150 {
 151     if (skip_if_zero) {
 152         bool nonzero_found = false;
 153         for (int i = 0; i < MAX_VEC_SIZE_BYTES / 8; i++) {
 154             if (env->QRegs[regnum].ub[i] != 0) {
 155                 nonzero_found = true;
 156                 break;
 157             }
 158         }
 159         if (!nonzero_found) {
 160             return;
 161         }
 162     }
 163
 164     qemu_fprintf(f, "  q%d = ( ", regnum);
 165     qemu_fprintf(f, "0x%02x",
 166                  env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]);
 167     for (int i = MAX_VEC_SIZE_BYTES / 8 - 2; i >= 0; i--) {
 168         qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]);
 169     }
 170     qemu_fprintf(f, " )\n");
 171 }
 172
 173 void hexagon_debug_qreg(CPUHexagonState *env, int regnum)
 174 {
 175     print_qreg(stdout, env, regnum, false);
 176 }
 177
 178 static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)
 179 {
 180     HexagonCPU *cpu = env_archcpu(env);
 181
 182     if (cpu->lldb_compat) {
 183         /*
 184          * When comparing with LLDB, it doesn't step through single-cycle
 185          * hardware loops the same way.  So, we just skip them here
 186          */
 187         if (env->gpr[HEX_REG_PC] == env->last_pc_dumped) {
 188             return;
 189         }
 190         env->last_pc_dumped = env->gpr[HEX_REG_PC];
 191     }
 192
 193     qemu_fprintf(f, "General Purpose Registers = {\n");
 194     for (int i = 0; i < 32; i++) {
 195         print_reg(f, env, i);
 196     }
 197     print_reg(f, env, HEX_REG_SA0);
 198     print_reg(f, env, HEX_REG_LC0);
 199     print_reg(f, env, HEX_REG_SA1);
 200     print_reg(f, env, HEX_REG_LC1);
 201     print_reg(f, env, HEX_REG_M0);
 202     print_reg(f, env, HEX_REG_M1);
 203     print_reg(f, env, HEX_REG_USR);
 204     print_reg(f, env, HEX_REG_P3_0_ALIASED);
 205     print_reg(f, env, HEX_REG_GP);
 206     print_reg(f, env, HEX_REG_UGP);
 207     print_reg(f, env, HEX_REG_PC);
 208 #ifdef CONFIG_USER_ONLY
 209     /*
 210      * Not modelled in user mode, print junk to minimize the diff's
 211      * with LLDB output
 212      */
 213     qemu_fprintf(f, "  cause = 0x000000db\n");
 214     qemu_fprintf(f, "  badva = 0x00000000\n");
 215     qemu_fprintf(f, "  cs0 = 0x00000000\n");
 216     qemu_fprintf(f, "  cs1 = 0x00000000\n");
 217 #else
 218     print_reg(f, env, HEX_REG_CAUSE);
 219     print_reg(f, env, HEX_REG_BADVA);
 220     print_reg(f, env, HEX_REG_CS0);
 221     print_reg(f, env, HEX_REG_CS1);
 222 #endif
 223     qemu_fprintf(f, "}\n");
 224
 225     if (flags & CPU_DUMP_FPU) {
 226         qemu_fprintf(f, "Vector Registers = {\n");
 227         for (int i = 0; i < NUM_VREGS; i++) {
 228             print_vreg(f, env, i, true);
 229         }
 230         for (int i = 0; i < NUM_QREGS; i++) {
 231             print_qreg(f, env, i, true);
 232         }
 233         qemu_fprintf(f, "}\n");
 234     }
 235 }
 236
 237 static void hexagon_dump_state(CPUState *cs, FILE *f, int flags)
 238 {
 239     hexagon_dump(cpu_env(cs), f, flags);
 240 }
 241
 242 void hexagon_debug(CPUHexagonState *env)
 243 {
 244     hexagon_dump(env, stdout, CPU_DUMP_FPU);
 245 }
 246
 247 static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
 248 {
 249     cpu_env(cs)->gpr[HEX_REG_PC] = value;
 250 }
 251
 252 static vaddr hexagon_cpu_get_pc(CPUState *cs)
 253 {
 254     return cpu_env(cs)->gpr[HEX_REG_PC];
 255 }
 256
 257 static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
 258                                             const TranslationBlock *tb)
 259 {
 260     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
 261     cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc;
 262 }
 263
 264 static bool hexagon_cpu_has_work(CPUState *cs)
 265 {
 266     return true;
 267 }
 268
 269 static void hexagon_restore_state_to_opc(CPUState *cs,
 270                                          const TranslationBlock *tb,
 271                                          const uint64_t *data)
 272 {
 273     cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
 274 }
 275
 276 static void hexagon_cpu_reset_hold(Object *obj)
 277 {
 278     CPUState *cs = CPU(obj);
 279     HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj);
 280     CPUHexagonState *env = cpu_env(cs);
 281
 282     if (mcc->parent_phases.hold) {
 283         mcc->parent_phases.hold(obj);
 284     }
 285
 286     set_default_nan_mode(1, &env->fp_status);
 287     set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
 288 }
 289
 290 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 291 {
 292     info->print_insn = print_insn_hexagon;
 293 }
 294
 295 static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
 296 {
 297     CPUState *cs = CPU(dev);
 298     HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(dev);
 299     Error *local_err = NULL;
 300
 301     cpu_exec_realizefn(cs, &local_err);
 302     if (local_err != NULL) {
 303         error_propagate(errp, local_err);
 304         return;
 305     }
 306
 307     gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register,
 308                              hexagon_hvx_gdb_write_register,
 309                              gdb_find_static_feature("hexagon-hvx.xml"), 0);
 310
 311     qemu_init_vcpu(cs);
 312     cpu_reset(cs);
 313
 314     mcc->parent_realize(dev, errp);
 315 }
 316
 317 static void hexagon_cpu_init(Object *obj)
 318 {
 319     qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property);
 320     qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
 321     qdev_property_add_static(DEVICE(obj), &hexagon_short_circuit_property);
 322 }
 323
 324 #include "hw/core/tcg-cpu-ops.h"
 325
 326 static const TCGCPUOps hexagon_tcg_ops = {
 327     .initialize = hexagon_translate_init,
 328     .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
 329     .restore_state_to_opc = hexagon_restore_state_to_opc,
 330 };
 331
 332 static void hexagon_cpu_class_init(ObjectClass *c, void *data)
 333 {
 334     HexagonCPUClass *mcc = HEXAGON_CPU_CLASS(c);
 335     CPUClass *cc = CPU_CLASS(c);
 336     DeviceClass *dc = DEVICE_CLASS(c);
 337     ResettableClass *rc = RESETTABLE_CLASS(c);
 338
 339     device_class_set_parent_realize(dc, hexagon_cpu_realize,
 340                                     &mcc->parent_realize);
 341
 342     resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL,
 343                                        &mcc->parent_phases);
 344
 345     cc->class_by_name = hexagon_cpu_class_by_name;
 346     cc->has_work = hexagon_cpu_has_work;
 347     cc->dump_state = hexagon_dump_state;
 348     cc->set_pc = hexagon_cpu_set_pc;
 349     cc->get_pc = hexagon_cpu_get_pc;
 350     cc->gdb_read_register = hexagon_gdb_read_register;
 351     cc->gdb_write_register = hexagon_gdb_write_register;
 352     cc->gdb_stop_before_watchpoint = true;
 353     cc->gdb_core_xml_file = "hexagon-core.xml";
 354     cc->disas_set_info = hexagon_cpu_disas_set_info;
 355     cc->tcg_ops = &hexagon_tcg_ops;
 356 }
 357
 358 #define DEFINE_CPU(type_name, initfn)      \
 359     {                                      \
 360         .name = type_name,                 \
 361         .parent = TYPE_HEXAGON_CPU,        \
 362         .instance_init = initfn            \
 363     }
 364
 365 static const TypeInfo hexagon_cpu_type_infos[] = {
 366     {
 367         .name = TYPE_HEXAGON_CPU,
 368         .parent = TYPE_CPU,
 369         .instance_size = sizeof(HexagonCPU),
 370         .instance_align = __alignof(HexagonCPU),
 371         .instance_init = hexagon_cpu_init,
 372         .abstract = true,
 373         .class_size = sizeof(HexagonCPUClass),
 374         .class_init = hexagon_cpu_class_init,
 375     },
 376     DEFINE_CPU(TYPE_HEXAGON_CPU_V67,              hexagon_v67_cpu_init),
 377     DEFINE_CPU(TYPE_HEXAGON_CPU_V68,              hexagon_v68_cpu_init),
 378     DEFINE_CPU(TYPE_HEXAGON_CPU_V69,              hexagon_v69_cpu_init),
 379     DEFINE_CPU(TYPE_HEXAGON_CPU_V71,              hexagon_v71_cpu_init),
 380     DEFINE_CPU(TYPE_HEXAGON_CPU_V73,              hexagon_v73_cpu_init),
 381 };
 382
 383 DEFINE_TYPES(hexagon_cpu_type_infos)