2 * Alpha emulation cpu definitions for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "exec/cpu-defs.h"
25 #include "qemu/cpu-float.h"
27 #define ICACHE_LINE_SIZE 32
28 #define DCACHE_LINE_SIZE 32
30 /* Alpha major type */
36 ALPHA_EV5
= 5, /* 21164 */
37 ALPHA_EV45
= 6, /* 21064A */
38 ALPHA_EV56
= 7, /* 21164A */
49 ALPHA_LCA_1
= 1, /* 21066 */
50 ALPHA_LCA_2
= 2, /* 20166 */
51 ALPHA_LCA_3
= 3, /* 21068 */
52 ALPHA_LCA_4
= 4, /* 21068 */
53 ALPHA_LCA_5
= 5, /* 21066A */
54 ALPHA_LCA_6
= 6, /* 21068A */
59 ALPHA_EV5_1
= 1, /* Rev BA, CA */
60 ALPHA_EV5_2
= 2, /* Rev DA, EA */
61 ALPHA_EV5_3
= 3, /* Pass 3 */
62 ALPHA_EV5_4
= 4, /* Pass 3.2 */
63 ALPHA_EV5_5
= 5, /* Pass 4 */
68 ALPHA_EV45_1
= 1, /* Pass 1 */
69 ALPHA_EV45_2
= 2, /* Pass 1.1 */
70 ALPHA_EV45_3
= 3, /* Pass 2 */
75 ALPHA_EV56_1
= 1, /* Pass 1 */
76 ALPHA_EV56_2
= 2, /* Pass 2 */
80 IMPLVER_2106x
= 0, /* EV4, EV45 & LCA45 */
81 IMPLVER_21164
= 1, /* EV5, EV56 & PCA45 */
82 IMPLVER_21264
= 2, /* EV6, EV67 & EV68x */
83 IMPLVER_21364
= 3, /* EV7 & EV79 */
87 AMASK_BWX
= 0x00000001,
88 AMASK_FIX
= 0x00000002,
89 AMASK_CIX
= 0x00000004,
90 AMASK_MVI
= 0x00000100,
91 AMASK_TRAP
= 0x00000200,
92 AMASK_PREFETCH
= 0x00001000,
101 IEEE_ROUND_NORMAL
= 0,
108 /* IEEE floating-point operations encoding */
120 FP_ROUND_CHOPPED
= 0x0,
121 FP_ROUND_MINUS
= 0x1,
122 FP_ROUND_NORMAL
= 0x2,
123 FP_ROUND_DYNAMIC
= 0x3,
126 /* FPCR bits -- right-shifted 32 so we can use a uint32_t. */
127 #define FPCR_SUM (1U << (63 - 32))
128 #define FPCR_INED (1U << (62 - 32))
129 #define FPCR_UNFD (1U << (61 - 32))
130 #define FPCR_UNDZ (1U << (60 - 32))
131 #define FPCR_DYN_SHIFT (58 - 32)
132 #define FPCR_DYN_CHOPPED (0U << FPCR_DYN_SHIFT)
133 #define FPCR_DYN_MINUS (1U << FPCR_DYN_SHIFT)
134 #define FPCR_DYN_NORMAL (2U << FPCR_DYN_SHIFT)
135 #define FPCR_DYN_PLUS (3U << FPCR_DYN_SHIFT)
136 #define FPCR_DYN_MASK (3U << FPCR_DYN_SHIFT)
137 #define FPCR_IOV (1U << (57 - 32))
138 #define FPCR_INE (1U << (56 - 32))
139 #define FPCR_UNF (1U << (55 - 32))
140 #define FPCR_OVF (1U << (54 - 32))
141 #define FPCR_DZE (1U << (53 - 32))
142 #define FPCR_INV (1U << (52 - 32))
143 #define FPCR_OVFD (1U << (51 - 32))
144 #define FPCR_DZED (1U << (50 - 32))
145 #define FPCR_INVD (1U << (49 - 32))
146 #define FPCR_DNZ (1U << (48 - 32))
147 #define FPCR_DNOD (1U << (47 - 32))
148 #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
149 | FPCR_OVF | FPCR_DZE | FPCR_INV)
151 /* The silly software trap enables implemented by the kernel emulation.
152 These are more or less architecturally required, since the real hardware
153 has read-as-zero bits in the FPCR when the features aren't implemented.
154 For the purposes of QEMU, we pretend the FPCR can hold everything. */
155 #define SWCR_TRAP_ENABLE_INV (1U << 1)
156 #define SWCR_TRAP_ENABLE_DZE (1U << 2)
157 #define SWCR_TRAP_ENABLE_OVF (1U << 3)
158 #define SWCR_TRAP_ENABLE_UNF (1U << 4)
159 #define SWCR_TRAP_ENABLE_INE (1U << 5)
160 #define SWCR_TRAP_ENABLE_DNO (1U << 6)
161 #define SWCR_TRAP_ENABLE_MASK ((1U << 7) - (1U << 1))
163 #define SWCR_MAP_DMZ (1U << 12)
164 #define SWCR_MAP_UMZ (1U << 13)
165 #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
167 #define SWCR_STATUS_INV (1U << 17)
168 #define SWCR_STATUS_DZE (1U << 18)
169 #define SWCR_STATUS_OVF (1U << 19)
170 #define SWCR_STATUS_UNF (1U << 20)
171 #define SWCR_STATUS_INE (1U << 21)
172 #define SWCR_STATUS_DNO (1U << 22)
173 #define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
175 #define SWCR_STATUS_TO_EXCSUM_SHIFT 16
177 #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
179 /* MMU modes definitions */
181 /* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User.
182 The Unix PALcode only exposes the kernel and user modes; presumably
183 executive and supervisor are used by VMS.
185 PALcode itself uses physical mode for code and kernel mode for data;
186 there are PALmode instructions that can access data via physical mode
187 or via an os-installed "alternate mode", which is one of the 4 above.
189 That said, we're only emulating Unix PALcode, and not attempting VMS,
190 so we don't need to implement Executive and Supervisor. QEMU's own
191 PALcode cheats and uses the KSEG mapping for its code+data rather than
192 physical addresses. */
194 #define MMU_KERNEL_IDX 0
195 #define MMU_USER_IDX 1
196 #define MMU_PHYS_IDX 2
198 typedef struct CPUArchState
{
206 /* The FPCR, and disassembled portions thereof. */
208 #ifdef CONFIG_USER_ONLY
211 uint32_t fpcr_exc_enable
;
212 float_status fp_status
;
213 uint8_t fpcr_dyn_round
;
214 uint8_t fpcr_flush_to_zero
;
216 /* Mask of PALmode, Processor State et al. Most of this gets copied
217 into the TranslatorBlock flags and controls code generation. */
220 /* The high 32-bits of the processor cycle counter. */
223 /* These pass data from the exception logic in the translator and
224 helpers to the OS entry point. This is used for both system
225 emulation and user-mode. */
230 #if !defined(CONFIG_USER_ONLY)
231 /* The internal data required by our emulation of the Unix PALcode. */
239 uint64_t scratch
[24];
242 /* This alarm doesn't exist in real hardware; we wish it did. */
243 uint64_t alarm_expire
;
254 * @env: #CPUAlphaState
263 /* This alarm doesn't exist in real hardware; we wish it did. */
264 QEMUTimer
*alarm_timer
;
269 * @parent_realize: The parent class' realize handler.
270 * @parent_reset: The parent class' reset handler.
272 * An Alpha CPU model.
274 struct AlphaCPUClass
{
275 CPUClass parent_class
;
277 DeviceRealize parent_realize
;
278 DeviceReset parent_reset
;
281 #ifndef CONFIG_USER_ONLY
282 extern const VMStateDescription vmstate_alpha_cpu
;
284 void alpha_cpu_do_interrupt(CPUState
*cpu
);
285 bool alpha_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
286 hwaddr
alpha_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
287 #endif /* !CONFIG_USER_ONLY */
288 void alpha_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
);
289 int alpha_cpu_gdb_read_register(CPUState
*cpu
, GByteArray
*buf
, int reg
);
290 int alpha_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
292 #include "exec/cpu-all.h"
295 FEATURE_ASN
= 0x00000001,
296 FEATURE_SPS
= 0x00000002,
297 FEATURE_VIRBND
= 0x00000004,
298 FEATURE_TBCHK
= 0x00000008,
315 /* Alpha-specific interrupt pending bits. */
316 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
317 #define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
318 #define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
320 /* OSF/1 Page table bits. */
323 PTE_FOR
= 0x0002, /* used for page protection (fault on read) */
324 PTE_FOW
= 0x0004, /* used for page protection (fault on write) */
325 PTE_FOE
= 0x0008, /* used for page protection (fault on exec) */
333 /* Hardware interrupt (entInt) constants. */
342 /* Memory management (entMM) constants. */
351 /* Arithmetic exception (entArith) constants. */
353 EXC_M_SWC
= 1, /* Software completion */
354 EXC_M_INV
= 2, /* Invalid operation */
355 EXC_M_DZE
= 4, /* Division by zero */
356 EXC_M_FOV
= 8, /* Overflow */
357 EXC_M_UNF
= 16, /* Underflow */
358 EXC_M_INE
= 32, /* Inexact result */
359 EXC_M_IOV
= 64 /* Integer Overflow */
362 /* Processor status constants. */
363 /* Low 3 bits are interrupt mask level. */
364 #define PS_INT_MASK 7u
366 /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
367 The Unix PALcode only uses bit 4. */
368 #define PS_USER_MODE 8u
370 /* CPUAlphaState->flags constants. These are laid out so that we
371 can set or reset the pieces individually by assigning to the byte,
372 or manipulated as a whole. */
374 #define ENV_FLAG_PAL_SHIFT 0
375 #define ENV_FLAG_PS_SHIFT 8
376 #define ENV_FLAG_RX_SHIFT 16
377 #define ENV_FLAG_FEN_SHIFT 24
379 #define ENV_FLAG_PAL_MODE (1u << ENV_FLAG_PAL_SHIFT)
380 #define ENV_FLAG_PS_USER (PS_USER_MODE << ENV_FLAG_PS_SHIFT)
381 #define ENV_FLAG_RX_FLAG (1u << ENV_FLAG_RX_SHIFT)
382 #define ENV_FLAG_FEN (1u << ENV_FLAG_FEN_SHIFT)
384 #define ENV_FLAG_TB_MASK \
385 (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN)
387 #define TB_FLAG_UNALIGN (1u << 1)
389 static inline int alpha_env_mmu_index(CPUAlphaState
*env
)
391 int ret
= env
->flags
& ENV_FLAG_PS_USER
? MMU_USER_IDX
: MMU_KERNEL_IDX
;
392 if (env
->flags
& ENV_FLAG_PAL_MODE
) {
393 ret
= MMU_KERNEL_IDX
;
435 void alpha_translate_init(void);
437 #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
439 G_NORETURN
void dynamic_excp(CPUAlphaState
*, uintptr_t, int, int);
440 G_NORETURN
void arith_excp(CPUAlphaState
*, uintptr_t, int, uint64_t);
442 uint64_t cpu_alpha_load_fpcr (CPUAlphaState
*env
);
443 void cpu_alpha_store_fpcr (CPUAlphaState
*env
, uint64_t val
);
444 uint64_t cpu_alpha_load_gr(CPUAlphaState
*env
, unsigned reg
);
445 void cpu_alpha_store_gr(CPUAlphaState
*env
, unsigned reg
, uint64_t val
);
447 #ifdef CONFIG_USER_ONLY
448 void alpha_cpu_record_sigsegv(CPUState
*cs
, vaddr address
,
449 MMUAccessType access_type
,
450 bool maperr
, uintptr_t retaddr
);
451 void alpha_cpu_record_sigbus(CPUState
*cs
, vaddr address
,
452 MMUAccessType access_type
, uintptr_t retaddr
);
454 bool alpha_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
455 MMUAccessType access_type
, int mmu_idx
,
456 bool probe
, uintptr_t retaddr
);
457 G_NORETURN
void alpha_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
458 MMUAccessType access_type
, int mmu_idx
,
460 void alpha_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
461 vaddr addr
, unsigned size
,
462 MMUAccessType access_type
,
463 int mmu_idx
, MemTxAttrs attrs
,
464 MemTxResult response
, uintptr_t retaddr
);
467 static inline void cpu_get_tb_cpu_state(CPUAlphaState
*env
, vaddr
*pc
,
468 uint64_t *cs_base
, uint32_t *pflags
)
472 *pflags
= env
->flags
& ENV_FLAG_TB_MASK
;
473 #ifdef CONFIG_USER_ONLY
474 *pflags
|= TB_FLAG_UNALIGN
* !env_cpu(env
)->prctl_unalign_sigbus
;
478 #ifdef CONFIG_USER_ONLY
479 /* Copied from linux ieee_swcr_to_fpcr. */
480 static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr
)
484 fpcr
|= (swcr
& SWCR_STATUS_MASK
) << 35;
485 fpcr
|= (swcr
& SWCR_MAP_DMZ
) << 36;
486 fpcr
|= (~swcr
& (SWCR_TRAP_ENABLE_INV
487 | SWCR_TRAP_ENABLE_DZE
488 | SWCR_TRAP_ENABLE_OVF
)) << 48;
489 fpcr
|= (~swcr
& (SWCR_TRAP_ENABLE_UNF
490 | SWCR_TRAP_ENABLE_INE
)) << 57;
491 fpcr
|= (swcr
& SWCR_MAP_UMZ
? FPCR_UNDZ
| FPCR_UNFD
: 0);
492 fpcr
|= (~swcr
& SWCR_TRAP_ENABLE_DNO
) << 41;
497 /* Copied from linux ieee_fpcr_to_swcr. */
498 static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr
)
502 swcr
|= (fpcr
>> 35) & SWCR_STATUS_MASK
;
503 swcr
|= (fpcr
>> 36) & SWCR_MAP_DMZ
;
504 swcr
|= (~fpcr
>> 48) & (SWCR_TRAP_ENABLE_INV
505 | SWCR_TRAP_ENABLE_DZE
506 | SWCR_TRAP_ENABLE_OVF
);
507 swcr
|= (~fpcr
>> 57) & (SWCR_TRAP_ENABLE_UNF
| SWCR_TRAP_ENABLE_INE
);
508 swcr
|= (fpcr
>> 47) & SWCR_MAP_UMZ
;
509 swcr
|= (~fpcr
>> 41) & SWCR_TRAP_ENABLE_DNO
;
513 #endif /* CONFIG_USER_ONLY */
515 #endif /* ALPHA_CPU_H */