linux-user/riscv/cpu_loop.c

   1 /*
   2  *  qemu user cpu loop
   3  *
   4  *  Copyright (c) 2003-2008 Fabrice Bellard
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/error-report.h"
  22 #include "qemu.h"
  23 #include "user-internals.h"
  24 #include "cpu_loop-common.h"
  25 #include "signal-common.h"
  26 #include "elf.h"
  27 #include "semihosting/common-semi.h"
  28
  29 void cpu_loop(CPURISCVState *env)
  30 {
  31     CPUState *cs = env_cpu(env);
  32     int trapnr;
  33     target_ulong ret;
  34
  35     for (;;) {
  36         cpu_exec_start(cs);
  37         trapnr = cpu_exec(cs);
  38         cpu_exec_end(cs);
  39         process_queued_cpu_work(cs);
  40
  41         switch (trapnr) {
  42         case EXCP_INTERRUPT:
  43             /* just indicate that signals should be handled asap */
  44             break;
  45         case EXCP_ATOMIC:
  46             cpu_exec_step_atomic(cs);
  47             break;
  48         case RISCV_EXCP_U_ECALL:
  49             env->pc += 4;
  50             if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) {
  51                 /* riscv_flush_icache_syscall is a no-op in QEMU as
  52                    self-modifying code is automatically detected */
  53                 ret = 0;
  54             } else {
  55                 ret = do_syscall(env,
  56                                  env->gpr[(env->elf_flags & EF_RISCV_RVE)
  57                                     ? xT0 : xA7],
  58                                  env->gpr[xA0],
  59                                  env->gpr[xA1],
  60                                  env->gpr[xA2],
  61                                  env->gpr[xA3],
  62                                  env->gpr[xA4],
  63                                  env->gpr[xA5],
  64                                  0, 0);
  65             }
  66             if (ret == -QEMU_ERESTARTSYS) {
  67                 env->pc -= 4;
  68             } else if (ret != -QEMU_ESIGRETURN) {
  69                 env->gpr[xA0] = ret;
  70             }
  71             if (cs->singlestep_enabled) {
  72                 goto gdbstep;
  73             }
  74             break;
  75         case RISCV_EXCP_ILLEGAL_INST:
  76             force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc);
  77             break;
  78         case RISCV_EXCP_BREAKPOINT:
  79         case EXCP_DEBUG:
  80         gdbstep:
  81             force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
  82             break;
  83         case RISCV_EXCP_SEMIHOST:
  84             do_common_semihosting(cs);
  85             env->pc += 4;
  86             break;
  87         default:
  88             EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
  89                      trapnr);
  90             exit(EXIT_FAILURE);
  91         }
  92
  93         process_pending_signals(env);
  94     }
  95 }
  96
  97 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
  98 {
  99     CPUState *cpu = env_cpu(env);
 100     TaskState *ts = get_task_state(cpu);
 101     struct image_info *info = ts->info;
 102
 103     env->pc = regs->sepc;
 104     env->gpr[xSP] = regs->sp;
 105     env->elf_flags = info->elf_flags;
 106
 107     if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
 108         error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
 109         exit(EXIT_FAILURE);
 110     }
 111
 112     ts->stack_base = info->start_stack;
 113     ts->heap_base = info->brk;
 114     /* This will be filled in on the first SYS_HEAPINFO call.  */
 115     ts->heap_limit = 0;
 116 }