include/hw/gpio/aspeed_gpio.h

   1 /*
   2  *  ASPEED GPIO Controller
   3  *
   4  *  Copyright (C) 2017-2018 IBM Corp.
   5  *
   6  * This code is licensed under the GPL version 2 or later.  See
   7  * the COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef ASPEED_GPIO_H
  11 #define ASPEED_GPIO_H
  12
  13 #include "hw/sysbus.h"
  14 #include "qom/object.h"
  15
  16 #define TYPE_ASPEED_GPIO "aspeed.gpio"
  17 OBJECT_DECLARE_TYPE(AspeedGPIOState, AspeedGPIOClass, ASPEED_GPIO)
  18
  19 #define ASPEED_GPIO_MAX_NR_SETS 8
  20 #define ASPEED_GPIOS_PER_SET 32
  21 #define ASPEED_REGS_PER_BANK 14
  22 #define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS)
  23 #define ASPEED_GROUPS_PER_SET 4
  24 #define ASPEED_GPIO_NR_DEBOUNCE_REGS 3
  25 #define ASPEED_CHARS_PER_GROUP_LABEL 4
  26
  27 typedef struct GPIOSets GPIOSets;
  28
  29 typedef struct GPIOSetProperties {
  30     uint32_t input;
  31     uint32_t output;
  32     char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL];
  33 } GPIOSetProperties;
  34
  35 enum GPIORegType {
  36     gpio_not_a_reg,
  37     gpio_reg_data_value,
  38     gpio_reg_direction,
  39     gpio_reg_int_enable,
  40     gpio_reg_int_sens_0,
  41     gpio_reg_int_sens_1,
  42     gpio_reg_int_sens_2,
  43     gpio_reg_int_status,
  44     gpio_reg_reset_tolerant,
  45     gpio_reg_debounce_1,
  46     gpio_reg_debounce_2,
  47     gpio_reg_cmd_source_0,
  48     gpio_reg_cmd_source_1,
  49     gpio_reg_data_read,
  50     gpio_reg_input_mask,
  51 };
  52
  53 /* GPIO index mode */
  54 enum GPIORegIndexType {
  55     gpio_reg_idx_data = 0,
  56     gpio_reg_idx_direction,
  57     gpio_reg_idx_interrupt,
  58     gpio_reg_idx_debounce,
  59     gpio_reg_idx_tolerance,
  60     gpio_reg_idx_cmd_src,
  61     gpio_reg_idx_input_mask,
  62     gpio_reg_idx_reserved,
  63     gpio_reg_idx_new_w_cmd_src,
  64     gpio_reg_idx_new_r_cmd_src,
  65 };
  66
  67 typedef struct AspeedGPIOReg {
  68     uint16_t set_idx;
  69     enum GPIORegType type;
  70 } AspeedGPIOReg;
  71
  72 struct AspeedGPIOClass {
  73     SysBusDevice parent_obj;
  74     const GPIOSetProperties *props;
  75     uint32_t nr_gpio_pins;
  76     uint32_t nr_gpio_sets;
  77     const AspeedGPIOReg *reg_table;
  78     unsigned reg_table_count;
  79 };
  80
  81 struct AspeedGPIOState {
  82     /* <private> */
  83     SysBusDevice parent;
  84
  85     /*< public >*/
  86     MemoryRegion iomem;
  87     int pending;
  88     qemu_irq irq;
  89     qemu_irq gpios[ASPEED_GPIO_MAX_NR_SETS][ASPEED_GPIOS_PER_SET];
  90
  91 /* Parallel GPIO Registers */
  92     uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
  93     struct GPIOSets {
  94         uint32_t data_value; /* Reflects pin values */
  95         uint32_t data_read; /* Contains last value written to data value */
  96         uint32_t direction;
  97         uint32_t int_enable;
  98         uint32_t int_sens_0;
  99         uint32_t int_sens_1;
 100         uint32_t int_sens_2;
 101         uint32_t int_status;
 102         uint32_t reset_tol;
 103         uint32_t cmd_source_0;
 104         uint32_t cmd_source_1;
 105         uint32_t debounce_1;
 106         uint32_t debounce_2;
 107         uint32_t input_mask;
 108     } sets[ASPEED_GPIO_MAX_NR_SETS];
 109 };
 110
 111 #endif /* ASPEED_GPIO_H */