2 * QEMU Freescale eTSEC Emulator
4 * Copyright (c) 2011-2013 AdaCore
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
25 #include "net/checksum.h"
28 #include "registers.h"
30 /* #define ETSEC_RING_DEBUG */
31 /* #define HEX_DUMP */
32 /* #define DEBUG_BD */
34 #ifdef ETSEC_RING_DEBUG
35 static const int debug_etsec
= 1;
37 static const int debug_etsec
;
40 #define RING_DEBUG(fmt, ...) do { \
42 qemu_log(fmt , ## __VA_ARGS__); \
48 static void print_tx_bd_flags(uint16_t flags
)
50 qemu_log(" Ready: %d\n", !!(flags
& BD_TX_READY
));
51 qemu_log(" PAD/CRC: %d\n", !!(flags
& BD_TX_PADCRC
));
52 qemu_log(" Wrap: %d\n", !!(flags
& BD_WRAP
));
53 qemu_log(" Interrupt: %d\n", !!(flags
& BD_INTERRUPT
));
54 qemu_log(" Last in frame: %d\n", !!(flags
& BD_LAST
));
55 qemu_log(" Tx CRC: %d\n", !!(flags
& BD_TX_TC
));
56 qemu_log(" User-defined preamble / defer: %d\n",
57 !!(flags
& BD_TX_PREDEF
));
58 qemu_log(" Huge frame enable / Late collision: %d\n",
59 !!(flags
& BD_TX_HFELC
));
60 qemu_log(" Control frame / Retransmission Limit: %d\n",
61 !!(flags
& BD_TX_CFRL
));
62 qemu_log(" Retry count: %d\n",
63 (flags
>> BD_TX_RC_OFFSET
) & BD_TX_RC_MASK
);
64 qemu_log(" Underrun / TCP/IP off-load enable: %d\n",
65 !!(flags
& BD_TX_TOEUN
));
66 qemu_log(" Truncation: %d\n", !!(flags
& BD_TX_TR
));
69 static void print_rx_bd_flags(uint16_t flags
)
71 qemu_log(" Empty: %d\n", !!(flags
& BD_RX_EMPTY
));
72 qemu_log(" Receive software ownership: %d\n", !!(flags
& BD_RX_RO1
));
73 qemu_log(" Wrap: %d\n", !!(flags
& BD_WRAP
));
74 qemu_log(" Interrupt: %d\n", !!(flags
& BD_INTERRUPT
));
75 qemu_log(" Last in frame: %d\n", !!(flags
& BD_LAST
));
76 qemu_log(" First in frame: %d\n", !!(flags
& BD_RX_FIRST
));
77 qemu_log(" Miss: %d\n", !!(flags
& BD_RX_MISS
));
78 qemu_log(" Broadcast: %d\n", !!(flags
& BD_RX_BROADCAST
));
79 qemu_log(" Multicast: %d\n", !!(flags
& BD_RX_MULTICAST
));
80 qemu_log(" Rx frame length violation: %d\n", !!(flags
& BD_RX_LG
));
81 qemu_log(" Rx non-octet aligned frame: %d\n", !!(flags
& BD_RX_NO
));
82 qemu_log(" Short frame: %d\n", !!(flags
& BD_RX_SH
));
83 qemu_log(" Rx CRC Error: %d\n", !!(flags
& BD_RX_CR
));
84 qemu_log(" Overrun: %d\n", !!(flags
& BD_RX_OV
));
85 qemu_log(" Truncation: %d\n", !!(flags
& BD_RX_TR
));
89 static void print_bd(eTSEC_rxtx_bd bd
, int mode
, uint32_t index
)
91 qemu_log("eTSEC %s Data Buffer Descriptor (%u)\n",
92 mode
== eTSEC_TRANSMIT
? "Transmit" : "Receive",
94 qemu_log(" Flags : 0x%04x\n", bd
.flags
);
95 if (mode
== eTSEC_TRANSMIT
) {
96 print_tx_bd_flags(bd
.flags
);
98 print_rx_bd_flags(bd
.flags
);
100 qemu_log(" Length : 0x%04x\n", bd
.length
);
101 qemu_log(" Pointer : 0x%08x\n", bd
.bufptr
);
104 #endif /* DEBUG_BD */
106 static void read_buffer_descriptor(eTSEC
*etsec
,
112 RING_DEBUG("READ Buffer Descriptor @ 0x" HWADDR_FMT_plx
"\n", addr
);
113 cpu_physical_memory_read(addr
,
115 sizeof(eTSEC_rxtx_bd
));
117 if (etsec
->regs
[DMACTRL
].value
& DMACTRL_LE
) {
118 bd
->flags
= lduw_le_p(&bd
->flags
);
119 bd
->length
= lduw_le_p(&bd
->length
);
120 bd
->bufptr
= ldl_le_p(&bd
->bufptr
);
122 bd
->flags
= lduw_be_p(&bd
->flags
);
123 bd
->length
= lduw_be_p(&bd
->length
);
124 bd
->bufptr
= ldl_be_p(&bd
->bufptr
);
128 static void write_buffer_descriptor(eTSEC
*etsec
,
134 if (etsec
->regs
[DMACTRL
].value
& DMACTRL_LE
) {
135 stw_le_p(&bd
->flags
, bd
->flags
);
136 stw_le_p(&bd
->length
, bd
->length
);
137 stl_le_p(&bd
->bufptr
, bd
->bufptr
);
139 stw_be_p(&bd
->flags
, bd
->flags
);
140 stw_be_p(&bd
->length
, bd
->length
);
141 stl_be_p(&bd
->bufptr
, bd
->bufptr
);
144 RING_DEBUG("Write Buffer Descriptor @ 0x" HWADDR_FMT_plx
"\n", addr
);
145 cpu_physical_memory_write(addr
,
147 sizeof(eTSEC_rxtx_bd
));
150 static void ievent_set(eTSEC
*etsec
,
153 etsec
->regs
[IEVENT
].value
|= flags
;
155 etsec_update_irq(etsec
);
158 static void tx_padding_and_crc(eTSEC
*etsec
, uint32_t min_frame_len
)
160 int add
= min_frame_len
- etsec
->tx_buffer_len
;
164 RING_DEBUG("pad:%u\n", add
);
165 etsec
->tx_buffer
= g_realloc(etsec
->tx_buffer
,
166 etsec
->tx_buffer_len
+ add
);
168 memset(etsec
->tx_buffer
+ etsec
->tx_buffer_len
, 0x0, add
);
169 etsec
->tx_buffer_len
+= add
;
172 /* Never add CRC in QEMU */
175 static void process_tx_fcb(eTSEC
*etsec
)
177 uint8_t flags
= (uint8_t)(*etsec
->tx_buffer
);
178 /* L3 header offset from start of frame */
179 uint8_t l3_header_offset
= (uint8_t)*(etsec
->tx_buffer
+ 3);
180 /* L4 header offset from start of L3 header */
181 uint8_t l4_header_offset
= (uint8_t)*(etsec
->tx_buffer
+ 2);
183 uint8_t *l3_header
= etsec
->tx_buffer
+ 8 + l3_header_offset
;
185 uint8_t *l4_header
= l3_header
+ l4_header_offset
;
188 /* if packet is IP4 and IP checksum is requested */
189 if (flags
& FCB_TX_IP
&& flags
& FCB_TX_CIP
) {
192 /* TODO Check the correct usage of the PHCS field of the FCB in case the NPH
195 /* if packet is IP4 and TCP or UDP */
196 if (flags
& FCB_TX_IP
&& flags
& FCB_TX_TUP
) {
198 if (flags
& FCB_TX_UDP
) {
199 /* if checksum is requested */
200 if (flags
& FCB_TX_CTU
) {
201 /* do UDP checksum */
204 /* set checksum field to 0 */
208 } else if (flags
& FCB_TX_CTU
) { /* if TCP and checksum is requested */
209 /* do TCP checksum */
215 net_checksum_calculate(etsec
->tx_buffer
+ 8,
216 etsec
->tx_buffer_len
- 8, csum
);
220 static void process_tx_bd(eTSEC
*etsec
,
223 uint8_t *tmp_buff
= NULL
;
224 hwaddr tbdbth
= (hwaddr
)(etsec
->regs
[TBDBPH
].value
& 0xF) << 32;
226 if (bd
->length
== 0) {
231 if (etsec
->tx_buffer_len
== 0) {
232 /* It's the first BD */
233 etsec
->first_bd
= *bd
;
236 /* TODO: if TxBD[TOE/UN] skip the Tx Frame Control Block*/
238 /* Load this Data Buffer */
239 etsec
->tx_buffer
= g_realloc(etsec
->tx_buffer
,
240 etsec
->tx_buffer_len
+ bd
->length
);
241 tmp_buff
= etsec
->tx_buffer
+ etsec
->tx_buffer_len
;
242 cpu_physical_memory_read(bd
->bufptr
+ tbdbth
, tmp_buff
, bd
->length
);
244 /* Update buffer length */
245 etsec
->tx_buffer_len
+= bd
->length
;
248 if (etsec
->tx_buffer_len
!= 0 && (bd
->flags
& BD_LAST
)) {
249 if (etsec
->regs
[MACCFG1
].value
& MACCFG1_TX_EN
) {
250 /* MAC Transmit enabled */
252 /* Process offload Tx FCB */
253 if (etsec
->first_bd
.flags
& BD_TX_TOEUN
) {
254 process_tx_fcb(etsec
);
257 if (etsec
->first_bd
.flags
& BD_TX_PADCRC
258 || etsec
->regs
[MACCFG2
].value
& MACCFG2_PADCRC
) {
260 /* Padding and CRC (Padding implies CRC) */
261 tx_padding_and_crc(etsec
, 60);
263 } else if (etsec
->first_bd
.flags
& BD_TX_TC
264 || etsec
->regs
[MACCFG2
].value
& MACCFG2_CRC_EN
) {
267 /* Never add CRC in QEMU */
270 #if defined(HEX_DUMP)
271 qemu_log("eTSEC Send packet size:%d\n", etsec
->tx_buffer_len
);
272 qemu_hexdump(stderr
, "", etsec
->tx_buffer
, etsec
->tx_buffer_len
);
273 #endif /* ETSEC_RING_DEBUG */
275 if (etsec
->first_bd
.flags
& BD_TX_TOEUN
) {
276 qemu_send_packet(qemu_get_queue(etsec
->nic
),
277 etsec
->tx_buffer
+ 8,
278 etsec
->tx_buffer_len
- 8);
280 qemu_send_packet(qemu_get_queue(etsec
->nic
),
282 etsec
->tx_buffer_len
);
287 etsec
->tx_buffer_len
= 0;
289 if (bd
->flags
& BD_INTERRUPT
) {
290 ievent_set(etsec
, IEVENT_TXF
);
293 if (bd
->flags
& BD_INTERRUPT
) {
294 ievent_set(etsec
, IEVENT_TXB
);
298 /* Update DB flags */
301 bd
->flags
&= ~BD_TX_READY
;
304 bd
->flags
&= ~BD_TX_PREDEF
;
306 /* Clear Late Collision */
307 bd
->flags
&= ~BD_TX_HFELC
;
309 /* Clear Retransmission Limit */
310 bd
->flags
&= ~BD_TX_CFRL
;
312 /* Clear Retry Count */
313 bd
->flags
&= ~(BD_TX_RC_MASK
<< BD_TX_RC_OFFSET
);
316 bd
->flags
&= ~BD_TX_TOEUN
;
318 /* Clear Truncation */
319 bd
->flags
&= ~BD_TX_TR
;
322 void etsec_walk_tx_ring(eTSEC
*etsec
, int ring_nbr
)
324 hwaddr ring_base
= 0;
329 if (!(etsec
->regs
[MACCFG1
].value
& MACCFG1_TX_EN
)) {
330 RING_DEBUG("%s: MAC Transmit not enabled\n", __func__
);
334 ring_base
= (hwaddr
)(etsec
->regs
[TBASEH
].value
& 0xF) << 32;
335 ring_base
+= etsec
->regs
[TBASE0
+ ring_nbr
].value
& ~0x7;
336 bd_addr
= etsec
->regs
[TBPTR0
+ ring_nbr
].value
& ~0x7;
339 read_buffer_descriptor(etsec
, bd_addr
, &bd
);
344 (bd_addr
- ring_base
) / sizeof(eTSEC_rxtx_bd
));
346 #endif /* DEBUG_BD */
348 /* Save flags before BD update */
351 if (!(bd_flags
& BD_TX_READY
)) {
355 process_tx_bd(etsec
, &bd
);
356 /* Write back BD after update */
357 write_buffer_descriptor(etsec
, bd_addr
, &bd
);
359 /* Wrap or next BD */
360 if (bd_flags
& BD_WRAP
) {
363 bd_addr
+= sizeof(eTSEC_rxtx_bd
);
367 /* Save the Buffer Descriptor Pointers to last bd that was not
368 * successfully closed */
369 etsec
->regs
[TBPTR0
+ ring_nbr
].value
= bd_addr
;
371 /* Set transmit halt THLTx */
372 etsec
->regs
[TSTAT
].value
|= 1 << (31 - ring_nbr
);
376 * rx_init_frame() ensures we never do more padding than this
377 * (checksum plus minimum data packet size)
379 #define MAX_RX_PADDING 64
381 static void fill_rx_bd(eTSEC
*etsec
,
387 hwaddr bufptr
= bd
->bufptr
+
388 ((hwaddr
)(etsec
->regs
[TBDBPH
].value
& 0xF) << 32);
389 uint8_t padd
[MAX_RX_PADDING
];
392 assert(etsec
->rx_padding
<= MAX_RX_PADDING
);
394 RING_DEBUG("eTSEC fill Rx buffer @ 0x%016" HWADDR_PRIx
395 " size:%zu(padding + crc:%u) + fcb:%u\n",
396 bufptr
, *size
, etsec
->rx_padding
, etsec
->rx_fcb_size
);
400 /* This operation will only write FCB */
401 if (etsec
->rx_fcb_size
!= 0) {
403 cpu_physical_memory_write(bufptr
, etsec
->rx_fcb
, etsec
->rx_fcb_size
);
405 bufptr
+= etsec
->rx_fcb_size
;
406 bd
->length
+= etsec
->rx_fcb_size
;
407 etsec
->rx_fcb_size
= 0;
411 /* We remove padding from the computation of to_write because it is not
412 * allocated in the buffer.
414 to_write
= MIN(*size
- etsec
->rx_padding
,
415 etsec
->regs
[MRBLR
].value
- etsec
->rx_fcb_size
);
417 /* This operation can only write packet data and no padding */
419 cpu_physical_memory_write(bufptr
, *buf
, to_write
);
425 bd
->flags
&= ~BD_RX_EMPTY
;
426 bd
->length
+= to_write
;
429 if (*size
== etsec
->rx_padding
) {
430 /* The remaining bytes are only for padding which is not actually
431 * allocated in the data buffer.
434 rem
= MIN(etsec
->regs
[MRBLR
].value
- bd
->length
, etsec
->rx_padding
);
437 memset(padd
, 0x0, rem
);
438 etsec
->rx_padding
-= rem
;
441 cpu_physical_memory_write(bufptr
, padd
, rem
);
446 static void rx_init_frame(eTSEC
*etsec
, const uint8_t *buf
, size_t size
)
448 uint32_t fcb_size
= 0;
449 uint8_t prsdep
= (etsec
->regs
[RCTRL
].value
>> RCTRL_PRSDEP_OFFSET
)
453 /* Prepend FCB (FCB size + RCTRL[PAL]) */
454 fcb_size
= 8 + ((etsec
->regs
[RCTRL
].value
>> 16) & 0x1F);
456 etsec
->rx_fcb_size
= fcb_size
;
458 /* TODO: fill_FCB(etsec); */
459 memset(etsec
->rx_fcb
, 0x0, sizeof(etsec
->rx_fcb
));
462 etsec
->rx_fcb_size
= 0;
465 g_free(etsec
->rx_buffer
);
467 /* Do not copy the frame for now */
468 etsec
->rx_buffer
= (uint8_t *)buf
;
469 etsec
->rx_buffer_len
= size
;
471 /* CRC padding (We don't have to compute the CRC) */
472 etsec
->rx_padding
= 4;
475 * Ensure that payload length + CRC length is at least 802.3
476 * minimum MTU size bytes long (64)
478 if (etsec
->rx_buffer_len
< 60) {
479 etsec
->rx_padding
+= 60 - etsec
->rx_buffer_len
;
482 etsec
->rx_first_in_frame
= 1;
483 etsec
->rx_remaining_data
= etsec
->rx_buffer_len
;
484 RING_DEBUG("%s: rx_buffer_len:%u rx_padding+crc:%u\n", __func__
,
485 etsec
->rx_buffer_len
, etsec
->rx_padding
);
488 ssize_t
etsec_rx_ring_write(eTSEC
*etsec
, const uint8_t *buf
, size_t size
)
490 int ring_nbr
= 0; /* Always use ring0 (no filer) */
492 if (etsec
->rx_buffer_len
!= 0) {
493 RING_DEBUG("%s: We can't receive now,"
494 " a buffer is already in the pipe\n", __func__
);
498 if (etsec
->regs
[RSTAT
].value
& 1 << (23 - ring_nbr
)) {
499 RING_DEBUG("%s: The ring is halted\n", __func__
);
503 if (etsec
->regs
[DMACTRL
].value
& DMACTRL_GRS
) {
504 RING_DEBUG("%s: Graceful receive stop\n", __func__
);
508 if (!(etsec
->regs
[MACCFG1
].value
& MACCFG1_RX_EN
)) {
509 RING_DEBUG("%s: MAC Receive not enabled\n", __func__
);
513 if (!(etsec
->regs
[RCTRL
].value
& RCTRL_RSF
) && (size
< 60)) {
514 /* CRC is not in the packet yet, so short frame is below 60 bytes */
515 RING_DEBUG("%s: Drop short frame\n", __func__
);
519 rx_init_frame(etsec
, buf
, size
);
521 etsec_walk_rx_ring(etsec
, ring_nbr
);
526 void etsec_walk_rx_ring(eTSEC
*etsec
, int ring_nbr
)
528 hwaddr ring_base
= 0;
530 hwaddr start_bd_addr
= 0;
533 size_t remaining_data
;
538 if (etsec
->rx_buffer_len
== 0) {
539 /* No frame to send */
540 RING_DEBUG("No frame to send\n");
544 remaining_data
= etsec
->rx_remaining_data
+ etsec
->rx_padding
;
545 buf
= etsec
->rx_buffer
546 + (etsec
->rx_buffer_len
- etsec
->rx_remaining_data
);
547 size
= etsec
->rx_buffer_len
+ etsec
->rx_padding
;
549 ring_base
= (hwaddr
)(etsec
->regs
[RBASEH
].value
& 0xF) << 32;
550 ring_base
+= etsec
->regs
[RBASE0
+ ring_nbr
].value
& ~0x7;
551 start_bd_addr
= bd_addr
= etsec
->regs
[RBPTR0
+ ring_nbr
].value
& ~0x7;
554 read_buffer_descriptor(etsec
, bd_addr
, &bd
);
559 (bd_addr
- ring_base
) / sizeof(eTSEC_rxtx_bd
));
561 #endif /* DEBUG_BD */
563 /* Save flags before BD update */
566 if (bd_flags
& BD_RX_EMPTY
) {
567 fill_rx_bd(etsec
, &bd
, &buf
, &remaining_data
);
569 if (etsec
->rx_first_in_frame
) {
570 bd
.flags
|= BD_RX_FIRST
;
571 etsec
->rx_first_in_frame
= 0;
572 etsec
->rx_first_bd
= bd
;
576 if (remaining_data
== 0) {
584 /* NOTE: non-octet aligned frame is impossible in qemu */
586 if (size
>= etsec
->regs
[MAXFRM
].value
) {
587 /* frame length violation */
588 qemu_log("%s frame length violation: size:%zu MAXFRM:%d\n",
589 __func__
, size
, etsec
->regs
[MAXFRM
].value
);
591 bd
.flags
|= BD_RX_LG
;
596 bd
.flags
|= BD_RX_SH
;
599 /* TODO: Broadcast and Multicast */
601 if (bd
.flags
& BD_INTERRUPT
) {
603 etsec
->regs
[RSTAT
].value
|= 1 << (7 - ring_nbr
);
606 ievent_set(etsec
, IEVENT_RXF
);
610 if (bd
.flags
& BD_INTERRUPT
) {
612 ievent_set(etsec
, IEVENT_RXB
);
616 /* Write back BD after update */
617 write_buffer_descriptor(etsec
, bd_addr
, &bd
);
620 /* Wrap or next BD */
621 if (bd_flags
& BD_WRAP
) {
624 bd_addr
+= sizeof(eTSEC_rxtx_bd
);
626 } while (remaining_data
!= 0
627 && (bd_flags
& BD_RX_EMPTY
)
628 && bd_addr
!= start_bd_addr
);
631 etsec
->regs
[RBPTR0
+ ring_nbr
].value
= bd_addr
;
633 /* The frame is too large to fit in the Rx ring */
634 if (remaining_data
> 0) {
636 /* Set RSTAT[QHLTx] */
637 etsec
->regs
[RSTAT
].value
|= 1 << (23 - ring_nbr
);
639 /* Save remaining data to send the end of the frame when the ring will
642 etsec
->rx_remaining_data
= remaining_data
;
645 tmp_buf
= g_malloc(size
);
646 memcpy(tmp_buf
, etsec
->rx_buffer
, size
);
647 etsec
->rx_buffer
= tmp_buf
;
649 RING_DEBUG("no empty RxBD available any more\n");
651 etsec
->rx_buffer_len
= 0;
652 etsec
->rx_buffer
= NULL
;
653 if (etsec
->need_flush
) {
654 qemu_flush_queued_packets(qemu_get_queue(etsec
->nic
));
658 RING_DEBUG("eTSEC End of ring_write: remaining_data:%zu\n", remaining_data
);