2 * nRF51 System-on-Chip general purpose input/output register definition
4 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
5 * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf
7 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
13 #include "qemu/osdep.h"
15 #include "qemu/module.h"
16 #include "hw/gpio/nrf51_gpio.h"
18 #include "migration/vmstate.h"
22 * Check if the output driver is connected to the direction switch
23 * given the current configuration and logic level.
24 * It is not differentiated between standard and "high"(-power) drive modes.
26 static bool is_connected(uint32_t config
, uint32_t level
)
29 uint32_t drive_config
= extract32(config
, 8, 3);
31 switch (drive_config
) {
42 g_assert_not_reached();
49 static int pull_value(uint32_t config
)
51 int pull
= extract32(config
, 2, 2);
52 if (pull
== NRF51_GPIO_PULLDOWN
) {
54 } else if (pull
== NRF51_GPIO_PULLUP
) {
60 static void update_output_irq(NRF51GPIOState
*s
, size_t i
,
61 bool connected
, bool level
)
63 int64_t irq_level
= connected
? level
: -1;
64 bool old_connected
= extract32(s
->old_out_connected
, i
, 1);
65 bool old_level
= extract32(s
->old_out
, i
, 1);
67 if ((old_connected
!= connected
) || (old_level
!= level
)) {
68 qemu_set_irq(s
->output
[i
], irq_level
);
69 trace_nrf51_gpio_update_output_irq(i
, irq_level
);
72 s
->old_out
= deposit32(s
->old_out
, i
, 1, level
);
73 s
->old_out_connected
= deposit32(s
->old_out_connected
, i
, 1, connected
);
76 static void update_state(NRF51GPIOState
*s
)
80 bool connected_out
, dir
, connected_in
, out
, in
, input
;
81 bool assert_detect
= false;
83 for (i
= 0; i
< NRF51_GPIO_PINS
; i
++) {
84 pull
= pull_value(s
->cnf
[i
]);
85 dir
= extract32(s
->cnf
[i
], 0, 1);
86 connected_in
= extract32(s
->in_mask
, i
, 1);
87 out
= extract32(s
->out
, i
, 1);
88 in
= extract32(s
->in
, i
, 1);
89 input
= !extract32(s
->cnf
[i
], 1, 1);
90 connected_out
= is_connected(s
->cnf
[i
], out
) && dir
;
94 /* Input buffer disconnected from external drives */
95 s
->in
= deposit32(s
->in
, i
, 1, pull
);
98 if (connected_out
&& connected_in
&& out
!= in
) {
99 /* Pin both driven externally and internally */
100 qemu_log_mask(LOG_GUEST_ERROR
,
101 "GPIO pin %zu short circuited\n", i
);
104 uint32_t detect_config
= extract32(s
->cnf
[i
], 16, 2);
105 if ((detect_config
== 2) && (in
== 1)) {
106 assert_detect
= true;
108 if ((detect_config
== 3) && (in
== 0)) {
109 assert_detect
= true;
113 * Floating input: the output stimulates IN if connected,
114 * otherwise pull-up/pull-down resistors put a value on both
117 if (pull
>= 0 && !connected_out
) {
118 connected_out
= true;
122 s
->in
= deposit32(s
->in
, i
, 1, out
);
126 update_output_irq(s
, i
, connected_out
, out
);
129 qemu_set_irq(s
->detect
, assert_detect
);
133 * Direction is exposed in both the DIR register and the DIR bit
134 * of each PINs CNF configuration register. Reflect bits for pins in DIR
135 * to individual pin configuration registers.
137 static void reflect_dir_bit_in_cnf(NRF51GPIOState
*s
)
141 uint32_t value
= s
->dir
;
143 for (i
= 0; i
< NRF51_GPIO_PINS
; i
++) {
144 s
->cnf
[i
] = (s
->cnf
[i
] & ~(1UL)) | ((value
>> i
) & 0x01);
148 static uint64_t nrf51_gpio_read(void *opaque
, hwaddr offset
, unsigned int size
)
150 NRF51GPIOState
*s
= NRF51_GPIO(opaque
);
155 case NRF51_GPIO_REG_OUT
... NRF51_GPIO_REG_OUTCLR
:
159 case NRF51_GPIO_REG_IN
:
163 case NRF51_GPIO_REG_DIR
... NRF51_GPIO_REG_DIRCLR
:
167 case NRF51_GPIO_REG_CNF_START
... NRF51_GPIO_REG_CNF_END
:
168 idx
= (offset
- NRF51_GPIO_REG_CNF_START
) / 4;
173 qemu_log_mask(LOG_GUEST_ERROR
,
174 "%s: bad read offset 0x%" HWADDR_PRIx
"\n",
178 trace_nrf51_gpio_read(offset
, r
);
183 static void nrf51_gpio_write(void *opaque
, hwaddr offset
,
184 uint64_t value
, unsigned int size
)
186 NRF51GPIOState
*s
= NRF51_GPIO(opaque
);
189 trace_nrf51_gpio_write(offset
, value
);
192 case NRF51_GPIO_REG_OUT
:
196 case NRF51_GPIO_REG_OUTSET
:
200 case NRF51_GPIO_REG_OUTCLR
:
204 case NRF51_GPIO_REG_DIR
:
206 reflect_dir_bit_in_cnf(s
);
209 case NRF51_GPIO_REG_DIRSET
:
211 reflect_dir_bit_in_cnf(s
);
214 case NRF51_GPIO_REG_DIRCLR
:
216 reflect_dir_bit_in_cnf(s
);
219 case NRF51_GPIO_REG_CNF_START
... NRF51_GPIO_REG_CNF_END
:
220 idx
= (offset
- NRF51_GPIO_REG_CNF_START
) / 4;
223 * direction is exposed in both the DIR register and the DIR bit
224 * of each PINs CNF configuration register.
226 s
->dir
= (s
->dir
& ~(1UL << idx
)) | ((value
& 0x01) << idx
);
230 qemu_log_mask(LOG_GUEST_ERROR
,
231 "%s: bad write offset 0x%" HWADDR_PRIx
"\n",
238 static const MemoryRegionOps gpio_ops
= {
239 .read
= nrf51_gpio_read
,
240 .write
= nrf51_gpio_write
,
241 .endianness
= DEVICE_LITTLE_ENDIAN
,
242 .impl
.min_access_size
= 4,
243 .impl
.max_access_size
= 4,
246 static void nrf51_gpio_set(void *opaque
, int line
, int value
)
248 NRF51GPIOState
*s
= NRF51_GPIO(opaque
);
250 trace_nrf51_gpio_set(line
, value
);
252 assert(line
>= 0 && line
< NRF51_GPIO_PINS
);
254 s
->in_mask
= deposit32(s
->in_mask
, line
, 1, value
>= 0);
256 s
->in
= deposit32(s
->in
, line
, 1, value
!= 0);
262 static void nrf51_gpio_reset(DeviceState
*dev
)
264 NRF51GPIOState
*s
= NRF51_GPIO(dev
);
269 s
->old_out_connected
= 0;
274 for (i
= 0; i
< NRF51_GPIO_PINS
; i
++) {
275 s
->cnf
[i
] = 0x00000002;
279 static const VMStateDescription vmstate_nrf51_gpio
= {
280 .name
= TYPE_NRF51_GPIO
,
282 .minimum_version_id
= 1,
283 .fields
= (const VMStateField
[]) {
284 VMSTATE_UINT32(out
, NRF51GPIOState
),
285 VMSTATE_UINT32(in
, NRF51GPIOState
),
286 VMSTATE_UINT32(in_mask
, NRF51GPIOState
),
287 VMSTATE_UINT32(dir
, NRF51GPIOState
),
288 VMSTATE_UINT32_ARRAY(cnf
, NRF51GPIOState
, NRF51_GPIO_PINS
),
289 VMSTATE_UINT32(old_out
, NRF51GPIOState
),
290 VMSTATE_UINT32(old_out_connected
, NRF51GPIOState
),
291 VMSTATE_END_OF_LIST()
295 static void nrf51_gpio_init(Object
*obj
)
297 NRF51GPIOState
*s
= NRF51_GPIO(obj
);
299 memory_region_init_io(&s
->mmio
, obj
, &gpio_ops
, s
,
300 TYPE_NRF51_GPIO
, NRF51_GPIO_SIZE
);
301 sysbus_init_mmio(SYS_BUS_DEVICE(obj
), &s
->mmio
);
303 qdev_init_gpio_in(DEVICE(s
), nrf51_gpio_set
, NRF51_GPIO_PINS
);
304 qdev_init_gpio_out(DEVICE(s
), s
->output
, NRF51_GPIO_PINS
);
305 qdev_init_gpio_out_named(DEVICE(s
), &s
->detect
, "detect", 1);
308 static void nrf51_gpio_class_init(ObjectClass
*klass
, void *data
)
310 DeviceClass
*dc
= DEVICE_CLASS(klass
);
312 dc
->vmsd
= &vmstate_nrf51_gpio
;
313 dc
->reset
= nrf51_gpio_reset
;
314 dc
->desc
= "nRF51 GPIO";
317 static const TypeInfo nrf51_gpio_info
= {
318 .name
= TYPE_NRF51_GPIO
,
319 .parent
= TYPE_SYS_BUS_DEVICE
,
320 .instance_size
= sizeof(NRF51GPIOState
),
321 .instance_init
= nrf51_gpio_init
,
322 .class_init
= nrf51_gpio_class_init
325 static void nrf51_gpio_register_types(void)
327 type_register_static(&nrf51_gpio_info
);
330 type_init(nrf51_gpio_register_types
)