2 * ARM SBSA Reference Platform emulation
4 * Copyright (c) 2018 Linaro Limited
5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qemu/datadir.h"
23 #include "qapi/error.h"
24 #include "qemu/error-report.h"
25 #include "qemu/units.h"
26 #include "sysemu/device_tree.h"
27 #include "sysemu/kvm.h"
28 #include "sysemu/numa.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/sysemu.h"
31 #include "exec/hwaddr.h"
33 #include "hw/arm/boot.h"
34 #include "hw/arm/bsa.h"
35 #include "hw/arm/fdt.h"
36 #include "hw/arm/smmuv3.h"
37 #include "hw/block/flash.h"
38 #include "hw/boards.h"
39 #include "hw/ide/ide-bus.h"
40 #include "hw/ide/ahci-sysbus.h"
41 #include "hw/intc/arm_gicv3_common.h"
42 #include "hw/intc/arm_gicv3_its_common.h"
43 #include "hw/loader.h"
44 #include "hw/pci-host/gpex.h"
45 #include "hw/qdev-properties.h"
47 #include "hw/usb/xhci.h"
48 #include "hw/char/pl011.h"
49 #include "hw/watchdog/sbsa_gwdt.h"
51 #include "qapi/qmp/qlist.h"
52 #include "qom/object.h"
53 #include "target/arm/cpu-qom.h"
54 #include "target/arm/gtimer.h"
56 #define RAMLIMIT_GB 8192
57 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
60 #define NUM_SMMU_IRQS 4
61 #define NUM_SATA_PORTS 6
64 * Generic timer frequency in Hz (which drives both the CPU generic timers
65 * and the SBSA watchdog-timer). Older (<2.11) versions of the TF-A firmware
66 * assumed 62.5MHz here.
68 * Starting with Armv8.6 CPU 1GHz timer frequency is mandated.
70 #define SBSA_GTIMER_HZ 1000000000
99 struct SBSAMachineState
{
101 struct arm_boot_info bootinfo
;
107 PFlashCFI01
*flash
[2];
110 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
111 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState
, SBSA_MACHINE
)
113 static const MemMapEntry sbsa_ref_memmap
[] = {
115 [SBSA_FLASH
] = { 0, 0x20000000 },
116 /* 512M secure memory */
117 [SBSA_SECURE_MEM
] = { 0x20000000, 0x20000000 },
118 /* Space reserved for CPU peripheral devices */
119 [SBSA_CPUPERIPHS
] = { 0x40000000, 0x00040000 },
120 [SBSA_GIC_DIST
] = { 0x40060000, 0x00010000 },
121 [SBSA_GIC_REDIST
] = { 0x40080000, 0x04000000 },
122 [SBSA_GIC_ITS
] = { 0x44081000, 0x00020000 },
123 [SBSA_SECURE_EC
] = { 0x50000000, 0x00001000 },
124 [SBSA_GWDT_REFRESH
] = { 0x50010000, 0x00001000 },
125 [SBSA_GWDT_CONTROL
] = { 0x50011000, 0x00001000 },
126 [SBSA_UART
] = { 0x60000000, 0x00001000 },
127 [SBSA_RTC
] = { 0x60010000, 0x00001000 },
128 [SBSA_GPIO
] = { 0x60020000, 0x00001000 },
129 [SBSA_SECURE_UART
] = { 0x60030000, 0x00001000 },
130 [SBSA_SECURE_UART_MM
] = { 0x60040000, 0x00001000 },
131 [SBSA_SMMU
] = { 0x60050000, 0x00020000 },
132 /* Space here reserved for more SMMUs */
133 [SBSA_AHCI
] = { 0x60100000, 0x00010000 },
134 [SBSA_XHCI
] = { 0x60110000, 0x00010000 },
135 /* Space here reserved for other devices */
136 [SBSA_PCIE_PIO
] = { 0x7fff0000, 0x00010000 },
137 /* 32-bit address PCIE MMIO space */
138 [SBSA_PCIE_MMIO
] = { 0x80000000, 0x70000000 },
139 /* 256M PCIE ECAM space */
140 [SBSA_PCIE_ECAM
] = { 0xf0000000, 0x10000000 },
141 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
142 [SBSA_PCIE_MMIO_HIGH
] = { 0x100000000ULL
, 0xFF00000000ULL
},
143 [SBSA_MEM
] = { 0x10000000000ULL
, RAMLIMIT_BYTES
},
146 static const int sbsa_ref_irqmap
[] = {
149 [SBSA_PCIE
] = 3, /* ... to 6 */
151 [SBSA_SECURE_UART
] = 8,
152 [SBSA_SECURE_UART_MM
] = 9,
155 [SBSA_SMMU
] = 12, /* ... to 15 */
156 [SBSA_GWDT_WS0
] = 16,
159 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState
*sms
, int idx
)
161 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
162 return arm_build_mp_affinity(idx
, clustersz
);
165 static void sbsa_fdt_add_gic_node(SBSAMachineState
*sms
)
169 nodename
= g_strdup_printf("/intc");
170 qemu_fdt_add_subnode(sms
->fdt
, nodename
);
171 qemu_fdt_setprop_sized_cells(sms
->fdt
, nodename
, "reg",
172 2, sbsa_ref_memmap
[SBSA_GIC_DIST
].base
,
173 2, sbsa_ref_memmap
[SBSA_GIC_DIST
].size
,
174 2, sbsa_ref_memmap
[SBSA_GIC_REDIST
].base
,
175 2, sbsa_ref_memmap
[SBSA_GIC_REDIST
].size
);
177 nodename
= g_strdup_printf("/intc/its");
178 qemu_fdt_add_subnode(sms
->fdt
, nodename
);
179 qemu_fdt_setprop_sized_cells(sms
->fdt
, nodename
, "reg",
180 2, sbsa_ref_memmap
[SBSA_GIC_ITS
].base
,
181 2, sbsa_ref_memmap
[SBSA_GIC_ITS
].size
);
187 * Firmware on this machine only uses ACPI table to load OS, these limited
188 * device tree nodes are just to let firmware know the info which varies from
189 * command line parameters, so it is not necessary to be fully compatible
190 * with the kernel CPU and NUMA binding rules.
192 static void create_fdt(SBSAMachineState
*sms
)
194 void *fdt
= create_device_tree(&sms
->fdt_size
);
195 const MachineState
*ms
= MACHINE(sms
);
196 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
200 error_report("create_device_tree() failed");
206 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,sbsa-ref");
207 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
208 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
211 * This versioning scheme is for informing platform fw only. It is neither:
212 * - A QEMU versioned machine type; a given version of QEMU will emulate
213 * a given version of the platform.
214 * - A reflection of level of SBSA (now SystemReady SR) support provided.
216 * machine-version-major: updated when changes breaking fw compatibility
218 * machine-version-minor: updated when features are added that don't break
221 qemu_fdt_setprop_cell(fdt
, "/", "machine-version-major", 0);
222 qemu_fdt_setprop_cell(fdt
, "/", "machine-version-minor", 4);
224 if (ms
->numa_state
->have_numa_distance
) {
225 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
226 uint32_t *matrix
= g_malloc0(size
);
229 for (i
= 0; i
< nb_numa_nodes
; i
++) {
230 for (j
= 0; j
< nb_numa_nodes
; j
++) {
231 idx
= (i
* nb_numa_nodes
+ j
) * 3;
232 matrix
[idx
+ 0] = cpu_to_be32(i
);
233 matrix
[idx
+ 1] = cpu_to_be32(j
);
235 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
239 qemu_fdt_add_subnode(fdt
, "/distance-map");
240 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
246 * From Documentation/devicetree/bindings/arm/cpus.yaml
247 * On ARM v8 64-bit systems this property is required
248 * and matches the MPIDR_EL1 register affinity bits.
250 * * If cpus node's #address-cells property is set to 2
252 * The first reg cell bits [7:0] must be set to
253 * bits [39:32] of MPIDR_EL1.
255 * The second reg cell bits [23:0] must be set to
256 * bits [23:0] of MPIDR_EL1.
258 qemu_fdt_add_subnode(sms
->fdt
, "/cpus");
259 qemu_fdt_setprop_cell(sms
->fdt
, "/cpus", "#address-cells", 2);
260 qemu_fdt_setprop_cell(sms
->fdt
, "/cpus", "#size-cells", 0x0);
262 for (cpu
= sms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
263 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
264 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
265 CPUState
*cs
= CPU(armcpu
);
266 uint64_t mpidr
= sbsa_ref_cpu_mp_affinity(sms
, cpu
);
268 qemu_fdt_add_subnode(sms
->fdt
, nodename
);
269 qemu_fdt_setprop_u64(sms
->fdt
, nodename
, "reg", mpidr
);
271 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
272 qemu_fdt_setprop_cell(sms
->fdt
, nodename
, "numa-node-id",
273 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
279 /* Add CPU topology description through fdt node topology. */
280 qemu_fdt_add_subnode(sms
->fdt
, "/cpus/topology");
282 qemu_fdt_setprop_cell(sms
->fdt
, "/cpus/topology", "sockets", ms
->smp
.sockets
);
283 qemu_fdt_setprop_cell(sms
->fdt
, "/cpus/topology", "clusters", ms
->smp
.clusters
);
284 qemu_fdt_setprop_cell(sms
->fdt
, "/cpus/topology", "cores", ms
->smp
.cores
);
285 qemu_fdt_setprop_cell(sms
->fdt
, "/cpus/topology", "threads", ms
->smp
.threads
);
287 sbsa_fdt_add_gic_node(sms
);
290 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
292 static PFlashCFI01
*sbsa_flash_create1(SBSAMachineState
*sms
,
294 const char *alias_prop_name
)
297 * Create a single flash device. We use the same parameters as
298 * the flash devices on the Versatile Express board.
300 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
302 qdev_prop_set_uint64(dev
, "sector-length", SBSA_FLASH_SECTOR_SIZE
);
303 qdev_prop_set_uint8(dev
, "width", 4);
304 qdev_prop_set_uint8(dev
, "device-width", 2);
305 qdev_prop_set_bit(dev
, "big-endian", false);
306 qdev_prop_set_uint16(dev
, "id0", 0x89);
307 qdev_prop_set_uint16(dev
, "id1", 0x18);
308 qdev_prop_set_uint16(dev
, "id2", 0x00);
309 qdev_prop_set_uint16(dev
, "id3", 0x00);
310 qdev_prop_set_string(dev
, "name", name
);
311 object_property_add_child(OBJECT(sms
), name
, OBJECT(dev
));
312 object_property_add_alias(OBJECT(sms
), alias_prop_name
,
313 OBJECT(dev
), "drive");
314 return PFLASH_CFI01(dev
);
317 static void sbsa_flash_create(SBSAMachineState
*sms
)
319 sms
->flash
[0] = sbsa_flash_create1(sms
, "sbsa.flash0", "pflash0");
320 sms
->flash
[1] = sbsa_flash_create1(sms
, "sbsa.flash1", "pflash1");
323 static void sbsa_flash_map1(PFlashCFI01
*flash
,
324 hwaddr base
, hwaddr size
,
325 MemoryRegion
*sysmem
)
327 DeviceState
*dev
= DEVICE(flash
);
329 assert(QEMU_IS_ALIGNED(size
, SBSA_FLASH_SECTOR_SIZE
));
330 assert(size
/ SBSA_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
331 qdev_prop_set_uint32(dev
, "num-blocks", size
/ SBSA_FLASH_SECTOR_SIZE
);
332 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
334 memory_region_add_subregion(sysmem
, base
,
335 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
339 static void sbsa_flash_map(SBSAMachineState
*sms
,
340 MemoryRegion
*sysmem
,
341 MemoryRegion
*secure_sysmem
)
344 * Map two flash devices to fill the SBSA_FLASH space in the memmap.
345 * sysmem is the system memory space. secure_sysmem is the secure view
346 * of the system, and the first flash device should be made visible only
347 * there. The second flash device is visible to both secure and nonsecure.
349 hwaddr flashsize
= sbsa_ref_memmap
[SBSA_FLASH
].size
/ 2;
350 hwaddr flashbase
= sbsa_ref_memmap
[SBSA_FLASH
].base
;
352 sbsa_flash_map1(sms
->flash
[0], flashbase
, flashsize
,
354 sbsa_flash_map1(sms
->flash
[1], flashbase
+ flashsize
, flashsize
,
358 static bool sbsa_firmware_init(SBSAMachineState
*sms
,
359 MemoryRegion
*sysmem
,
360 MemoryRegion
*secure_sysmem
)
362 const char *bios_name
;
364 BlockBackend
*pflash_blk0
;
366 /* Map legacy -drive if=pflash to machine properties */
367 for (i
= 0; i
< ARRAY_SIZE(sms
->flash
); i
++) {
368 pflash_cfi01_legacy_drive(sms
->flash
[i
],
369 drive_get(IF_PFLASH
, 0, i
));
372 sbsa_flash_map(sms
, sysmem
, secure_sysmem
);
374 pflash_blk0
= pflash_cfi01_get_blk(sms
->flash
[0]);
376 bios_name
= MACHINE(sms
)->firmware
;
383 error_report("The contents of the first flash device may be "
384 "specified with -bios or with -drive if=pflash... "
385 "but you cannot use both options at once");
389 /* Fall back to -bios */
391 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
393 error_report("Could not find ROM image '%s'", bios_name
);
396 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(sms
->flash
[0]), 0);
397 image_size
= load_image_mr(fname
, mr
);
399 if (image_size
< 0) {
400 error_report("Could not load ROM image '%s'", bios_name
);
405 return pflash_blk0
|| bios_name
;
408 static void create_secure_ram(SBSAMachineState
*sms
,
409 MemoryRegion
*secure_sysmem
)
411 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
412 hwaddr base
= sbsa_ref_memmap
[SBSA_SECURE_MEM
].base
;
413 hwaddr size
= sbsa_ref_memmap
[SBSA_SECURE_MEM
].size
;
415 memory_region_init_ram(secram
, NULL
, "sbsa-ref.secure-ram", size
,
417 memory_region_add_subregion(secure_sysmem
, base
, secram
);
420 static void create_its(SBSAMachineState
*sms
)
422 const char *itsclass
= its_class_name();
425 dev
= qdev_new(itsclass
);
427 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(sms
->gic
),
429 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
430 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, sbsa_ref_memmap
[SBSA_GIC_ITS
].base
);
433 static void create_gic(SBSAMachineState
*sms
, MemoryRegion
*mem
)
435 unsigned int smp_cpus
= MACHINE(sms
)->smp
.cpus
;
436 SysBusDevice
*gicbusdev
;
438 uint32_t redist0_capacity
, redist0_count
;
439 QList
*redist_region_count
;
442 gictype
= gicv3_class_name();
444 sms
->gic
= qdev_new(gictype
);
445 qdev_prop_set_uint32(sms
->gic
, "revision", 3);
446 qdev_prop_set_uint32(sms
->gic
, "num-cpu", smp_cpus
);
448 * Note that the num-irq property counts both internal and external
449 * interrupts; there are always 32 of the former (mandated by GIC spec).
451 qdev_prop_set_uint32(sms
->gic
, "num-irq", NUM_IRQS
+ 32);
452 qdev_prop_set_bit(sms
->gic
, "has-security-extensions", true);
455 sbsa_ref_memmap
[SBSA_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
456 redist0_count
= MIN(smp_cpus
, redist0_capacity
);
458 redist_region_count
= qlist_new();
459 qlist_append_int(redist_region_count
, redist0_count
);
460 qdev_prop_set_array(sms
->gic
, "redist-region-count", redist_region_count
);
462 object_property_set_link(OBJECT(sms
->gic
), "sysmem",
463 OBJECT(mem
), &error_fatal
);
464 qdev_prop_set_bit(sms
->gic
, "has-lpi", true);
466 gicbusdev
= SYS_BUS_DEVICE(sms
->gic
);
467 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
468 sysbus_mmio_map(gicbusdev
, 0, sbsa_ref_memmap
[SBSA_GIC_DIST
].base
);
469 sysbus_mmio_map(gicbusdev
, 1, sbsa_ref_memmap
[SBSA_GIC_REDIST
].base
);
472 * Wire the outputs from each CPU's generic timer and the GICv3
473 * maintenance interrupt signal to the appropriate GIC PPI inputs,
474 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
476 for (i
= 0; i
< smp_cpus
; i
++) {
477 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
478 int intidbase
= NUM_IRQS
+ i
* GIC_INTERNAL
;
481 * Mapping from the output timer irq lines from the CPU to the
482 * GIC PPI inputs used for this board.
484 const int timer_irq
[] = {
485 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
486 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
487 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
488 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
489 [GTIMER_HYPVIRT
] = ARCH_TIMER_NS_EL2_VIRT_IRQ
,
492 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
493 qdev_connect_gpio_out(cpudev
, irq
,
494 qdev_get_gpio_in(sms
->gic
,
495 intidbase
+ timer_irq
[irq
]));
498 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt", 0,
499 qdev_get_gpio_in(sms
->gic
,
501 + ARCH_GIC_MAINT_IRQ
));
503 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
504 qdev_get_gpio_in(sms
->gic
,
508 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
509 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
510 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
511 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
512 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
513 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
514 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
519 static void create_uart(const SBSAMachineState
*sms
, int uart
,
520 MemoryRegion
*mem
, Chardev
*chr
)
522 hwaddr base
= sbsa_ref_memmap
[uart
].base
;
523 int irq
= sbsa_ref_irqmap
[uart
];
524 DeviceState
*dev
= qdev_new(TYPE_PL011
);
525 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
527 qdev_prop_set_chr(dev
, "chardev", chr
);
528 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
529 memory_region_add_subregion(mem
, base
,
530 sysbus_mmio_get_region(s
, 0));
531 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(sms
->gic
, irq
));
534 static void create_rtc(const SBSAMachineState
*sms
)
536 hwaddr base
= sbsa_ref_memmap
[SBSA_RTC
].base
;
537 int irq
= sbsa_ref_irqmap
[SBSA_RTC
];
539 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(sms
->gic
, irq
));
542 static void create_wdt(const SBSAMachineState
*sms
)
544 hwaddr rbase
= sbsa_ref_memmap
[SBSA_GWDT_REFRESH
].base
;
545 hwaddr cbase
= sbsa_ref_memmap
[SBSA_GWDT_CONTROL
].base
;
546 DeviceState
*dev
= qdev_new(TYPE_WDT_SBSA
);
547 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
548 int irq
= sbsa_ref_irqmap
[SBSA_GWDT_WS0
];
550 qdev_prop_set_uint64(dev
, "clock-frequency", SBSA_GTIMER_HZ
);
551 sysbus_realize_and_unref(s
, &error_fatal
);
552 sysbus_mmio_map(s
, 0, rbase
);
553 sysbus_mmio_map(s
, 1, cbase
);
554 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(sms
->gic
, irq
));
557 static DeviceState
*gpio_key_dev
;
558 static void sbsa_ref_powerdown_req(Notifier
*n
, void *opaque
)
560 /* use gpio Pin 3 for power button event */
561 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
564 static Notifier sbsa_ref_powerdown_notifier
= {
565 .notify
= sbsa_ref_powerdown_req
568 static void create_gpio(const SBSAMachineState
*sms
)
570 DeviceState
*pl061_dev
;
571 hwaddr base
= sbsa_ref_memmap
[SBSA_GPIO
].base
;
572 int irq
= sbsa_ref_irqmap
[SBSA_GPIO
];
574 pl061_dev
= sysbus_create_simple("pl061", base
,
575 qdev_get_gpio_in(sms
->gic
, irq
));
577 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
578 qdev_get_gpio_in(pl061_dev
, 3));
580 /* connect powerdown request */
581 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier
);
584 static void create_ahci(const SBSAMachineState
*sms
)
586 hwaddr base
= sbsa_ref_memmap
[SBSA_AHCI
].base
;
587 int irq
= sbsa_ref_irqmap
[SBSA_AHCI
];
589 DriveInfo
*hd
[NUM_SATA_PORTS
];
590 SysbusAHCIState
*sysahci
;
592 dev
= qdev_new("sysbus-ahci");
593 qdev_prop_set_uint32(dev
, "num-ports", NUM_SATA_PORTS
);
594 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
595 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
596 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(sms
->gic
, irq
));
598 sysahci
= SYSBUS_AHCI(dev
);
599 ide_drive_get(hd
, ARRAY_SIZE(hd
));
600 ahci_ide_create_devs(&sysahci
->ahci
, hd
);
603 static void create_xhci(const SBSAMachineState
*sms
)
605 hwaddr base
= sbsa_ref_memmap
[SBSA_XHCI
].base
;
606 int irq
= sbsa_ref_irqmap
[SBSA_XHCI
];
607 DeviceState
*dev
= qdev_new(TYPE_XHCI_SYSBUS
);
608 qdev_prop_set_uint32(dev
, "slots", XHCI_MAXSLOTS
);
610 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
611 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
612 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(sms
->gic
, irq
));
615 static void create_smmu(const SBSAMachineState
*sms
, PCIBus
*bus
)
617 hwaddr base
= sbsa_ref_memmap
[SBSA_SMMU
].base
;
618 int irq
= sbsa_ref_irqmap
[SBSA_SMMU
];
622 dev
= qdev_new(TYPE_ARM_SMMUV3
);
624 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
626 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
627 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
628 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
629 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
630 qdev_get_gpio_in(sms
->gic
, irq
+ i
));
634 static void create_pcie(SBSAMachineState
*sms
)
636 hwaddr base_ecam
= sbsa_ref_memmap
[SBSA_PCIE_ECAM
].base
;
637 hwaddr size_ecam
= sbsa_ref_memmap
[SBSA_PCIE_ECAM
].size
;
638 hwaddr base_mmio
= sbsa_ref_memmap
[SBSA_PCIE_MMIO
].base
;
639 hwaddr size_mmio
= sbsa_ref_memmap
[SBSA_PCIE_MMIO
].size
;
640 hwaddr base_mmio_high
= sbsa_ref_memmap
[SBSA_PCIE_MMIO_HIGH
].base
;
641 hwaddr size_mmio_high
= sbsa_ref_memmap
[SBSA_PCIE_MMIO_HIGH
].size
;
642 hwaddr base_pio
= sbsa_ref_memmap
[SBSA_PCIE_PIO
].base
;
643 int irq
= sbsa_ref_irqmap
[SBSA_PCIE
];
644 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
645 MemoryRegion
*mmio_alias
, *mmio_alias_high
, *mmio_reg
;
646 MemoryRegion
*ecam_alias
, *ecam_reg
;
651 dev
= qdev_new(TYPE_GPEX_HOST
);
652 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
655 ecam_alias
= g_new0(MemoryRegion
, 1);
656 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
657 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
658 ecam_reg
, 0, size_ecam
);
659 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
661 /* Map the MMIO space */
662 mmio_alias
= g_new0(MemoryRegion
, 1);
663 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
664 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
665 mmio_reg
, base_mmio
, size_mmio
);
666 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
668 /* Map the MMIO_HIGH space */
669 mmio_alias_high
= g_new0(MemoryRegion
, 1);
670 memory_region_init_alias(mmio_alias_high
, OBJECT(dev
), "pcie-mmio-high",
671 mmio_reg
, base_mmio_high
, size_mmio_high
);
672 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
675 /* Map IO port space */
676 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
678 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
679 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
680 qdev_get_gpio_in(sms
->gic
, irq
+ i
));
681 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
684 pci
= PCI_HOST_BRIDGE(dev
);
686 pci_init_nic_devices(pci
->bus
, mc
->default_nic
);
688 pci_create_simple(pci
->bus
, -1, "bochs-display");
690 create_smmu(sms
, pci
->bus
);
693 static void *sbsa_ref_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
695 const SBSAMachineState
*board
= container_of(binfo
, SBSAMachineState
,
698 *fdt_size
= board
->fdt_size
;
702 static void create_secure_ec(MemoryRegion
*mem
)
704 hwaddr base
= sbsa_ref_memmap
[SBSA_SECURE_EC
].base
;
705 DeviceState
*dev
= qdev_new("sbsa-ec");
706 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
708 memory_region_add_subregion(mem
, base
,
709 sysbus_mmio_get_region(s
, 0));
712 static void sbsa_ref_init(MachineState
*machine
)
714 unsigned int smp_cpus
= machine
->smp
.cpus
;
715 unsigned int max_cpus
= machine
->smp
.max_cpus
;
716 SBSAMachineState
*sms
= SBSA_MACHINE(machine
);
717 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
718 MemoryRegion
*sysmem
= get_system_memory();
719 MemoryRegion
*secure_sysmem
= g_new(MemoryRegion
, 1);
720 bool firmware_loaded
;
721 const CPUArchIdList
*possible_cpus
;
722 int n
, sbsa_max_cpus
;
725 error_report("sbsa-ref: KVM is not supported for this machine");
730 * The Secure view of the world is the same as the NonSecure,
731 * but with a few extra devices. Create it as a container region
732 * containing the system memory at low priority; any secure-only
733 * devices go in at higher priority and take precedence.
735 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
737 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
739 firmware_loaded
= sbsa_firmware_init(sms
, sysmem
, secure_sysmem
);
742 * This machine has EL3 enabled, external firmware should supply PSCI
743 * implementation, so the QEMU's internal PSCI is disabled.
745 sms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
747 sbsa_max_cpus
= sbsa_ref_memmap
[SBSA_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
749 if (max_cpus
> sbsa_max_cpus
) {
750 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
751 "supported by machine 'sbsa-ref' (%d)",
752 max_cpus
, sbsa_max_cpus
);
756 sms
->smp_cpus
= smp_cpus
;
758 if (machine
->ram_size
> sbsa_ref_memmap
[SBSA_MEM
].size
) {
759 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB
);
763 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
764 for (n
= 0; n
< possible_cpus
->len
; n
++) {
772 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
773 object_property_set_int(cpuobj
, "mp-affinity",
774 possible_cpus
->cpus
[n
].arch_id
, NULL
);
779 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
782 if (object_property_find(cpuobj
, "reset-cbar")) {
783 object_property_set_int(cpuobj
, "reset-cbar",
784 sbsa_ref_memmap
[SBSA_CPUPERIPHS
].base
,
788 object_property_set_int(cpuobj
, "cntfrq", SBSA_GTIMER_HZ
, &error_abort
);
790 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
793 object_property_set_link(cpuobj
, "secure-memory",
794 OBJECT(secure_sysmem
), &error_abort
);
796 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
797 object_unref(cpuobj
);
800 memory_region_add_subregion(sysmem
, sbsa_ref_memmap
[SBSA_MEM
].base
,
805 create_secure_ram(sms
, secure_sysmem
);
807 create_gic(sms
, sysmem
);
809 create_uart(sms
, SBSA_UART
, sysmem
, serial_hd(0));
810 create_uart(sms
, SBSA_SECURE_UART
, secure_sysmem
, serial_hd(1));
811 /* Second secure UART for RAS and MM from EL0 */
812 create_uart(sms
, SBSA_SECURE_UART_MM
, secure_sysmem
, serial_hd(2));
826 create_secure_ec(secure_sysmem
);
828 sms
->bootinfo
.ram_size
= machine
->ram_size
;
829 sms
->bootinfo
.board_id
= -1;
830 sms
->bootinfo
.loader_start
= sbsa_ref_memmap
[SBSA_MEM
].base
;
831 sms
->bootinfo
.get_dtb
= sbsa_ref_dtb
;
832 sms
->bootinfo
.firmware_loaded
= firmware_loaded
;
833 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &sms
->bootinfo
);
836 static const CPUArchIdList
*sbsa_ref_possible_cpu_arch_ids(MachineState
*ms
)
838 unsigned int max_cpus
= ms
->smp
.max_cpus
;
839 SBSAMachineState
*sms
= SBSA_MACHINE(ms
);
842 if (ms
->possible_cpus
) {
843 assert(ms
->possible_cpus
->len
== max_cpus
);
844 return ms
->possible_cpus
;
847 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
848 sizeof(CPUArchId
) * max_cpus
);
849 ms
->possible_cpus
->len
= max_cpus
;
850 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
851 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
852 ms
->possible_cpus
->cpus
[n
].arch_id
=
853 sbsa_ref_cpu_mp_affinity(sms
, n
);
854 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
855 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
857 return ms
->possible_cpus
;
860 static CpuInstanceProperties
861 sbsa_ref_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
863 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
864 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
866 assert(cpu_index
< possible_cpus
->len
);
867 return possible_cpus
->cpus
[cpu_index
].props
;
871 sbsa_ref_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
873 return idx
% ms
->numa_state
->num_nodes
;
876 static void sbsa_ref_instance_init(Object
*obj
)
878 SBSAMachineState
*sms
= SBSA_MACHINE(obj
);
880 sbsa_flash_create(sms
);
883 static void sbsa_ref_class_init(ObjectClass
*oc
, void *data
)
885 MachineClass
*mc
= MACHINE_CLASS(oc
);
886 static const char * const valid_cpu_types
[] = {
887 ARM_CPU_TYPE_NAME("cortex-a57"),
888 ARM_CPU_TYPE_NAME("cortex-a72"),
889 ARM_CPU_TYPE_NAME("neoverse-n1"),
890 ARM_CPU_TYPE_NAME("neoverse-v1"),
891 ARM_CPU_TYPE_NAME("neoverse-n2"),
892 ARM_CPU_TYPE_NAME("max"),
896 mc
->init
= sbsa_ref_init
;
897 mc
->desc
= "QEMU 'SBSA Reference' ARM Virtual Machine";
898 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("neoverse-n2");
899 mc
->valid_cpu_types
= valid_cpu_types
;
901 mc
->pci_allow_0_address
= true;
902 mc
->minimum_page_bits
= 12;
903 mc
->block_default_type
= IF_IDE
;
905 mc
->default_nic
= "e1000e";
906 mc
->default_ram_size
= 1 * GiB
;
907 mc
->default_ram_id
= "sbsa-ref.ram";
908 mc
->default_cpus
= 4;
909 mc
->smp_props
.clusters_supported
= true;
910 mc
->possible_cpu_arch_ids
= sbsa_ref_possible_cpu_arch_ids
;
911 mc
->cpu_index_to_instance_props
= sbsa_ref_cpu_index_to_props
;
912 mc
->get_default_cpu_node_id
= sbsa_ref_get_default_cpu_node_id
;
913 /* platform instead of architectural choice */
914 mc
->cpu_cluster_has_numa_boundary
= true;
917 static const TypeInfo sbsa_ref_info
= {
918 .name
= TYPE_SBSA_MACHINE
,
919 .parent
= TYPE_MACHINE
,
920 .instance_init
= sbsa_ref_instance_init
,
921 .class_init
= sbsa_ref_class_init
,
922 .instance_size
= sizeof(SBSAMachineState
),
925 static void sbsa_ref_machine_init(void)
927 type_register_static(&sbsa_ref_info
);
930 type_init(sbsa_ref_machine_init
);