hw/arm/s3c24xx.h

   1 /* hw/s3c24xx.h
   2  *
   3  * Samsung s3c24xx cpu state and functions.
   4  *
   5  * Copyright 2006, 2007, 2008 Daniel Silverstone and Vincent Sanders
   6  *
   7  * Copyright 2010, 2013 Stefan Weil
   8  *
   9  * This file is under the terms of the GNU General Public License Version 2.
  10  */
  11
  12 #ifndef S3C24XX_H
  13 #define S3C24XX_H 1
  14
  15 #include "hw/block/flash.h"
  16
  17 typedef struct S3C24xxGpioState S3C24xxGpioState;
  18
  19 /* This structure type encapsulates the state of a S3C24XX SoC. */
  20 typedef struct S3CState_s {
  21     MemoryRegion sdram0;
  22     MemoryRegion sdram1;
  23     MemoryRegion sdram2;
  24     MemoryRegion sram;
  25
  26     ARMCPU *cpu;
  27
  28     /* Memory controller state */
  29     struct s3c24xx_memc_state_s *memc;
  30
  31     /* IRQ controller state */
  32     struct s3c24xx_irq_state_s *irq;
  33
  34     /* Clock and power control */
  35     struct s3c24xx_clkcon_state_s *clkcon;
  36
  37     /* timer controller */
  38     struct s3c24xx_timers_state_s *timers;
  39
  40     /* Serial ports */
  41     struct s3c24xx_serial_dev_s *uart[3];
  42
  43     /* Real time clock */
  44     struct s3c24xx_rtc_state_s *rtc;
  45
  46     /* GPIO */
  47     S3C24xxGpioState *gpio;
  48
  49     /* I2C */
  50     struct s3c24xx_i2c_state_s *iic;
  51
  52     /* NAND controller */
  53     struct s3c24xx_nand_state_s *nand;
  54 } S3CState;
  55
  56
  57 /* initialise memory controller peripheral */
  58 struct s3c24xx_memc_state_s *s3c24xx_memc_init(hwaddr base_addr);
  59
  60 /* initialise the IRQ controller */
  61 struct s3c24xx_irq_state_s *s3c24xx_irq_init(S3CState *soc, hwaddr base_addr);
  62
  63 /* get the qemu interrupt from an irq number */
  64 qemu_irq s3c24xx_get_irq(struct s3c24xx_irq_state_s *s, unsigned inum);
  65
  66 /* initialise clock controller */
  67 struct s3c24xx_clkcon_state_s *s3c24xx_clkcon_init(S3CState *soc, hwaddr base_addr, uint32_t ref_freq);
  68
  69 /* initialise timer controller */
  70 struct s3c24xx_timers_state_s *s3c24xx_timers_init(S3CState *soc, hwaddr base_addr, uint32_t tclk0, uint32_t tclk1);
  71
  72 /* initialise a serial port controller */
  73 struct s3c24xx_serial_dev_s *s3c24xx_serial_init(S3CState *soc, Chardev *chr, hwaddr base_addr, int irqn);
  74
  75 /* Initialise real time clock */
  76 struct s3c24xx_rtc_state_s *s3c24xx_rtc_init(hwaddr base_addr);
  77
  78 /* initialise GPIO */
  79 S3C24xxGpioState *s3c24xx_gpio_init(S3CState *soc, hwaddr base_addr, uint32_t cpu_id);
  80
  81 /* get the qemu interrupt from an eirq number */
  82 qemu_irq s3c24xx_get_eirq(S3C24xxGpioState *s, unsigned einum);
  83
  84 /* Initialise I2c controller */
  85 struct s3c24xx_i2c_state_s *s3c24xx_iic_init(qemu_irq irq, hwaddr base_addr);
  86
  87 /* acquire bus from controller state */
  88 I2CBus *s3c24xx_i2c_bus(struct s3c24xx_i2c_state_s *s);
  89
  90 /* Initialise nand controller */
  91 struct s3c24xx_nand_state_s *s3c24xx_nand_init(hwaddr base_addr);
  92
  93 /* set nand controller context */
  94 void s3c24xx_nand_attach(struct s3c24xx_nand_state_s *s, DeviceState *nand);
  95
  96 #endif /* S3C24XX_H */