hw/arm/sabrelite.c

   1 /*
   2  * SABRELITE Board System emulation.
   3  *
   4  * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
   5  *
   6  * This code is licensed under the GPL, version 2 or later.
   7  * See the file `COPYING' in the top level directory.
   8  *
   9  * It (partially) emulates a sabrelite board, with a Freescale
  10  * i.MX6 SoC
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "qemu-common.h"
  16 #include "hw/arm/fsl-imx6.h"
  17 #include "hw/boards.h"
  18 #include "sysemu/sysemu.h"
  19 #include "qemu/error-report.h"
  20 #include "sysemu/qtest.h"
  21
  22 typedef struct IMX6Sabrelite {
  23     FslIMX6State soc;
  24     MemoryRegion ram;
  25 } IMX6Sabrelite;
  26
  27 static struct arm_boot_info sabrelite_binfo = {
  28     /* DDR memory start */
  29     .loader_start = FSL_IMX6_MMDC_ADDR,
  30     /* No board ID, we boot from DT tree */
  31     .board_id = -1,
  32 };
  33
  34 /* No need to do any particular setup for secondary boot */
  35 static void sabrelite_write_secondary(ARMCPU *cpu,
  36                                       const struct arm_boot_info *info)
  37 {
  38 }
  39
  40 /* Secondary cores are reset through SRC device */
  41 static void sabrelite_reset_secondary(ARMCPU *cpu,
  42                                       const struct arm_boot_info *info)
  43 {
  44 }
  45
  46 static void sabrelite_init(MachineState *machine)
  47 {
  48     IMX6Sabrelite *s = g_new0(IMX6Sabrelite, 1);
  49     Error *err = NULL;
  50
  51     /* Check the amount of memory is compatible with the SOC */
  52     if (machine->ram_size > FSL_IMX6_MMDC_SIZE) {
  53         error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
  54                      machine->ram_size, FSL_IMX6_MMDC_SIZE);
  55         exit(1);
  56     }
  57
  58     object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX6);
  59     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
  60                               &error_abort);
  61
  62     object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
  63     if (err != NULL) {
  64         error_report("%s", error_get_pretty(err));
  65         exit(1);
  66     }
  67
  68     memory_region_allocate_system_memory(&s->ram, NULL, "sabrelite.ram",
  69                                          machine->ram_size);
  70     memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR,
  71                                 &s->ram);
  72
  73     {
  74         /*
  75          * TODO: Ideally we would expose the chip select and spi bus on the
  76          * SoC object using alias properties; then we would not need to
  77          * directly access the underlying spi device object.
  78          */
  79         /* Add the sst25vf016b NOR FLASH memory to first SPI */
  80         Object *spi_dev;
  81
  82         spi_dev = object_resolve_path_component(OBJECT(&s->soc), "spi1");
  83         if (spi_dev) {
  84             SSIBus *spi_bus;
  85
  86             spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(spi_dev), "spi");
  87             if (spi_bus) {
  88                 DeviceState *flash_dev;
  89                 qemu_irq cs_line;
  90                 DriveInfo *dinfo = drive_get_next(IF_MTD);
  91
  92                 flash_dev = ssi_create_slave_no_init(spi_bus, "sst25vf016b");
  93                 if (dinfo) {
  94                     qdev_prop_set_drive(flash_dev, "drive",
  95                                         blk_by_legacy_dinfo(dinfo),
  96                                         &error_fatal);
  97                 }
  98                 qdev_init_nofail(flash_dev);
  99
 100                 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 101                 sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
 102             }
 103         }
 104     }
 105
 106     sabrelite_binfo.ram_size = machine->ram_size;
 107     sabrelite_binfo.kernel_filename = machine->kernel_filename;
 108     sabrelite_binfo.kernel_cmdline = machine->kernel_cmdline;
 109     sabrelite_binfo.initrd_filename = machine->initrd_filename;
 110     sabrelite_binfo.nb_cpus = smp_cpus;
 111     sabrelite_binfo.secure_boot = true;
 112     sabrelite_binfo.write_secondary_boot = sabrelite_write_secondary;
 113     sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary;
 114
 115     if (!qtest_enabled()) {
 116         arm_load_kernel(&s->soc.cpu[0], &sabrelite_binfo);
 117     }
 118 }
 119
 120 static void sabrelite_machine_init(MachineClass *mc)
 121 {
 122     mc->desc = "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)";
 123     mc->init = sabrelite_init;
 124     mc->max_cpus = FSL_IMX6_NUM_CPUS;
 125     mc->ignore_memory_transaction_failures = true;
 126 }
 127
 128 DEFINE_MACHINE("sabrelite", sabrelite_machine_init)