hw/net/xgmac.c

   1 /*
   2  * QEMU model of XGMAC Ethernet.
   3  *
   4  * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
   5  *
   6  * Copyright (c) 2011 Calxeda, Inc.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/sysbus.h"
  29 #include "sysemu/char.h"
  30 #include "qemu/log.h"
  31 #include "net/net.h"
  32 #include "net/checksum.h"
  33
  34 #ifdef DEBUG_XGMAC
  35 #define DEBUGF_BRK(message, args...) do { \
  36                                          fprintf(stderr, (message), ## args); \
  37                                      } while (0)
  38 #else
  39 #define DEBUGF_BRK(message, args...) do { } while (0)
  40 #endif
  41
  42 #define XGMAC_CONTROL           0x00000000   /* MAC Configuration */
  43 #define XGMAC_FRAME_FILTER      0x00000001   /* MAC Frame Filter */
  44 #define XGMAC_FLOW_CTRL         0x00000006   /* MAC Flow Control */
  45 #define XGMAC_VLAN_TAG          0x00000007   /* VLAN Tags */
  46 #define XGMAC_VERSION           0x00000008   /* Version */
  47 /* VLAN tag for insertion or replacement into tx frames */
  48 #define XGMAC_VLAN_INCL         0x00000009
  49 #define XGMAC_LPI_CTRL          0x0000000a   /* LPI Control and Status */
  50 #define XGMAC_LPI_TIMER         0x0000000b   /* LPI Timers Control */
  51 #define XGMAC_TX_PACE           0x0000000c   /* Transmit Pace and Stretch */
  52 #define XGMAC_VLAN_HASH         0x0000000d   /* VLAN Hash Table */
  53 #define XGMAC_DEBUG             0x0000000e   /* Debug */
  54 #define XGMAC_INT_STATUS        0x0000000f   /* Interrupt and Control */
  55 /* HASH table registers */
  56 #define XGMAC_HASH(n)           ((0x00000300/4) + (n))
  57 #define XGMAC_NUM_HASH          16
  58 /* Operation Mode */
  59 #define XGMAC_OPMODE            (0x00000400/4)
  60 /* Remote Wake-Up Frame Filter */
  61 #define XGMAC_REMOTE_WAKE       (0x00000700/4)
  62 /* PMT Control and Status */
  63 #define XGMAC_PMT               (0x00000704/4)
  64
  65 #define XGMAC_ADDR_HIGH(reg)    (0x00000010+((reg) * 2))
  66 #define XGMAC_ADDR_LOW(reg)     (0x00000011+((reg) * 2))
  67
  68 #define DMA_BUS_MODE            0x000003c0   /* Bus Mode */
  69 #define DMA_XMT_POLL_DEMAND     0x000003c1   /* Transmit Poll Demand */
  70 #define DMA_RCV_POLL_DEMAND     0x000003c2   /* Received Poll Demand */
  71 #define DMA_RCV_BASE_ADDR       0x000003c3   /* Receive List Base */
  72 #define DMA_TX_BASE_ADDR        0x000003c4   /* Transmit List Base */
  73 #define DMA_STATUS              0x000003c5   /* Status Register */
  74 #define DMA_CONTROL             0x000003c6   /* Ctrl (Operational Mode) */
  75 #define DMA_INTR_ENA            0x000003c7   /* Interrupt Enable */
  76 #define DMA_MISSED_FRAME_CTR    0x000003c8   /* Missed Frame Counter */
  77 /* Receive Interrupt Watchdog Timer */
  78 #define DMA_RI_WATCHDOG_TIMER   0x000003c9
  79 #define DMA_AXI_BUS             0x000003ca   /* AXI Bus Mode */
  80 #define DMA_AXI_STATUS          0x000003cb   /* AXI Status */
  81 #define DMA_CUR_TX_DESC_ADDR    0x000003d2   /* Current Host Tx Descriptor */
  82 #define DMA_CUR_RX_DESC_ADDR    0x000003d3   /* Current Host Rx Descriptor */
  83 #define DMA_CUR_TX_BUF_ADDR     0x000003d4   /* Current Host Tx Buffer */
  84 #define DMA_CUR_RX_BUF_ADDR     0x000003d5   /* Current Host Rx Buffer */
  85 #define DMA_HW_FEATURE          0x000003d6   /* Enabled Hardware Features */
  86
  87 /* DMA Status register defines */
  88 #define DMA_STATUS_GMI          0x08000000   /* MMC interrupt */
  89 #define DMA_STATUS_GLI          0x04000000   /* GMAC Line interface int */
  90 #define DMA_STATUS_EB_MASK      0x00380000   /* Error Bits Mask */
  91 #define DMA_STATUS_EB_TX_ABORT  0x00080000   /* Error Bits - TX Abort */
  92 #define DMA_STATUS_EB_RX_ABORT  0x00100000   /* Error Bits - RX Abort */
  93 #define DMA_STATUS_TS_MASK      0x00700000   /* Transmit Process State */
  94 #define DMA_STATUS_TS_SHIFT     20
  95 #define DMA_STATUS_RS_MASK      0x000e0000   /* Receive Process State */
  96 #define DMA_STATUS_RS_SHIFT     17
  97 #define DMA_STATUS_NIS          0x00010000   /* Normal Interrupt Summary */
  98 #define DMA_STATUS_AIS          0x00008000   /* Abnormal Interrupt Summary */
  99 #define DMA_STATUS_ERI          0x00004000   /* Early Receive Interrupt */
 100 #define DMA_STATUS_FBI          0x00002000   /* Fatal Bus Error Interrupt */
 101 #define DMA_STATUS_ETI          0x00000400   /* Early Transmit Interrupt */
 102 #define DMA_STATUS_RWT          0x00000200   /* Receive Watchdog Timeout */
 103 #define DMA_STATUS_RPS          0x00000100   /* Receive Process Stopped */
 104 #define DMA_STATUS_RU           0x00000080   /* Receive Buffer Unavailable */
 105 #define DMA_STATUS_RI           0x00000040   /* Receive Interrupt */
 106 #define DMA_STATUS_UNF          0x00000020   /* Transmit Underflow */
 107 #define DMA_STATUS_OVF          0x00000010   /* Receive Overflow */
 108 #define DMA_STATUS_TJT          0x00000008   /* Transmit Jabber Timeout */
 109 #define DMA_STATUS_TU           0x00000004   /* Transmit Buffer Unavailable */
 110 #define DMA_STATUS_TPS          0x00000002   /* Transmit Process Stopped */
 111 #define DMA_STATUS_TI           0x00000001   /* Transmit Interrupt */
 112
 113 /* DMA Control register defines */
 114 #define DMA_CONTROL_ST          0x00002000   /* Start/Stop Transmission */
 115 #define DMA_CONTROL_SR          0x00000002   /* Start/Stop Receive */
 116 #define DMA_CONTROL_DFF         0x01000000   /* Disable flush of rx frames */
 117
 118 struct desc {
 119     uint32_t ctl_stat;
 120     uint16_t buffer1_size;
 121     uint16_t buffer2_size;
 122     uint32_t buffer1_addr;
 123     uint32_t buffer2_addr;
 124     uint32_t ext_stat;
 125     uint32_t res[3];
 126 };
 127
 128 #define R_MAX 0x400
 129
 130 typedef struct RxTxStats {
 131     uint64_t rx_bytes;
 132     uint64_t tx_bytes;
 133
 134     uint64_t rx;
 135     uint64_t rx_bcast;
 136     uint64_t rx_mcast;
 137 } RxTxStats;
 138
 139 #define TYPE_XGMAC "xgmac"
 140 #define XGMAC(obj) OBJECT_CHECK(XgmacState, (obj), TYPE_XGMAC)
 141
 142 typedef struct XgmacState {
 143     SysBusDevice parent_obj;
 144
 145     MemoryRegion iomem;
 146     qemu_irq sbd_irq;
 147     qemu_irq pmt_irq;
 148     qemu_irq mci_irq;
 149     NICState *nic;
 150     NICConf conf;
 151
 152     struct RxTxStats stats;
 153     uint32_t regs[R_MAX];
 154 } XgmacState;
 155
 156 static const VMStateDescription vmstate_rxtx_stats = {
 157     .name = "xgmac_stats",
 158     .version_id = 1,
 159     .minimum_version_id = 1,
 160     .fields = (VMStateField[]) {
 161         VMSTATE_UINT64(rx_bytes, RxTxStats),
 162         VMSTATE_UINT64(tx_bytes, RxTxStats),
 163         VMSTATE_UINT64(rx, RxTxStats),
 164         VMSTATE_UINT64(rx_bcast, RxTxStats),
 165         VMSTATE_UINT64(rx_mcast, RxTxStats),
 166         VMSTATE_END_OF_LIST()
 167     }
 168 };
 169
 170 static const VMStateDescription vmstate_xgmac = {
 171     .name = "xgmac",
 172     .version_id = 1,
 173     .minimum_version_id = 1,
 174     .fields = (VMStateField[]) {
 175         VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats),
 176         VMSTATE_UINT32_ARRAY(regs, XgmacState, R_MAX),
 177         VMSTATE_END_OF_LIST()
 178     }
 179 };
 180
 181 static void xgmac_read_desc(XgmacState *s, struct desc *d, int rx)
 182 {
 183     uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] :
 184         s->regs[DMA_CUR_TX_DESC_ADDR];
 185     cpu_physical_memory_read(addr, d, sizeof(*d));
 186 }
 187
 188 static void xgmac_write_desc(XgmacState *s, struct desc *d, int rx)
 189 {
 190     int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR;
 191     uint32_t addr = s->regs[reg];
 192
 193     if (!rx && (d->ctl_stat & 0x00200000)) {
 194         s->regs[reg] = s->regs[DMA_TX_BASE_ADDR];
 195     } else if (rx && (d->buffer1_size & 0x8000)) {
 196         s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR];
 197     } else {
 198         s->regs[reg] += sizeof(*d);
 199     }
 200     cpu_physical_memory_write(addr, d, sizeof(*d));
 201 }
 202
 203 static void xgmac_enet_send(XgmacState *s)
 204 {
 205     struct desc bd;
 206     int frame_size;
 207     int len;
 208     uint8_t frame[8192];
 209     uint8_t *ptr;
 210
 211     ptr = frame;
 212     frame_size = 0;
 213     while (1) {
 214         xgmac_read_desc(s, &bd, 0);
 215         if ((bd.ctl_stat & 0x80000000) == 0) {
 216             /* Run out of descriptors to transmit.  */
 217             break;
 218         }
 219         len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff);
 220
 221         if ((bd.buffer1_size & 0xfff) > 2048) {
 222             DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
 223                         "xgmac buffer 1 len on send > 2048 (0x%x)\n",
 224                          __func__, bd.buffer1_size & 0xfff);
 225         }
 226         if ((bd.buffer2_size & 0xfff) != 0) {
 227             DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
 228                         "xgmac buffer 2 len on send != 0 (0x%x)\n",
 229                         __func__, bd.buffer2_size & 0xfff);
 230         }
 231         if (len >= sizeof(frame)) {
 232             DEBUGF_BRK("qemu:%s: buffer overflow %d read into %zu "
 233                         "buffer\n" , __func__, len, sizeof(frame));
 234             DEBUGF_BRK("qemu:%s: buffer1.size=%d; buffer2.size=%d\n",
 235                         __func__, bd.buffer1_size, bd.buffer2_size);
 236         }
 237
 238         cpu_physical_memory_read(bd.buffer1_addr, ptr, len);
 239         ptr += len;
 240         frame_size += len;
 241         if (bd.ctl_stat & 0x20000000) {
 242             /* Last buffer in frame.  */
 243             qemu_send_packet(qemu_get_queue(s->nic), frame, len);
 244             ptr = frame;
 245             frame_size = 0;
 246             s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS;
 247         }
 248         bd.ctl_stat &= ~0x80000000;
 249         /* Write back the modified descriptor.  */
 250         xgmac_write_desc(s, &bd, 0);
 251     }
 252 }
 253
 254 static void enet_update_irq(XgmacState *s)
 255 {
 256     int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA];
 257     qemu_set_irq(s->sbd_irq, !!stat);
 258 }
 259
 260 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
 261 {
 262     XgmacState *s = opaque;
 263     uint64_t r = 0;
 264     addr >>= 2;
 265
 266     switch (addr) {
 267     case XGMAC_VERSION:
 268         r = 0x1012;
 269         break;
 270     default:
 271         if (addr < ARRAY_SIZE(s->regs)) {
 272             r = s->regs[addr];
 273         }
 274         break;
 275     }
 276     return r;
 277 }
 278
 279 static void enet_write(void *opaque, hwaddr addr,
 280                        uint64_t value, unsigned size)
 281 {
 282     XgmacState *s = opaque;
 283
 284     addr >>= 2;
 285     switch (addr) {
 286     case DMA_BUS_MODE:
 287         s->regs[DMA_BUS_MODE] = value & ~0x1;
 288         break;
 289     case DMA_XMT_POLL_DEMAND:
 290         xgmac_enet_send(s);
 291         break;
 292     case DMA_STATUS:
 293         s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value;
 294         break;
 295     case DMA_RCV_BASE_ADDR:
 296         s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value;
 297         break;
 298     case DMA_TX_BASE_ADDR:
 299         s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value;
 300         break;
 301     default:
 302         if (addr < ARRAY_SIZE(s->regs)) {
 303             s->regs[addr] = value;
 304         }
 305         break;
 306     }
 307     enet_update_irq(s);
 308 }
 309
 310 static const MemoryRegionOps enet_mem_ops = {
 311     .read = enet_read,
 312     .write = enet_write,
 313     .endianness = DEVICE_LITTLE_ENDIAN,
 314 };
 315
 316 static int eth_can_rx(XgmacState *s)
 317 {
 318     /* RX enabled?  */
 319     return s->regs[DMA_CONTROL] & DMA_CONTROL_SR;
 320 }
 321
 322 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 323 {
 324     XgmacState *s = qemu_get_nic_opaque(nc);
 325     static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
 326                                               0xff, 0xff, 0xff};
 327     int unicast, broadcast, multicast;
 328     struct desc bd;
 329     ssize_t ret;
 330
 331     if (!eth_can_rx(s)) {
 332         return -1;
 333     }
 334     unicast = ~buf[0] & 0x1;
 335     broadcast = memcmp(buf, sa_bcast, 6) == 0;
 336     multicast = !unicast && !broadcast;
 337     if (size < 12) {
 338         s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
 339         ret = -1;
 340         goto out;
 341     }
 342
 343     xgmac_read_desc(s, &bd, 1);
 344     if ((bd.ctl_stat & 0x80000000) == 0) {
 345         s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS;
 346         ret = size;
 347         goto out;
 348     }
 349
 350     cpu_physical_memory_write(bd.buffer1_addr, buf, size);
 351
 352     /* Add in the 4 bytes for crc (the real hw returns length incl crc) */
 353     size += 4;
 354     bd.ctl_stat = (size << 16) | 0x300;
 355     xgmac_write_desc(s, &bd, 1);
 356
 357     s->stats.rx_bytes += size;
 358     s->stats.rx++;
 359     if (multicast) {
 360         s->stats.rx_mcast++;
 361     } else if (broadcast) {
 362         s->stats.rx_bcast++;
 363     }
 364
 365     s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
 366     ret = size;
 367
 368 out:
 369     enet_update_irq(s);
 370     return ret;
 371 }
 372
 373 static NetClientInfo net_xgmac_enet_info = {
 374     .type = NET_CLIENT_DRIVER_NIC,
 375     .size = sizeof(NICState),
 376     .receive = eth_rx,
 377 };
 378
 379 static int xgmac_enet_init(SysBusDevice *sbd)
 380 {
 381     DeviceState *dev = DEVICE(sbd);
 382     XgmacState *s = XGMAC(dev);
 383
 384     memory_region_init_io(&s->iomem, OBJECT(s), &enet_mem_ops, s,
 385                           "xgmac", 0x1000);
 386     sysbus_init_mmio(sbd, &s->iomem);
 387     sysbus_init_irq(sbd, &s->sbd_irq);
 388     sysbus_init_irq(sbd, &s->pmt_irq);
 389     sysbus_init_irq(sbd, &s->mci_irq);
 390
 391     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 392     s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf,
 393                           object_get_typename(OBJECT(dev)), dev->id, s);
 394     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 395
 396     s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) |
 397                                    s->conf.macaddr.a[4];
 398     s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) |
 399                                  (s->conf.macaddr.a[2] << 16) |
 400                                  (s->conf.macaddr.a[1] << 8) |
 401                                   s->conf.macaddr.a[0];
 402
 403     return 0;
 404 }
 405
 406 static Property xgmac_properties[] = {
 407     DEFINE_NIC_PROPERTIES(XgmacState, conf),
 408     DEFINE_PROP_END_OF_LIST(),
 409 };
 410
 411 static void xgmac_enet_class_init(ObjectClass *klass, void *data)
 412 {
 413     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 414     DeviceClass *dc = DEVICE_CLASS(klass);
 415
 416     sbc->init = xgmac_enet_init;
 417     dc->vmsd = &vmstate_xgmac;
 418     dc->props = xgmac_properties;
 419 }
 420
 421 static const TypeInfo xgmac_enet_info = {
 422     .name          = TYPE_XGMAC,
 423     .parent        = TYPE_SYS_BUS_DEVICE,
 424     .instance_size = sizeof(XgmacState),
 425     .class_init    = xgmac_enet_class_init,
 426 };
 427
 428 static void xgmac_enet_register_types(void)
 429 {
 430     type_register_static(&xgmac_enet_info);
 431 }
 432
 433 type_init(xgmac_enet_register_types)