hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "qemu-common.h"
  31 #include "cpu.h"
  32 #include "hw/hw.h"
  33 #include "trace.h"
  34 #include "qemu/timer.h"
  35 #include "hw/ppc/xics.h"
  36 #include "qemu/error-report.h"
  37 #include "qapi/visitor.h"
  38 #include "monitor/monitor.h"
  39 #include "hw/intc/intc.h"
  40
  41 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  42 {
  43     ICPStateClass *icpc = ICP_GET_CLASS(icp);
  44     int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  45
  46     if (!icp->output) {
  47         return;
  48     }
  49
  50     if (icpc->synchronize_state) {
  51         icpc->synchronize_state(icp);
  52     }
  53
  54     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
  55                    cpu_index, icp->xirr, icp->xirr_owner,
  56                    icp->pending_priority, icp->mfrr);
  57 }
  58
  59 void ics_pic_print_info(ICSState *ics, Monitor *mon)
  60 {
  61     ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
  62     uint32_t i;
  63
  64     monitor_printf(mon, "ICS %4x..%4x %p\n",
  65                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
  66
  67     if (!ics->irqs) {
  68         return;
  69     }
  70
  71     if (icsc->synchronize_state) {
  72         icsc->synchronize_state(ics);
  73     }
  74
  75     for (i = 0; i < ics->nr_irqs; i++) {
  76         ICSIRQState *irq = ics->irqs + i;
  77
  78         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
  79             continue;
  80         }
  81         monitor_printf(mon, "  %4x %s %02x %02x\n",
  82                        ics->offset + i,
  83                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
  84                        "LSI" : "MSI",
  85                        irq->priority, irq->status);
  86     }
  87 }
  88
  89 /*
  90  * ICP: Presentation layer
  91  */
  92
  93 #define XISR_MASK  0x00ffffff
  94 #define CPPR_MASK  0xff000000
  95
  96 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
  97 #define CPPR(icp)   (((icp)->xirr) >> 24)
  98
  99 static void ics_reject(ICSState *ics, uint32_t nr)
 100 {
 101     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 102
 103     if (k->reject) {
 104         k->reject(ics, nr);
 105     }
 106 }
 107
 108 void ics_resend(ICSState *ics)
 109 {
 110     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 111
 112     if (k->resend) {
 113         k->resend(ics);
 114     }
 115 }
 116
 117 static void ics_eoi(ICSState *ics, int nr)
 118 {
 119     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 120
 121     if (k->eoi) {
 122         k->eoi(ics, nr);
 123     }
 124 }
 125
 126 static void icp_check_ipi(ICPState *icp)
 127 {
 128     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 129         return;
 130     }
 131
 132     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 133
 134     if (XISR(icp) && icp->xirr_owner) {
 135         ics_reject(icp->xirr_owner, XISR(icp));
 136     }
 137
 138     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 139     icp->pending_priority = icp->mfrr;
 140     icp->xirr_owner = NULL;
 141     qemu_irq_raise(icp->output);
 142 }
 143
 144 void icp_resend(ICPState *icp)
 145 {
 146     XICSFabric *xi = icp->xics;
 147     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 148
 149     if (icp->mfrr < CPPR(icp)) {
 150         icp_check_ipi(icp);
 151     }
 152
 153     xic->ics_resend(xi);
 154 }
 155
 156 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 157 {
 158     uint8_t old_cppr;
 159     uint32_t old_xisr;
 160
 161     old_cppr = CPPR(icp);
 162     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 163
 164     if (cppr < old_cppr) {
 165         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 166             old_xisr = XISR(icp);
 167             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 168             icp->pending_priority = 0xff;
 169             qemu_irq_lower(icp->output);
 170             if (icp->xirr_owner) {
 171                 ics_reject(icp->xirr_owner, old_xisr);
 172                 icp->xirr_owner = NULL;
 173             }
 174         }
 175     } else {
 176         if (!XISR(icp)) {
 177             icp_resend(icp);
 178         }
 179     }
 180 }
 181
 182 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 183 {
 184     icp->mfrr = mfrr;
 185     if (mfrr < CPPR(icp)) {
 186         icp_check_ipi(icp);
 187     }
 188 }
 189
 190 uint32_t icp_accept(ICPState *icp)
 191 {
 192     uint32_t xirr = icp->xirr;
 193
 194     qemu_irq_lower(icp->output);
 195     icp->xirr = icp->pending_priority << 24;
 196     icp->pending_priority = 0xff;
 197     icp->xirr_owner = NULL;
 198
 199     trace_xics_icp_accept(xirr, icp->xirr);
 200
 201     return xirr;
 202 }
 203
 204 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 205 {
 206     if (mfrr) {
 207         *mfrr = icp->mfrr;
 208     }
 209     return icp->xirr;
 210 }
 211
 212 void icp_eoi(ICPState *icp, uint32_t xirr)
 213 {
 214     XICSFabric *xi = icp->xics;
 215     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 216     ICSState *ics;
 217     uint32_t irq;
 218
 219     /* Send EOI -> ICS */
 220     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 221     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 222     irq = xirr & XISR_MASK;
 223
 224     ics = xic->ics_get(xi, irq);
 225     if (ics) {
 226         ics_eoi(ics, irq);
 227     }
 228     if (!XISR(icp)) {
 229         icp_resend(icp);
 230     }
 231 }
 232
 233 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 234 {
 235     ICPState *icp = xics_icp_get(ics->xics, server);
 236
 237     trace_xics_icp_irq(server, nr, priority);
 238
 239     if ((priority >= CPPR(icp))
 240         || (XISR(icp) && (icp->pending_priority <= priority))) {
 241         ics_reject(ics, nr);
 242     } else {
 243         if (XISR(icp) && icp->xirr_owner) {
 244             ics_reject(icp->xirr_owner, XISR(icp));
 245             icp->xirr_owner = NULL;
 246         }
 247         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 248         icp->xirr_owner = ics;
 249         icp->pending_priority = priority;
 250         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 251         qemu_irq_raise(icp->output);
 252     }
 253 }
 254
 255 static int icp_dispatch_pre_save(void *opaque)
 256 {
 257     ICPState *icp = opaque;
 258     ICPStateClass *info = ICP_GET_CLASS(icp);
 259
 260     if (info->pre_save) {
 261         info->pre_save(icp);
 262     }
 263
 264     return 0;
 265 }
 266
 267 static int icp_dispatch_post_load(void *opaque, int version_id)
 268 {
 269     ICPState *icp = opaque;
 270     ICPStateClass *info = ICP_GET_CLASS(icp);
 271
 272     if (info->post_load) {
 273         return info->post_load(icp, version_id);
 274     }
 275
 276     return 0;
 277 }
 278
 279 static const VMStateDescription vmstate_icp_server = {
 280     .name = "icp/server",
 281     .version_id = 1,
 282     .minimum_version_id = 1,
 283     .pre_save = icp_dispatch_pre_save,
 284     .post_load = icp_dispatch_post_load,
 285     .fields = (VMStateField[]) {
 286         /* Sanity check */
 287         VMSTATE_UINT32(xirr, ICPState),
 288         VMSTATE_UINT8(pending_priority, ICPState),
 289         VMSTATE_UINT8(mfrr, ICPState),
 290         VMSTATE_END_OF_LIST()
 291     },
 292 };
 293
 294 static void icp_reset(DeviceState *dev)
 295 {
 296     ICPState *icp = ICP(dev);
 297
 298     icp->xirr = 0;
 299     icp->pending_priority = 0xff;
 300     icp->mfrr = 0xff;
 301
 302     /* Make all outputs are deasserted */
 303     qemu_set_irq(icp->output, 0);
 304 }
 305
 306 static void icp_reset_handler(void *dev)
 307 {
 308     DeviceClass *dc = DEVICE_GET_CLASS(dev);
 309
 310     dc->reset(dev);
 311 }
 312
 313 static void icp_realize(DeviceState *dev, Error **errp)
 314 {
 315     ICPState *icp = ICP(dev);
 316     PowerPCCPU *cpu;
 317     CPUPPCState *env;
 318     Object *obj;
 319     Error *err = NULL;
 320
 321     obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err);
 322     if (!obj) {
 323         error_propagate_prepend(errp, err,
 324                                 "required link '" ICP_PROP_XICS
 325                                 "' not found: ");
 326         return;
 327     }
 328
 329     icp->xics = XICS_FABRIC(obj);
 330
 331     obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err);
 332     if (!obj) {
 333         error_propagate_prepend(errp, err,
 334                                 "required link '" ICP_PROP_CPU
 335                                 "' not found: ");
 336         return;
 337     }
 338
 339     cpu = POWERPC_CPU(obj);
 340     icp->cs = CPU(obj);
 341
 342     env = &cpu->env;
 343     switch (PPC_INPUT(env)) {
 344     case PPC_FLAGS_INPUT_POWER7:
 345         icp->output = env->irq_inputs[POWER7_INPUT_INT];
 346         break;
 347
 348     case PPC_FLAGS_INPUT_970:
 349         icp->output = env->irq_inputs[PPC970_INPUT_INT];
 350         break;
 351
 352     default:
 353         error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
 354         return;
 355     }
 356
 357     qemu_register_reset(icp_reset_handler, dev);
 358     vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
 359 }
 360
 361 static void icp_unrealize(DeviceState *dev, Error **errp)
 362 {
 363     ICPState *icp = ICP(dev);
 364
 365     vmstate_unregister(NULL, &vmstate_icp_server, icp);
 366     qemu_unregister_reset(icp_reset_handler, dev);
 367 }
 368
 369 static void icp_class_init(ObjectClass *klass, void *data)
 370 {
 371     DeviceClass *dc = DEVICE_CLASS(klass);
 372
 373     dc->realize = icp_realize;
 374     dc->unrealize = icp_unrealize;
 375     dc->reset = icp_reset;
 376 }
 377
 378 static const TypeInfo icp_info = {
 379     .name = TYPE_ICP,
 380     .parent = TYPE_DEVICE,
 381     .instance_size = sizeof(ICPState),
 382     .class_init = icp_class_init,
 383     .class_size = sizeof(ICPStateClass),
 384 };
 385
 386 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
 387 {
 388     Error *local_err = NULL;
 389     Object *obj;
 390
 391     obj = object_new(type);
 392     object_property_add_child(cpu, type, obj, &error_abort);
 393     object_unref(obj);
 394     object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi),
 395                                    &error_abort);
 396     object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort);
 397     object_property_set_bool(obj, true, "realized", &local_err);
 398     if (local_err) {
 399         object_unparent(obj);
 400         error_propagate(errp, local_err);
 401         obj = NULL;
 402     }
 403
 404     return obj;
 405 }
 406
 407 /*
 408  * ICS: Source layer
 409  */
 410 static void ics_simple_resend_msi(ICSState *ics, int srcno)
 411 {
 412     ICSIRQState *irq = ics->irqs + srcno;
 413
 414     /* FIXME: filter by server#? */
 415     if (irq->status & XICS_STATUS_REJECTED) {
 416         irq->status &= ~XICS_STATUS_REJECTED;
 417         if (irq->priority != 0xff) {
 418             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 419         }
 420     }
 421 }
 422
 423 static void ics_simple_resend_lsi(ICSState *ics, int srcno)
 424 {
 425     ICSIRQState *irq = ics->irqs + srcno;
 426
 427     if ((irq->priority != 0xff)
 428         && (irq->status & XICS_STATUS_ASSERTED)
 429         && !(irq->status & XICS_STATUS_SENT)) {
 430         irq->status |= XICS_STATUS_SENT;
 431         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 432     }
 433 }
 434
 435 static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
 436 {
 437     ICSIRQState *irq = ics->irqs + srcno;
 438
 439     trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
 440
 441     if (val) {
 442         if (irq->priority == 0xff) {
 443             irq->status |= XICS_STATUS_MASKED_PENDING;
 444             trace_xics_masked_pending();
 445         } else  {
 446             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 447         }
 448     }
 449 }
 450
 451 static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
 452 {
 453     ICSIRQState *irq = ics->irqs + srcno;
 454
 455     trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
 456     if (val) {
 457         irq->status |= XICS_STATUS_ASSERTED;
 458     } else {
 459         irq->status &= ~XICS_STATUS_ASSERTED;
 460     }
 461     ics_simple_resend_lsi(ics, srcno);
 462 }
 463
 464 void ics_simple_set_irq(void *opaque, int srcno, int val)
 465 {
 466     ICSState *ics = (ICSState *)opaque;
 467
 468     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 469         ics_simple_set_irq_lsi(ics, srcno, val);
 470     } else {
 471         ics_simple_set_irq_msi(ics, srcno, val);
 472     }
 473 }
 474
 475 static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
 476 {
 477     ICSIRQState *irq = ics->irqs + srcno;
 478
 479     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 480         || (irq->priority == 0xff)) {
 481         return;
 482     }
 483
 484     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 485     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 486 }
 487
 488 static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
 489 {
 490     ics_simple_resend_lsi(ics, srcno);
 491 }
 492
 493 void ics_simple_write_xive(ICSState *ics, int srcno, int server,
 494                            uint8_t priority, uint8_t saved_priority)
 495 {
 496     ICSIRQState *irq = ics->irqs + srcno;
 497
 498     irq->server = server;
 499     irq->priority = priority;
 500     irq->saved_priority = saved_priority;
 501
 502     trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
 503                                      priority);
 504
 505     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 506         ics_simple_write_xive_lsi(ics, srcno);
 507     } else {
 508         ics_simple_write_xive_msi(ics, srcno);
 509     }
 510 }
 511
 512 static void ics_simple_reject(ICSState *ics, uint32_t nr)
 513 {
 514     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 515
 516     trace_xics_ics_simple_reject(nr, nr - ics->offset);
 517     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 518         irq->status |= XICS_STATUS_REJECTED;
 519     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 520         irq->status &= ~XICS_STATUS_SENT;
 521     }
 522 }
 523
 524 static void ics_simple_resend(ICSState *ics)
 525 {
 526     int i;
 527
 528     for (i = 0; i < ics->nr_irqs; i++) {
 529         /* FIXME: filter by server#? */
 530         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 531             ics_simple_resend_lsi(ics, i);
 532         } else {
 533             ics_simple_resend_msi(ics, i);
 534         }
 535     }
 536 }
 537
 538 static void ics_simple_eoi(ICSState *ics, uint32_t nr)
 539 {
 540     int srcno = nr - ics->offset;
 541     ICSIRQState *irq = ics->irqs + srcno;
 542
 543     trace_xics_ics_simple_eoi(nr);
 544
 545     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 546         irq->status &= ~XICS_STATUS_SENT;
 547     }
 548 }
 549
 550 static void ics_simple_reset(DeviceState *dev)
 551 {
 552     ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
 553
 554     icsc->parent_reset(dev);
 555 }
 556
 557 static void ics_simple_reset_handler(void *dev)
 558 {
 559     ics_simple_reset(dev);
 560 }
 561
 562 static void ics_simple_realize(DeviceState *dev, Error **errp)
 563 {
 564     ICSState *ics = ICS_SIMPLE(dev);
 565     ICSStateClass *icsc = ICS_BASE_GET_CLASS(ics);
 566     Error *local_err = NULL;
 567
 568     icsc->parent_realize(dev, &local_err);
 569     if (local_err) {
 570         error_propagate(errp, local_err);
 571         return;
 572     }
 573
 574     qemu_register_reset(ics_simple_reset_handler, ics);
 575 }
 576
 577 static void ics_simple_class_init(ObjectClass *klass, void *data)
 578 {
 579     DeviceClass *dc = DEVICE_CLASS(klass);
 580     ICSStateClass *isc = ICS_BASE_CLASS(klass);
 581
 582     device_class_set_parent_realize(dc, ics_simple_realize,
 583                                     &isc->parent_realize);
 584     device_class_set_parent_reset(dc, ics_simple_reset,
 585                                   &isc->parent_reset);
 586
 587     isc->reject = ics_simple_reject;
 588     isc->resend = ics_simple_resend;
 589     isc->eoi = ics_simple_eoi;
 590 }
 591
 592 static const TypeInfo ics_simple_info = {
 593     .name = TYPE_ICS_SIMPLE,
 594     .parent = TYPE_ICS_BASE,
 595     .instance_size = sizeof(ICSState),
 596     .class_init = ics_simple_class_init,
 597     .class_size = sizeof(ICSStateClass),
 598 };
 599
 600 static void ics_base_reset(DeviceState *dev)
 601 {
 602     ICSState *ics = ICS_BASE(dev);
 603     int i;
 604     uint8_t flags[ics->nr_irqs];
 605
 606     for (i = 0; i < ics->nr_irqs; i++) {
 607         flags[i] = ics->irqs[i].flags;
 608     }
 609
 610     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 611
 612     for (i = 0; i < ics->nr_irqs; i++) {
 613         ics->irqs[i].priority = 0xff;
 614         ics->irqs[i].saved_priority = 0xff;
 615         ics->irqs[i].flags = flags[i];
 616     }
 617 }
 618
 619 static void ics_base_realize(DeviceState *dev, Error **errp)
 620 {
 621     ICSState *ics = ICS_BASE(dev);
 622     Object *obj;
 623     Error *err = NULL;
 624
 625     obj = object_property_get_link(OBJECT(dev), ICS_PROP_XICS, &err);
 626     if (!obj) {
 627         error_propagate_prepend(errp, err,
 628                                 "required link '" ICS_PROP_XICS
 629                                 "' not found: ");
 630         return;
 631     }
 632     ics->xics = XICS_FABRIC(obj);
 633
 634     if (!ics->nr_irqs) {
 635         error_setg(errp, "Number of interrupts needs to be greater 0");
 636         return;
 637     }
 638     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 639 }
 640
 641 static void ics_base_instance_init(Object *obj)
 642 {
 643     ICSState *ics = ICS_BASE(obj);
 644
 645     ics->offset = XICS_IRQ_BASE;
 646 }
 647
 648 static int ics_base_dispatch_pre_save(void *opaque)
 649 {
 650     ICSState *ics = opaque;
 651     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
 652
 653     if (info->pre_save) {
 654         info->pre_save(ics);
 655     }
 656
 657     return 0;
 658 }
 659
 660 static int ics_base_dispatch_post_load(void *opaque, int version_id)
 661 {
 662     ICSState *ics = opaque;
 663     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
 664
 665     if (info->post_load) {
 666         return info->post_load(ics, version_id);
 667     }
 668
 669     return 0;
 670 }
 671
 672 static const VMStateDescription vmstate_ics_base_irq = {
 673     .name = "ics/irq",
 674     .version_id = 2,
 675     .minimum_version_id = 1,
 676     .fields = (VMStateField[]) {
 677         VMSTATE_UINT32(server, ICSIRQState),
 678         VMSTATE_UINT8(priority, ICSIRQState),
 679         VMSTATE_UINT8(saved_priority, ICSIRQState),
 680         VMSTATE_UINT8(status, ICSIRQState),
 681         VMSTATE_UINT8(flags, ICSIRQState),
 682         VMSTATE_END_OF_LIST()
 683     },
 684 };
 685
 686 static const VMStateDescription vmstate_ics_base = {
 687     .name = "ics",
 688     .version_id = 1,
 689     .minimum_version_id = 1,
 690     .pre_save = ics_base_dispatch_pre_save,
 691     .post_load = ics_base_dispatch_post_load,
 692     .fields = (VMStateField[]) {
 693         /* Sanity check */
 694         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
 695
 696         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 697                                              vmstate_ics_base_irq,
 698                                              ICSIRQState),
 699         VMSTATE_END_OF_LIST()
 700     },
 701 };
 702
 703 static Property ics_base_properties[] = {
 704     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 705     DEFINE_PROP_END_OF_LIST(),
 706 };
 707
 708 static void ics_base_class_init(ObjectClass *klass, void *data)
 709 {
 710     DeviceClass *dc = DEVICE_CLASS(klass);
 711
 712     dc->realize = ics_base_realize;
 713     dc->props = ics_base_properties;
 714     dc->reset = ics_base_reset;
 715     dc->vmsd = &vmstate_ics_base;
 716 }
 717
 718 static const TypeInfo ics_base_info = {
 719     .name = TYPE_ICS_BASE,
 720     .parent = TYPE_DEVICE,
 721     .abstract = true,
 722     .instance_size = sizeof(ICSState),
 723     .instance_init = ics_base_instance_init,
 724     .class_init = ics_base_class_init,
 725     .class_size = sizeof(ICSStateClass),
 726 };
 727
 728 static const TypeInfo xics_fabric_info = {
 729     .name = TYPE_XICS_FABRIC,
 730     .parent = TYPE_INTERFACE,
 731     .class_size = sizeof(XICSFabricClass),
 732 };
 733
 734 /*
 735  * Exported functions
 736  */
 737 ICPState *xics_icp_get(XICSFabric *xi, int server)
 738 {
 739     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 740
 741     return xic->icp_get(xi, server);
 742 }
 743
 744 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 745 {
 746     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 747
 748     ics->irqs[srcno].flags |=
 749         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 750 }
 751
 752 static void xics_register_types(void)
 753 {
 754     type_register_static(&ics_simple_info);
 755     type_register_static(&ics_base_info);
 756     type_register_static(&icp_info);
 757     type_register_static(&xics_fabric_info);
 758 }
 759
 760 type_init(xics_register_types)