4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>
19 #include "qemu/osdep.h"
20 #include "qemu-common.h"
22 #include "qemu/thread.h"
23 #include "hw/i386/apic_internal.h"
24 #include "hw/i386/apic.h"
25 #include "hw/i386/ioapic.h"
26 #include "hw/pci/msi.h"
27 #include "qemu/host-utils.h"
29 #include "hw/i386/pc.h"
30 #include "hw/i386/apic-msidef.h"
31 #include "qapi/error.h"
34 #define MAX_APIC_WORDS 8
36 #define SYNC_FROM_VAPIC 0x1
37 #define SYNC_TO_VAPIC 0x2
38 #define SYNC_ISR_IRR_TO_VAPIC 0x4
40 static APICCommonState
*local_apics
[MAX_APICS
+ 1];
42 #define TYPE_APIC "apic"
44 OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC)
46 static void apic_set_irq(APICCommonState
*s
, int vector_num
, int trigger_mode
);
47 static void apic_update_irq(APICCommonState
*s
);
48 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
49 uint8_t dest
, uint8_t dest_mode
);
51 /* Find first bit starting from msb */
52 static int apic_fls_bit(uint32_t value
)
54 return 31 - clz32(value
);
57 /* Find first bit starting from lsb */
58 static int apic_ffs_bit(uint32_t value
)
63 static inline void apic_reset_bit(uint32_t *tab
, int index
)
67 mask
= 1 << (index
& 0x1f);
71 /* return -1 if no bit is set */
72 static int get_highest_priority_int(uint32_t *tab
)
75 for (i
= 7; i
>= 0; i
--) {
77 return i
* 32 + apic_fls_bit(tab
[i
]);
83 static void apic_sync_vapic(APICCommonState
*s
, int sync_type
)
85 VAPICState vapic_state
;
90 if (!s
->vapic_paddr
) {
93 if (sync_type
& SYNC_FROM_VAPIC
) {
94 cpu_physical_memory_read(s
->vapic_paddr
, &vapic_state
,
96 s
->tpr
= vapic_state
.tpr
;
98 if (sync_type
& (SYNC_TO_VAPIC
| SYNC_ISR_IRR_TO_VAPIC
)) {
99 start
= offsetof(VAPICState
, isr
);
100 length
= offsetof(VAPICState
, enabled
) - offsetof(VAPICState
, isr
);
102 if (sync_type
& SYNC_TO_VAPIC
) {
103 assert(qemu_cpu_is_self(CPU(s
->cpu
)));
105 vapic_state
.tpr
= s
->tpr
;
106 vapic_state
.enabled
= 1;
108 length
= sizeof(VAPICState
);
111 vector
= get_highest_priority_int(s
->isr
);
115 vapic_state
.isr
= vector
& 0xf0;
117 vapic_state
.zero
= 0;
119 vector
= get_highest_priority_int(s
->irr
);
123 vapic_state
.irr
= vector
& 0xff;
125 address_space_write_rom(&address_space_memory
,
126 s
->vapic_paddr
+ start
,
127 MEMTXATTRS_UNSPECIFIED
,
128 ((void *)&vapic_state
) + start
, length
);
132 static void apic_vapic_base_update(APICCommonState
*s
)
134 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
137 static void apic_local_deliver(APICCommonState
*s
, int vector
)
139 uint32_t lvt
= s
->lvt
[vector
];
142 trace_apic_local_deliver(vector
, (lvt
>> 8) & 7);
144 if (lvt
& APIC_LVT_MASKED
)
147 switch ((lvt
>> 8) & 7) {
149 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_SMI
);
153 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_NMI
);
157 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_HARD
);
161 trigger_mode
= APIC_TRIGGER_EDGE
;
162 if ((vector
== APIC_LVT_LINT0
|| vector
== APIC_LVT_LINT1
) &&
163 (lvt
& APIC_LVT_LEVEL_TRIGGER
))
164 trigger_mode
= APIC_TRIGGER_LEVEL
;
165 apic_set_irq(s
, lvt
& 0xff, trigger_mode
);
169 void apic_deliver_pic_intr(DeviceState
*dev
, int level
)
171 APICCommonState
*s
= APIC(dev
);
174 apic_local_deliver(s
, APIC_LVT_LINT0
);
176 uint32_t lvt
= s
->lvt
[APIC_LVT_LINT0
];
178 switch ((lvt
>> 8) & 7) {
180 if (!(lvt
& APIC_LVT_LEVEL_TRIGGER
))
182 apic_reset_bit(s
->irr
, lvt
& 0xff);
191 static void apic_external_nmi(APICCommonState
*s
)
193 apic_local_deliver(s
, APIC_LVT_LINT1
);
196 #define foreach_apic(apic, deliver_bitmask, code) \
199 for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
200 uint32_t __mask = deliver_bitmask[__i];\
202 for(__j = 0; __j < 32; __j++) {\
203 if (__mask & (1U << __j)) {\
204 apic = local_apics[__i * 32 + __j];\
214 static void apic_bus_deliver(const uint32_t *deliver_bitmask
,
215 uint8_t delivery_mode
, uint8_t vector_num
,
216 uint8_t trigger_mode
)
218 APICCommonState
*apic_iter
;
220 switch (delivery_mode
) {
222 /* XXX: search for focus processor, arbitration */
226 for(i
= 0; i
< MAX_APIC_WORDS
; i
++) {
227 if (deliver_bitmask
[i
]) {
228 d
= i
* 32 + apic_ffs_bit(deliver_bitmask
[i
]);
233 apic_iter
= local_apics
[d
];
235 apic_set_irq(apic_iter
, vector_num
, trigger_mode
);
245 foreach_apic(apic_iter
, deliver_bitmask
,
246 cpu_interrupt(CPU(apic_iter
->cpu
), CPU_INTERRUPT_SMI
)
251 foreach_apic(apic_iter
, deliver_bitmask
,
252 cpu_interrupt(CPU(apic_iter
->cpu
), CPU_INTERRUPT_NMI
)
257 /* normal INIT IPI sent to processors */
258 foreach_apic(apic_iter
, deliver_bitmask
,
259 cpu_interrupt(CPU(apic_iter
->cpu
),
265 /* handled in I/O APIC code */
272 foreach_apic(apic_iter
, deliver_bitmask
,
273 apic_set_irq(apic_iter
, vector_num
, trigger_mode
) );
276 void apic_deliver_irq(uint8_t dest
, uint8_t dest_mode
, uint8_t delivery_mode
,
277 uint8_t vector_num
, uint8_t trigger_mode
)
279 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
281 trace_apic_deliver_irq(dest
, dest_mode
, delivery_mode
, vector_num
,
284 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
285 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, trigger_mode
);
288 static void apic_set_base(APICCommonState
*s
, uint64_t val
)
290 s
->apicbase
= (val
& 0xfffff000) |
291 (s
->apicbase
& (MSR_IA32_APICBASE_BSP
| MSR_IA32_APICBASE_ENABLE
));
292 /* if disabled, cannot be enabled again */
293 if (!(val
& MSR_IA32_APICBASE_ENABLE
)) {
294 s
->apicbase
&= ~MSR_IA32_APICBASE_ENABLE
;
295 cpu_clear_apic_feature(&s
->cpu
->env
);
296 s
->spurious_vec
&= ~APIC_SV_ENABLE
;
300 static void apic_set_tpr(APICCommonState
*s
, uint8_t val
)
302 /* Updates from cr8 are ignored while the VAPIC is active */
303 if (!s
->vapic_paddr
) {
309 int apic_get_highest_priority_irr(DeviceState
*dev
)
317 s
= APIC_COMMON(dev
);
318 return get_highest_priority_int(s
->irr
);
321 static uint8_t apic_get_tpr(APICCommonState
*s
)
323 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
327 int apic_get_ppr(APICCommonState
*s
)
332 isrv
= get_highest_priority_int(s
->isr
);
343 static int apic_get_arb_pri(APICCommonState
*s
)
345 /* XXX: arbitration */
351 * <0 - low prio interrupt,
353 * >0 - interrupt number
355 static int apic_irq_pending(APICCommonState
*s
)
359 if (!(s
->spurious_vec
& APIC_SV_ENABLE
)) {
363 irrv
= get_highest_priority_int(s
->irr
);
367 ppr
= apic_get_ppr(s
);
368 if (ppr
&& (irrv
& 0xf0) <= (ppr
& 0xf0)) {
375 /* signal the CPU if an irq is pending */
376 static void apic_update_irq(APICCommonState
*s
)
379 DeviceState
*dev
= (DeviceState
*)s
;
382 if (!qemu_cpu_is_self(cpu
)) {
383 cpu_interrupt(cpu
, CPU_INTERRUPT_POLL
);
384 } else if (apic_irq_pending(s
) > 0) {
385 cpu_interrupt(cpu
, CPU_INTERRUPT_HARD
);
386 } else if (!apic_accept_pic_intr(dev
) || !pic_get_output(isa_pic
)) {
387 cpu_reset_interrupt(cpu
, CPU_INTERRUPT_HARD
);
391 void apic_poll_irq(DeviceState
*dev
)
393 APICCommonState
*s
= APIC(dev
);
395 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
399 static void apic_set_irq(APICCommonState
*s
, int vector_num
, int trigger_mode
)
401 apic_report_irq_delivered(!apic_get_bit(s
->irr
, vector_num
));
403 apic_set_bit(s
->irr
, vector_num
);
405 apic_set_bit(s
->tmr
, vector_num
);
407 apic_reset_bit(s
->tmr
, vector_num
);
408 if (s
->vapic_paddr
) {
409 apic_sync_vapic(s
, SYNC_ISR_IRR_TO_VAPIC
);
411 * The vcpu thread needs to see the new IRR before we pull its current
412 * TPR value. That way, if we miss a lowering of the TRP, the guest
413 * has the chance to notice the new IRR and poll for IRQs on its own.
416 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
421 static void apic_eoi(APICCommonState
*s
)
424 isrv
= get_highest_priority_int(s
->isr
);
427 apic_reset_bit(s
->isr
, isrv
);
428 if (!(s
->spurious_vec
& APIC_SV_DIRECTED_IO
) && apic_get_bit(s
->tmr
, isrv
)) {
429 ioapic_eoi_broadcast(isrv
);
431 apic_sync_vapic(s
, SYNC_FROM_VAPIC
| SYNC_TO_VAPIC
);
435 static int apic_find_dest(uint8_t dest
)
437 APICCommonState
*apic
= local_apics
[dest
];
440 if (apic
&& apic
->id
== dest
)
441 return dest
; /* shortcut in case apic->id == local_apics[dest]->id */
443 for (i
= 0; i
< MAX_APICS
; i
++) {
444 apic
= local_apics
[i
];
445 if (apic
&& apic
->id
== dest
)
454 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask
,
455 uint8_t dest
, uint8_t dest_mode
)
457 APICCommonState
*apic_iter
;
460 if (dest_mode
== 0) {
462 memset(deliver_bitmask
, 0xff, MAX_APIC_WORDS
* sizeof(uint32_t));
464 int idx
= apic_find_dest(dest
);
465 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
467 apic_set_bit(deliver_bitmask
, idx
);
470 /* XXX: cluster mode */
471 memset(deliver_bitmask
, 0x00, MAX_APIC_WORDS
* sizeof(uint32_t));
472 for(i
= 0; i
< MAX_APICS
; i
++) {
473 apic_iter
= local_apics
[i
];
475 if (apic_iter
->dest_mode
== 0xf) {
476 if (dest
& apic_iter
->log_dest
)
477 apic_set_bit(deliver_bitmask
, i
);
478 } else if (apic_iter
->dest_mode
== 0x0) {
479 if ((dest
& 0xf0) == (apic_iter
->log_dest
& 0xf0) &&
480 (dest
& apic_iter
->log_dest
& 0x0f)) {
481 apic_set_bit(deliver_bitmask
, i
);
491 static void apic_startup(APICCommonState
*s
, int vector_num
)
493 s
->sipi_vector
= vector_num
;
494 cpu_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_SIPI
);
497 void apic_sipi(DeviceState
*dev
)
499 APICCommonState
*s
= APIC(dev
);
501 cpu_reset_interrupt(CPU(s
->cpu
), CPU_INTERRUPT_SIPI
);
503 if (!s
->wait_for_sipi
)
505 cpu_x86_load_seg_cache_sipi(s
->cpu
, s
->sipi_vector
);
506 s
->wait_for_sipi
= 0;
509 static void apic_deliver(DeviceState
*dev
, uint8_t dest
, uint8_t dest_mode
,
510 uint8_t delivery_mode
, uint8_t vector_num
,
511 uint8_t trigger_mode
)
513 APICCommonState
*s
= APIC(dev
);
514 uint32_t deliver_bitmask
[MAX_APIC_WORDS
];
515 int dest_shorthand
= (s
->icr
[0] >> 18) & 3;
516 APICCommonState
*apic_iter
;
518 switch (dest_shorthand
) {
520 apic_get_delivery_bitmask(deliver_bitmask
, dest
, dest_mode
);
523 memset(deliver_bitmask
, 0x00, sizeof(deliver_bitmask
));
524 apic_set_bit(deliver_bitmask
, s
->id
);
527 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
530 memset(deliver_bitmask
, 0xff, sizeof(deliver_bitmask
));
531 apic_reset_bit(deliver_bitmask
, s
->id
);
535 switch (delivery_mode
) {
538 int trig_mode
= (s
->icr
[0] >> 15) & 1;
539 int level
= (s
->icr
[0] >> 14) & 1;
540 if (level
== 0 && trig_mode
== 1) {
541 foreach_apic(apic_iter
, deliver_bitmask
,
542 apic_iter
->arb_id
= apic_iter
->id
);
549 foreach_apic(apic_iter
, deliver_bitmask
,
550 apic_startup(apic_iter
, vector_num
) );
554 apic_bus_deliver(deliver_bitmask
, delivery_mode
, vector_num
, trigger_mode
);
557 static bool apic_check_pic(APICCommonState
*s
)
559 DeviceState
*dev
= (DeviceState
*)s
;
561 if (!apic_accept_pic_intr(dev
) || !pic_get_output(isa_pic
)) {
564 apic_deliver_pic_intr(dev
, 1);
568 int apic_get_interrupt(DeviceState
*dev
)
570 APICCommonState
*s
= APIC(dev
);
573 /* if the APIC is installed or enabled, we let the 8259 handle the
577 if (!(s
->spurious_vec
& APIC_SV_ENABLE
))
580 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
581 intno
= apic_irq_pending(s
);
583 /* if there is an interrupt from the 8259, let the caller handle
584 * that first since ExtINT interrupts ignore the priority.
586 if (intno
== 0 || apic_check_pic(s
)) {
587 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
589 } else if (intno
< 0) {
590 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
591 return s
->spurious_vec
& 0xff;
593 apic_reset_bit(s
->irr
, intno
);
594 apic_set_bit(s
->isr
, intno
);
595 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
602 int apic_accept_pic_intr(DeviceState
*dev
)
604 APICCommonState
*s
= APIC(dev
);
610 lvt0
= s
->lvt
[APIC_LVT_LINT0
];
612 if ((s
->apicbase
& MSR_IA32_APICBASE_ENABLE
) == 0 ||
613 (lvt0
& APIC_LVT_MASKED
) == 0)
619 static uint32_t apic_get_current_count(APICCommonState
*s
)
623 d
= (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - s
->initial_count_load_time
) >>
625 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
627 val
= s
->initial_count
- (d
% ((uint64_t)s
->initial_count
+ 1));
629 if (d
>= s
->initial_count
)
632 val
= s
->initial_count
- d
;
637 static void apic_timer_update(APICCommonState
*s
, int64_t current_time
)
639 if (apic_next_timer(s
, current_time
)) {
640 timer_mod(s
->timer
, s
->next_time
);
646 static void apic_timer(void *opaque
)
648 APICCommonState
*s
= opaque
;
650 apic_local_deliver(s
, APIC_LVT_TIMER
);
651 apic_timer_update(s
, s
->next_time
);
654 static uint64_t apic_mem_read(void *opaque
, hwaddr addr
, unsigned size
)
665 dev
= cpu_get_current_apic();
671 index
= (addr
>> 4) & 0xff;
676 case 0x03: /* version */
677 val
= s
->version
| ((APIC_LVT_NB
- 1) << 16);
680 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
681 if (apic_report_tpr_access
) {
682 cpu_report_tpr_access(&s
->cpu
->env
, TPR_ACCESS_READ
);
687 val
= apic_get_arb_pri(s
);
691 val
= apic_get_ppr(s
);
697 val
= s
->log_dest
<< 24;
700 val
= (s
->dest_mode
<< 28) | 0xfffffff;
703 val
= s
->spurious_vec
;
706 val
= s
->isr
[index
& 7];
709 val
= s
->tmr
[index
& 7];
712 val
= s
->irr
[index
& 7];
719 val
= s
->icr
[index
& 1];
722 val
= s
->lvt
[index
- 0x32];
725 val
= s
->initial_count
;
728 val
= apic_get_current_count(s
);
731 val
= s
->divide_conf
;
734 s
->esr
|= APIC_ESR_ILLEGAL_ADDRESS
;
738 trace_apic_mem_readl(addr
, val
);
742 static void apic_send_msi(MSIMessage
*msi
)
744 uint64_t addr
= msi
->address
;
745 uint32_t data
= msi
->data
;
746 uint8_t dest
= (addr
& MSI_ADDR_DEST_ID_MASK
) >> MSI_ADDR_DEST_ID_SHIFT
;
747 uint8_t vector
= (data
& MSI_DATA_VECTOR_MASK
) >> MSI_DATA_VECTOR_SHIFT
;
748 uint8_t dest_mode
= (addr
>> MSI_ADDR_DEST_MODE_SHIFT
) & 0x1;
749 uint8_t trigger_mode
= (data
>> MSI_DATA_TRIGGER_SHIFT
) & 0x1;
750 uint8_t delivery
= (data
>> MSI_DATA_DELIVERY_MODE_SHIFT
) & 0x7;
751 /* XXX: Ignore redirection hint. */
752 apic_deliver_irq(dest
, dest_mode
, delivery
, vector
, trigger_mode
);
755 static void apic_mem_write(void *opaque
, hwaddr addr
, uint64_t val
,
760 int index
= (addr
>> 4) & 0xff;
766 if (addr
> 0xfff || !index
) {
767 /* MSI and MMIO APIC are at the same memory location,
768 * but actually not on the global bus: MSI is on PCI bus
769 * APIC is connected directly to the CPU.
770 * Mapping them on the global bus happens to work because
771 * MSI registers are reserved in APIC MMIO and vice versa. */
772 MSIMessage msi
= { .address
= addr
, .data
= val
};
777 dev
= cpu_get_current_apic();
783 trace_apic_mem_writel(addr
, val
);
792 if (apic_report_tpr_access
) {
793 cpu_report_tpr_access(&s
->cpu
->env
, TPR_ACCESS_WRITE
);
796 apic_sync_vapic(s
, SYNC_TO_VAPIC
);
806 s
->log_dest
= val
>> 24;
809 s
->dest_mode
= val
>> 28;
812 s
->spurious_vec
= val
& 0x1ff;
822 apic_deliver(dev
, (s
->icr
[1] >> 24) & 0xff, (s
->icr
[0] >> 11) & 1,
823 (s
->icr
[0] >> 8) & 7, (s
->icr
[0] & 0xff),
824 (s
->icr
[0] >> 15) & 1);
831 int n
= index
- 0x32;
833 if (n
== APIC_LVT_TIMER
) {
834 apic_timer_update(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
835 } else if (n
== APIC_LVT_LINT0
&& apic_check_pic(s
)) {
841 s
->initial_count
= val
;
842 s
->initial_count_load_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
843 apic_timer_update(s
, s
->initial_count_load_time
);
850 s
->divide_conf
= val
& 0xb;
851 v
= (s
->divide_conf
& 3) | ((s
->divide_conf
>> 1) & 4);
852 s
->count_shift
= (v
+ 1) & 7;
856 s
->esr
|= APIC_ESR_ILLEGAL_ADDRESS
;
861 static void apic_pre_save(APICCommonState
*s
)
863 apic_sync_vapic(s
, SYNC_FROM_VAPIC
);
866 static void apic_post_load(APICCommonState
*s
)
868 if (s
->timer_expiry
!= -1) {
869 timer_mod(s
->timer
, s
->timer_expiry
);
875 static const MemoryRegionOps apic_io_ops
= {
876 .read
= apic_mem_read
,
877 .write
= apic_mem_write
,
878 .impl
.min_access_size
= 1,
879 .impl
.max_access_size
= 4,
880 .valid
.min_access_size
= 1,
881 .valid
.max_access_size
= 4,
882 .endianness
= DEVICE_NATIVE_ENDIAN
,
885 static void apic_realize(DeviceState
*dev
, Error
**errp
)
887 APICCommonState
*s
= APIC(dev
);
889 if (s
->id
>= MAX_APICS
) {
890 error_setg(errp
, "%s initialization failed. APIC ID %d is invalid",
891 object_get_typename(OBJECT(dev
)), s
->id
);
895 memory_region_init_io(&s
->io_memory
, OBJECT(s
), &apic_io_ops
, s
, "apic-msi",
898 s
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, apic_timer
, s
);
899 local_apics
[s
->id
] = s
;
901 msi_nonbroken
= true;
904 static void apic_unrealize(DeviceState
*dev
, Error
**errp
)
906 APICCommonState
*s
= APIC(dev
);
909 timer_free(s
->timer
);
910 local_apics
[s
->id
] = NULL
;
913 static void apic_class_init(ObjectClass
*klass
, void *data
)
915 APICCommonClass
*k
= APIC_COMMON_CLASS(klass
);
917 k
->realize
= apic_realize
;
918 k
->unrealize
= apic_unrealize
;
919 k
->set_base
= apic_set_base
;
920 k
->set_tpr
= apic_set_tpr
;
921 k
->get_tpr
= apic_get_tpr
;
922 k
->vapic_base_update
= apic_vapic_base_update
;
923 k
->external_nmi
= apic_external_nmi
;
924 k
->pre_save
= apic_pre_save
;
925 k
->post_load
= apic_post_load
;
926 k
->send_msi
= apic_send_msi
;
929 static const TypeInfo apic_info
= {
931 .instance_size
= sizeof(APICCommonState
),
932 .parent
= TYPE_APIC_COMMON
,
933 .class_init
= apic_class_init
,
936 static void apic_register_types(void)
938 type_register_static(&apic_info
);
941 type_init(apic_register_types
)