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target/arm: Postpone interpretation of stage 2 descriptor attribute bits
[qemu/ar7.git] / hw / sd / allwinner-sdhost.c
blob041e45c680472832571d9c2c5f3a0bfee791dcbf
1 /*
2 * Allwinner (sun4i and above) SD Host Controller emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/module.h"
23 #include "qemu/units.h"
24 #include "qapi/error.h"
25 #include "sysemu/blockdev.h"
26 #include "sysemu/dma.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/irq.h"
29 #include "hw/sd/allwinner-sdhost.h"
30 #include "migration/vmstate.h"
31 #include "trace.h"
32 #include "qom/object.h"
33
34 #define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
35 /* This is reusing the SDBus typedef from SD_BUS */
36 DECLARE_INSTANCE_CHECKER(SDBus, AW_SDHOST_BUS,
37 TYPE_AW_SDHOST_BUS)
38
39 /* SD Host register offsets */
40 enum {
41 REG_SD_GCTL = 0x00, /* Global Control */
42 REG_SD_CKCR = 0x04, /* Clock Control */
43 REG_SD_TMOR = 0x08, /* Timeout */
44 REG_SD_BWDR = 0x0C, /* Bus Width */
45 REG_SD_BKSR = 0x10, /* Block Size */
46 REG_SD_BYCR = 0x14, /* Byte Count */
47 REG_SD_CMDR = 0x18, /* Command */
48 REG_SD_CAGR = 0x1C, /* Command Argument */
49 REG_SD_RESP0 = 0x20, /* Response Zero */
50 REG_SD_RESP1 = 0x24, /* Response One */
51 REG_SD_RESP2 = 0x28, /* Response Two */
52 REG_SD_RESP3 = 0x2C, /* Response Three */
53 REG_SD_IMKR = 0x30, /* Interrupt Mask */
54 REG_SD_MISR = 0x34, /* Masked Interrupt Status */
55 REG_SD_RISR = 0x38, /* Raw Interrupt Status */
56 REG_SD_STAR = 0x3C, /* Status */
57 REG_SD_FWLR = 0x40, /* FIFO Water Level */
58 REG_SD_FUNS = 0x44, /* FIFO Function Select */
59 REG_SD_DBGC = 0x50, /* Debug Enable */
60 REG_SD_A12A = 0x58, /* Auto command 12 argument */
61 REG_SD_NTSR = 0x5C, /* SD NewTiming Set */
62 REG_SD_SDBG = 0x60, /* SD newTiming Set Debug */
63 REG_SD_HWRST = 0x78, /* Hardware Reset Register */
64 REG_SD_DMAC = 0x80, /* Internal DMA Controller Control */
65 REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
66 REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
67 REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
68 REG_SD_THLDC = 0x100, /* Card Threshold Control */
69 REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
70 REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
71 REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
72 REG_SD_DATA6_CRC = 0x118, /* CRC Data 6 from card/eMMC */
73 REG_SD_DATA5_CRC = 0x11C, /* CRC Data 5 from card/eMMC */
74 REG_SD_DATA4_CRC = 0x120, /* CRC Data 4 from card/eMMC */
75 REG_SD_DATA3_CRC = 0x124, /* CRC Data 3 from card/eMMC */
76 REG_SD_DATA2_CRC = 0x128, /* CRC Data 2 from card/eMMC */
77 REG_SD_DATA1_CRC = 0x12C, /* CRC Data 1 from card/eMMC */
78 REG_SD_DATA0_CRC = 0x130, /* CRC Data 0 from card/eMMC */
79 REG_SD_CRC_STA = 0x134, /* CRC status from card/eMMC during write */
80 REG_SD_FIFO = 0x200, /* Read/Write FIFO */
81 };
82
83 /* SD Host register flags */
84 enum {
85 SD_GCTL_FIFO_AC_MOD = (1 << 31),
86 SD_GCTL_DDR_MOD_SEL = (1 << 10),
87 SD_GCTL_CD_DBC_ENB = (1 << 8),
88 SD_GCTL_DMA_ENB = (1 << 5),
89 SD_GCTL_INT_ENB = (1 << 4),
90 SD_GCTL_DMA_RST = (1 << 2),
91 SD_GCTL_FIFO_RST = (1 << 1),
92 SD_GCTL_SOFT_RST = (1 << 0),
93 };
94
95 enum {
96 SD_CMDR_LOAD = (1 << 31),
97 SD_CMDR_CLKCHANGE = (1 << 21),
98 SD_CMDR_WRITE = (1 << 10),
99 SD_CMDR_AUTOSTOP = (1 << 12),
100 SD_CMDR_DATA = (1 << 9),
101 SD_CMDR_RESPONSE_LONG = (1 << 7),
102 SD_CMDR_RESPONSE = (1 << 6),
103 SD_CMDR_CMDID_MASK = (0x3f),
104 };
105
106 enum {
107 SD_RISR_CARD_REMOVE = (1 << 31),
108 SD_RISR_CARD_INSERT = (1 << 30),
109 SD_RISR_SDIO_INTR = (1 << 16),
110 SD_RISR_AUTOCMD_DONE = (1 << 14),
111 SD_RISR_DATA_COMPLETE = (1 << 3),
112 SD_RISR_CMD_COMPLETE = (1 << 2),
113 SD_RISR_NO_RESPONSE = (1 << 1),
114 };
115
116 enum {
117 SD_STAR_CARD_PRESENT = (1 << 8),
118 };
119
120 enum {
121 SD_IDST_INT_SUMMARY = (1 << 8),
122 SD_IDST_RECEIVE_IRQ = (1 << 1),
123 SD_IDST_TRANSMIT_IRQ = (1 << 0),
124 SD_IDST_IRQ_MASK = (1 << 1) | (1 << 0) | (1 << 8),
125 SD_IDST_WR_MASK = (0x3ff),
126 };
127
128 /* SD Host register reset values */
129 enum {
130 REG_SD_GCTL_RST = 0x00000300,
131 REG_SD_CKCR_RST = 0x0,
132 REG_SD_TMOR_RST = 0xFFFFFF40,
133 REG_SD_BWDR_RST = 0x0,
134 REG_SD_BKSR_RST = 0x00000200,
135 REG_SD_BYCR_RST = 0x00000200,
136 REG_SD_CMDR_RST = 0x0,
137 REG_SD_CAGR_RST = 0x0,
138 REG_SD_RESP_RST = 0x0,
139 REG_SD_IMKR_RST = 0x0,
140 REG_SD_MISR_RST = 0x0,
141 REG_SD_RISR_RST = 0x0,
142 REG_SD_STAR_RST = 0x00000100,
143 REG_SD_FWLR_RST = 0x000F0000,
144 REG_SD_FUNS_RST = 0x0,
145 REG_SD_DBGC_RST = 0x0,
146 REG_SD_A12A_RST = 0x0000FFFF,
147 REG_SD_NTSR_RST = 0x00000001,
148 REG_SD_SDBG_RST = 0x0,
149 REG_SD_HWRST_RST = 0x00000001,
150 REG_SD_DMAC_RST = 0x0,
151 REG_SD_DLBA_RST = 0x0,
152 REG_SD_IDST_RST = 0x0,
153 REG_SD_IDIE_RST = 0x0,
154 REG_SD_THLDC_RST = 0x0,
155 REG_SD_DSBD_RST = 0x0,
156 REG_SD_RES_CRC_RST = 0x0,
157 REG_SD_DATA_CRC_RST = 0x0,
158 REG_SD_CRC_STA_RST = 0x0,
159 REG_SD_FIFO_RST = 0x0,
160 };
161
162 /* Data transfer descriptor for DMA */
163 typedef struct TransferDescriptor {
164 uint32_t status; /* Status flags */
165 uint32_t size; /* Data buffer size */
166 uint32_t addr; /* Data buffer address */
167 uint32_t next; /* Physical address of next descriptor */
168 } TransferDescriptor;
169
170 /* Data transfer descriptor flags */
171 enum {
172 DESC_STATUS_HOLD = (1 << 31), /* Set when descriptor is in use by DMA */
173 DESC_STATUS_ERROR = (1 << 30), /* Set when DMA transfer error occurred */
174 DESC_STATUS_CHAIN = (1 << 4), /* Indicates chained descriptor. */
175 DESC_STATUS_FIRST = (1 << 3), /* Set on the first descriptor */
176 DESC_STATUS_LAST = (1 << 2), /* Set on the last descriptor */
177 DESC_STATUS_NOIRQ = (1 << 1), /* Skip raising interrupt after transfer */
178 DESC_SIZE_MASK = (0xfffffffc)
179 };
180
181 static void allwinner_sdhost_update_irq(AwSdHostState *s)
182 {
183 uint32_t irq;
184
185 if (s->global_ctl & SD_GCTL_INT_ENB) {
186 irq = s->irq_status & s->irq_mask;
187 } else {
188 irq = 0;
189 }
190
191 trace_allwinner_sdhost_update_irq(irq);
192 qemu_set_irq(s->irq, irq);
193 }
194
195 static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
196 uint32_t bytes)
197 {
198 if (s->transfer_cnt > bytes) {
199 s->transfer_cnt -= bytes;
200 } else {
201 s->transfer_cnt = 0;
202 }
203
204 if (!s->transfer_cnt) {
205 s->irq_status |= SD_RISR_DATA_COMPLETE;
206 }
207 }
208
209 static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
210 {
211 AwSdHostState *s = AW_SDHOST(dev);
212
213 trace_allwinner_sdhost_set_inserted(inserted);
214
215 if (inserted) {
216 s->irq_status |= SD_RISR_CARD_INSERT;
217 s->irq_status &= ~SD_RISR_CARD_REMOVE;
218 s->status |= SD_STAR_CARD_PRESENT;
219 } else {
220 s->irq_status &= ~SD_RISR_CARD_INSERT;
221 s->irq_status |= SD_RISR_CARD_REMOVE;
222 s->status &= ~SD_STAR_CARD_PRESENT;
223 }
224
225 allwinner_sdhost_update_irq(s);
226 }
227
228 static void allwinner_sdhost_send_command(AwSdHostState *s)
229 {
230 SDRequest request;
231 uint8_t resp[16];
232 int rlen;
233
234 /* Auto clear load flag */
235 s->command &= ~SD_CMDR_LOAD;
236
237 /* Clock change does not actually interact with the SD bus */
238 if (!(s->command & SD_CMDR_CLKCHANGE)) {
239
240 /* Prepare request */
241 request.cmd = s->command & SD_CMDR_CMDID_MASK;
242 request.arg = s->command_arg;
243
244 /* Send request to SD bus */
245 rlen = sdbus_do_command(&s->sdbus, &request, resp);
246 if (rlen < 0) {
247 goto error;
248 }
249
250 /* If the command has a response, store it in the response registers */
251 if ((s->command & SD_CMDR_RESPONSE)) {
252 if (rlen == 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
253 s->response[0] = ldl_be_p(&resp[0]);
254 s->response[1] = s->response[2] = s->response[3] = 0;
255
256 } else if (rlen == 16 && (s->command & SD_CMDR_RESPONSE_LONG)) {
257 s->response[0] = ldl_be_p(&resp[12]);
258 s->response[1] = ldl_be_p(&resp[8]);
259 s->response[2] = ldl_be_p(&resp[4]);
260 s->response[3] = ldl_be_p(&resp[0]);
261 } else {
262 goto error;
263 }
264 }
265 }
266
267 /* Set interrupt status bits */
268 s->irq_status |= SD_RISR_CMD_COMPLETE;
269 return;
270
271 error:
272 s->irq_status |= SD_RISR_NO_RESPONSE;
273 }
274
275 static void allwinner_sdhost_auto_stop(AwSdHostState *s)
276 {
277 /*
278 * The stop command (CMD12) ensures the SD bus
279 * returns to the transfer state.
280 */
281 if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt == 0)) {
282 /* First save current command registers */
283 uint32_t saved_cmd = s->command;
284 uint32_t saved_arg = s->command_arg;
285
286 /* Prepare stop command (CMD12) */
287 s->command &= ~SD_CMDR_CMDID_MASK;
288 s->command |= 12; /* CMD12 */
289 s->command_arg = 0;
290
291 /* Put the command on SD bus */
292 allwinner_sdhost_send_command(s);
293
294 /* Restore command values */
295 s->command = saved_cmd;
296 s->command_arg = saved_arg;
297
298 /* Set IRQ status bit for automatic stop done */
299 s->irq_status |= SD_RISR_AUTOCMD_DONE;
300 }
301 }
302
303 static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
304 hwaddr desc_addr,
305 TransferDescriptor *desc,
306 bool is_write, uint32_t max_bytes)
307 {
308 AwSdHostClass *klass = AW_SDHOST_GET_CLASS(s);
309 uint32_t num_done = 0;
310 uint32_t num_bytes = max_bytes;
311 uint8_t buf[1024];
312
313 /* Read descriptor */
314 dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc),
315 MEMTXATTRS_UNSPECIFIED);
316 if (desc->size == 0) {
317 desc->size = klass->max_desc_size;
318 } else if (desc->size > klass->max_desc_size) {
319 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
320 " is out-of-bounds: %" PRIu32 " > %zu",
321 __func__, desc->size, klass->max_desc_size);
322 desc->size = klass->max_desc_size;
323 }
324 if (desc->size < num_bytes) {
325 num_bytes = desc->size;
326 }
327
328 trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
329 is_write, max_bytes);
330
331 while (num_done < num_bytes) {
332 /* Try to completely fill the local buffer */
333 uint32_t buf_bytes = num_bytes - num_done;
334 if (buf_bytes > sizeof(buf)) {
335 buf_bytes = sizeof(buf);
336 }
337
338 /* Write to SD bus */
339 if (is_write) {
340 dma_memory_read(&s->dma_as,
341 (desc->addr & DESC_SIZE_MASK) + num_done, buf,
342 buf_bytes, MEMTXATTRS_UNSPECIFIED);
343 sdbus_write_data(&s->sdbus, buf, buf_bytes);
344
345 /* Read from SD bus */
346 } else {
347 sdbus_read_data(&s->sdbus, buf, buf_bytes);
348 dma_memory_write(&s->dma_as,
349 (desc->addr & DESC_SIZE_MASK) + num_done, buf,
350 buf_bytes, MEMTXATTRS_UNSPECIFIED);
351 }
352 num_done += buf_bytes;
353 }
354
355 /* Clear hold flag and flush descriptor */
356 desc->status &= ~DESC_STATUS_HOLD;
357 dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc),
358 MEMTXATTRS_UNSPECIFIED);
359
360 return num_done;
361 }
362
363 static void allwinner_sdhost_dma(AwSdHostState *s)
364 {
365 TransferDescriptor desc;
366 hwaddr desc_addr = s->desc_base;
367 bool is_write = (s->command & SD_CMDR_WRITE);
368 uint32_t bytes_done = 0;
369
370 /* Check if DMA can be performed */
371 if (s->byte_count == 0 || s->block_size == 0 ||
372 !(s->global_ctl & SD_GCTL_DMA_ENB)) {
373 return;
374 }
375
376 /*
377 * For read operations, data must be available on the SD bus
378 * If not, it is an error and we should not act at all
379 */
380 if (!is_write && !sdbus_data_ready(&s->sdbus)) {
381 return;
382 }
383
384 /* Process the DMA descriptors until all data is copied */
385 while (s->byte_count > 0) {
386 bytes_done = allwinner_sdhost_process_desc(s, desc_addr, &desc,
387 is_write, s->byte_count);
388 allwinner_sdhost_update_transfer_cnt(s, bytes_done);
389
390 if (bytes_done <= s->byte_count) {
391 s->byte_count -= bytes_done;
392 } else {
393 s->byte_count = 0;
394 }
395
396 if (desc.status & DESC_STATUS_LAST) {
397 break;
398 } else {
399 desc_addr = desc.next;
400 }
401 }
402
403 /* Raise IRQ to signal DMA is completed */
404 s->irq_status |= SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
405
406 /* Update DMAC bits */
407 s->dmac_status |= SD_IDST_INT_SUMMARY;
408
409 if (is_write) {
410 s->dmac_status |= SD_IDST_TRANSMIT_IRQ;
411 } else {
412 s->dmac_status |= SD_IDST_RECEIVE_IRQ;
413 }
414 }
415
416 static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
417 unsigned size)
418 {
419 AwSdHostState *s = AW_SDHOST(opaque);
420 uint32_t res = 0;
421
422 switch (offset) {
423 case REG_SD_GCTL: /* Global Control */
424 res = s->global_ctl;
425 break;
426 case REG_SD_CKCR: /* Clock Control */
427 res = s->clock_ctl;
428 break;
429 case REG_SD_TMOR: /* Timeout */
430 res = s->timeout;
431 break;
432 case REG_SD_BWDR: /* Bus Width */
433 res = s->bus_width;
434 break;
435 case REG_SD_BKSR: /* Block Size */
436 res = s->block_size;
437 break;
438 case REG_SD_BYCR: /* Byte Count */
439 res = s->byte_count;
440 break;
441 case REG_SD_CMDR: /* Command */
442 res = s->command;
443 break;
444 case REG_SD_CAGR: /* Command Argument */
445 res = s->command_arg;
446 break;
447 case REG_SD_RESP0: /* Response Zero */
448 res = s->response[0];
449 break;
450 case REG_SD_RESP1: /* Response One */
451 res = s->response[1];
452 break;
453 case REG_SD_RESP2: /* Response Two */
454 res = s->response[2];
455 break;
456 case REG_SD_RESP3: /* Response Three */
457 res = s->response[3];
458 break;
459 case REG_SD_IMKR: /* Interrupt Mask */
460 res = s->irq_mask;
461 break;
462 case REG_SD_MISR: /* Masked Interrupt Status */
463 res = s->irq_status & s->irq_mask;
464 break;
465 case REG_SD_RISR: /* Raw Interrupt Status */
466 res = s->irq_status;
467 break;
468 case REG_SD_STAR: /* Status */
469 res = s->status;
470 break;
471 case REG_SD_FWLR: /* FIFO Water Level */
472 res = s->fifo_wlevel;
473 break;
474 case REG_SD_FUNS: /* FIFO Function Select */
475 res = s->fifo_func_sel;
476 break;
477 case REG_SD_DBGC: /* Debug Enable */
478 res = s->debug_enable;
479 break;
480 case REG_SD_A12A: /* Auto command 12 argument */
481 res = s->auto12_arg;
482 break;
483 case REG_SD_NTSR: /* SD NewTiming Set */
484 res = s->newtiming_set;
485 break;
486 case REG_SD_SDBG: /* SD newTiming Set Debug */
487 res = s->newtiming_debug;
488 break;
489 case REG_SD_HWRST: /* Hardware Reset Register */
490 res = s->hardware_rst;
491 break;
492 case REG_SD_DMAC: /* Internal DMA Controller Control */
493 res = s->dmac;
494 break;
495 case REG_SD_DLBA: /* Descriptor List Base Address */
496 res = s->desc_base;
497 break;
498 case REG_SD_IDST: /* Internal DMA Controller Status */
499 res = s->dmac_status;
500 break;
501 case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
502 res = s->dmac_irq;
503 break;
504 case REG_SD_THLDC: /* Card Threshold Control */
505 res = s->card_threshold;
506 break;
507 case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
508 res = s->startbit_detect;
509 break;
510 case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
511 res = s->response_crc;
512 break;
513 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
514 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
515 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
516 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
517 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
518 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
519 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
520 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
521 res = s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t))];
522 break;
523 case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
524 res = s->status_crc;
525 break;
526 case REG_SD_FIFO: /* Read/Write FIFO */
527 if (sdbus_data_ready(&s->sdbus)) {
528 sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
529 le32_to_cpus(&res);
530 allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
531 allwinner_sdhost_auto_stop(s);
532 allwinner_sdhost_update_irq(s);
533 } else {
534 qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
535 __func__);
536 }
537 break;
538 default:
539 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
540 HWADDR_PRIx"\n", __func__, offset);
541 res = 0;
542 break;
543 }
544
545 trace_allwinner_sdhost_read(offset, res, size);
546 return res;
547 }
548
549 static void allwinner_sdhost_write(void *opaque, hwaddr offset,
550 uint64_t value, unsigned size)
551 {
552 AwSdHostState *s = AW_SDHOST(opaque);
553 uint32_t u32;
554
555 trace_allwinner_sdhost_write(offset, value, size);
556
557 switch (offset) {
558 case REG_SD_GCTL: /* Global Control */
559 s->global_ctl = value;
560 s->global_ctl &= ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
561 SD_GCTL_SOFT_RST);
562 allwinner_sdhost_update_irq(s);
563 break;
564 case REG_SD_CKCR: /* Clock Control */
565 s->clock_ctl = value;
566 break;
567 case REG_SD_TMOR: /* Timeout */
568 s->timeout = value;
569 break;
570 case REG_SD_BWDR: /* Bus Width */
571 s->bus_width = value;
572 break;
573 case REG_SD_BKSR: /* Block Size */
574 s->block_size = value;
575 break;
576 case REG_SD_BYCR: /* Byte Count */
577 s->byte_count = value;
578 s->transfer_cnt = value;
579 break;
580 case REG_SD_CMDR: /* Command */
581 s->command = value;
582 if (value & SD_CMDR_LOAD) {
583 allwinner_sdhost_send_command(s);
584 allwinner_sdhost_dma(s);
585 allwinner_sdhost_auto_stop(s);
586 }
587 allwinner_sdhost_update_irq(s);
588 break;
589 case REG_SD_CAGR: /* Command Argument */
590 s->command_arg = value;
591 break;
592 case REG_SD_RESP0: /* Response Zero */
593 s->response[0] = value;
594 break;
595 case REG_SD_RESP1: /* Response One */
596 s->response[1] = value;
597 break;
598 case REG_SD_RESP2: /* Response Two */
599 s->response[2] = value;
600 break;
601 case REG_SD_RESP3: /* Response Three */
602 s->response[3] = value;
603 break;
604 case REG_SD_IMKR: /* Interrupt Mask */
605 s->irq_mask = value;
606 allwinner_sdhost_update_irq(s);
607 break;
608 case REG_SD_MISR: /* Masked Interrupt Status */
609 case REG_SD_RISR: /* Raw Interrupt Status */
610 s->irq_status &= ~value;
611 allwinner_sdhost_update_irq(s);
612 break;
613 case REG_SD_STAR: /* Status */
614 s->status &= ~value;
615 allwinner_sdhost_update_irq(s);
616 break;
617 case REG_SD_FWLR: /* FIFO Water Level */
618 s->fifo_wlevel = value;
619 break;
620 case REG_SD_FUNS: /* FIFO Function Select */
621 s->fifo_func_sel = value;
622 break;
623 case REG_SD_DBGC: /* Debug Enable */
624 s->debug_enable = value;
625 break;
626 case REG_SD_A12A: /* Auto command 12 argument */
627 s->auto12_arg = value;
628 break;
629 case REG_SD_NTSR: /* SD NewTiming Set */
630 s->newtiming_set = value;
631 break;
632 case REG_SD_SDBG: /* SD newTiming Set Debug */
633 s->newtiming_debug = value;
634 break;
635 case REG_SD_HWRST: /* Hardware Reset Register */
636 s->hardware_rst = value;
637 break;
638 case REG_SD_DMAC: /* Internal DMA Controller Control */
639 s->dmac = value;
640 allwinner_sdhost_update_irq(s);
641 break;
642 case REG_SD_DLBA: /* Descriptor List Base Address */
643 s->desc_base = value;
644 break;
645 case REG_SD_IDST: /* Internal DMA Controller Status */
646 s->dmac_status &= (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK);
647 allwinner_sdhost_update_irq(s);
648 break;
649 case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
650 s->dmac_irq = value;
651 allwinner_sdhost_update_irq(s);
652 break;
653 case REG_SD_THLDC: /* Card Threshold Control */
654 s->card_threshold = value;
655 break;
656 case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
657 s->startbit_detect = value;
658 break;
659 case REG_SD_FIFO: /* Read/Write FIFO */
660 u32 = cpu_to_le32(value);
661 sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
662 allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
663 allwinner_sdhost_auto_stop(s);
664 allwinner_sdhost_update_irq(s);
665 break;
666 case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
667 case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
668 case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
669 case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
670 case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
671 case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
672 case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
673 case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
674 case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
675 case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation */
676 break;
677 default:
678 qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
679 HWADDR_PRIx"\n", __func__, offset);
680 break;
681 }
682 }
683
684 static const MemoryRegionOps allwinner_sdhost_ops = {
685 .read = allwinner_sdhost_read,
686 .write = allwinner_sdhost_write,
687 .endianness = DEVICE_NATIVE_ENDIAN,
688 .valid = {
689 .min_access_size = 4,
690 .max_access_size = 4,
691 },
692 .impl.min_access_size = 4,
693 };
694
695 static const VMStateDescription vmstate_allwinner_sdhost = {
696 .name = "allwinner-sdhost",
697 .version_id = 1,
698 .minimum_version_id = 1,
699 .fields = (VMStateField[]) {
700 VMSTATE_UINT32(global_ctl, AwSdHostState),
701 VMSTATE_UINT32(clock_ctl, AwSdHostState),
702 VMSTATE_UINT32(timeout, AwSdHostState),
703 VMSTATE_UINT32(bus_width, AwSdHostState),
704 VMSTATE_UINT32(block_size, AwSdHostState),
705 VMSTATE_UINT32(byte_count, AwSdHostState),
706 VMSTATE_UINT32(transfer_cnt, AwSdHostState),
707 VMSTATE_UINT32(command, AwSdHostState),
708 VMSTATE_UINT32(command_arg, AwSdHostState),
709 VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
710 VMSTATE_UINT32(irq_mask, AwSdHostState),
711 VMSTATE_UINT32(irq_status, AwSdHostState),
712 VMSTATE_UINT32(status, AwSdHostState),
713 VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
714 VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
715 VMSTATE_UINT32(debug_enable, AwSdHostState),
716 VMSTATE_UINT32(auto12_arg, AwSdHostState),
717 VMSTATE_UINT32(newtiming_set, AwSdHostState),
718 VMSTATE_UINT32(newtiming_debug, AwSdHostState),
719 VMSTATE_UINT32(hardware_rst, AwSdHostState),
720 VMSTATE_UINT32(dmac, AwSdHostState),
721 VMSTATE_UINT32(desc_base, AwSdHostState),
722 VMSTATE_UINT32(dmac_status, AwSdHostState),
723 VMSTATE_UINT32(dmac_irq, AwSdHostState),
724 VMSTATE_UINT32(card_threshold, AwSdHostState),
725 VMSTATE_UINT32(startbit_detect, AwSdHostState),
726 VMSTATE_UINT32(response_crc, AwSdHostState),
727 VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
728 VMSTATE_UINT32(status_crc, AwSdHostState),
729 VMSTATE_END_OF_LIST()
730 }
731 };
732
733 static Property allwinner_sdhost_properties[] = {
734 DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr,
735 TYPE_MEMORY_REGION, MemoryRegion *),
736 DEFINE_PROP_END_OF_LIST(),
737 };
738
739 static void allwinner_sdhost_init(Object *obj)
740 {
741 AwSdHostState *s = AW_SDHOST(obj);
742
743 qbus_init(&s->sdbus, sizeof(s->sdbus),
744 TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
745
746 memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
747 TYPE_AW_SDHOST, 4 * KiB);
748 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
749 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
750 }
751
752 static void allwinner_sdhost_realize(DeviceState *dev, Error **errp)
753 {
754 AwSdHostState *s = AW_SDHOST(dev);
755
756 if (!s->dma_mr) {
757 error_setg(errp, TYPE_AW_SDHOST " 'dma-memory' link not set");
758 return;
759 }
760
761 address_space_init(&s->dma_as, s->dma_mr, "sdhost-dma");
762 }
763
764 static void allwinner_sdhost_reset(DeviceState *dev)
765 {
766 AwSdHostState *s = AW_SDHOST(dev);
767
768 s->global_ctl = REG_SD_GCTL_RST;
769 s->clock_ctl = REG_SD_CKCR_RST;
770 s->timeout = REG_SD_TMOR_RST;
771 s->bus_width = REG_SD_BWDR_RST;
772 s->block_size = REG_SD_BKSR_RST;
773 s->byte_count = REG_SD_BYCR_RST;
774 s->transfer_cnt = 0;
775
776 s->command = REG_SD_CMDR_RST;
777 s->command_arg = REG_SD_CAGR_RST;
778
779 for (int i = 0; i < ARRAY_SIZE(s->response); i++) {
780 s->response[i] = REG_SD_RESP_RST;
781 }
782
783 s->irq_mask = REG_SD_IMKR_RST;
784 s->irq_status = REG_SD_RISR_RST;
785 s->status = REG_SD_STAR_RST;
786
787 s->fifo_wlevel = REG_SD_FWLR_RST;
788 s->fifo_func_sel = REG_SD_FUNS_RST;
789 s->debug_enable = REG_SD_DBGC_RST;
790 s->auto12_arg = REG_SD_A12A_RST;
791 s->newtiming_set = REG_SD_NTSR_RST;
792 s->newtiming_debug = REG_SD_SDBG_RST;
793 s->hardware_rst = REG_SD_HWRST_RST;
794 s->dmac = REG_SD_DMAC_RST;
795 s->desc_base = REG_SD_DLBA_RST;
796 s->dmac_status = REG_SD_IDST_RST;
797 s->dmac_irq = REG_SD_IDIE_RST;
798 s->card_threshold = REG_SD_THLDC_RST;
799 s->startbit_detect = REG_SD_DSBD_RST;
800 s->response_crc = REG_SD_RES_CRC_RST;
801
802 for (int i = 0; i < ARRAY_SIZE(s->data_crc); i++) {
803 s->data_crc[i] = REG_SD_DATA_CRC_RST;
804 }
805
806 s->status_crc = REG_SD_CRC_STA_RST;
807 }
808
809 static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data)
810 {
811 SDBusClass *sbc = SD_BUS_CLASS(klass);
812
813 sbc->set_inserted = allwinner_sdhost_set_inserted;
814 }
815
816 static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
817 {
818 DeviceClass *dc = DEVICE_CLASS(klass);
819
820 dc->reset = allwinner_sdhost_reset;
821 dc->vmsd = &vmstate_allwinner_sdhost;
822 dc->realize = allwinner_sdhost_realize;
823 device_class_set_props(dc, allwinner_sdhost_properties);
824 }
825
826 static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
827 {
828 AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
829 sc->max_desc_size = 8 * KiB;
830 }
831
832 static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
833 {
834 AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
835 sc->max_desc_size = 64 * KiB;
836 }
837
838 static const TypeInfo allwinner_sdhost_info = {
839 .name = TYPE_AW_SDHOST,
840 .parent = TYPE_SYS_BUS_DEVICE,
841 .instance_init = allwinner_sdhost_init,
842 .instance_size = sizeof(AwSdHostState),
843 .class_init = allwinner_sdhost_class_init,
844 .class_size = sizeof(AwSdHostClass),
845 .abstract = true,
846 };
847
848 static const TypeInfo allwinner_sdhost_sun4i_info = {
849 .name = TYPE_AW_SDHOST_SUN4I,
850 .parent = TYPE_AW_SDHOST,
851 .class_init = allwinner_sdhost_sun4i_class_init,
852 };
853
854 static const TypeInfo allwinner_sdhost_sun5i_info = {
855 .name = TYPE_AW_SDHOST_SUN5I,
856 .parent = TYPE_AW_SDHOST,
857 .class_init = allwinner_sdhost_sun5i_class_init,
858 };
859
860 static const TypeInfo allwinner_sdhost_bus_info = {
861 .name = TYPE_AW_SDHOST_BUS,
862 .parent = TYPE_SD_BUS,
863 .instance_size = sizeof(SDBus),
864 .class_init = allwinner_sdhost_bus_class_init,
865 };
866
867 static void allwinner_sdhost_register_types(void)
868 {
869 type_register_static(&allwinner_sdhost_info);
870 type_register_static(&allwinner_sdhost_sun4i_info);
871 type_register_static(&allwinner_sdhost_sun5i_info);
872 type_register_static(&allwinner_sdhost_bus_info);
873 }
874
875 type_init(allwinner_sdhost_register_types)
AR7 emulation for QEMU