target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "qemu-common.h"
  26
  27 #define TARGET_LONG_BITS 64
  28
  29 #define ELF_MACHINE_UNAME "S390X"
  30
  31 #define CPUArchState struct CPUS390XState
  32
  33 #include "exec/cpu-defs.h"
  34 #define TARGET_PAGE_BITS 12
  35
  36 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  37 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  38
  39 #include "exec/cpu-all.h"
  40
  41 #include "fpu/softfloat.h"
  42
  43 #define NB_MMU_MODES 3
  44 #define TARGET_INSN_START_EXTRA_WORDS 1
  45
  46 #define MMU_MODE0_SUFFIX _primary
  47 #define MMU_MODE1_SUFFIX _secondary
  48 #define MMU_MODE2_SUFFIX _home
  49
  50 #define MMU_USER_IDX 0
  51
  52 #define MAX_EXT_QUEUE 16
  53 #define MAX_IO_QUEUE 16
  54 #define MAX_MCHK_QUEUE 16
  55
  56 #define PSW_MCHK_MASK 0x0004000000000000
  57 #define PSW_IO_MASK 0x0200000000000000
  58
  59 typedef struct PSW {
  60     uint64_t mask;
  61     uint64_t addr;
  62 } PSW;
  63
  64 typedef struct ExtQueue {
  65     uint32_t code;
  66     uint32_t param;
  67     uint32_t param64;
  68 } ExtQueue;
  69
  70 typedef struct IOIntQueue {
  71     uint16_t id;
  72     uint16_t nr;
  73     uint32_t parm;
  74     uint32_t word;
  75 } IOIntQueue;
  76
  77 typedef struct MchkQueue {
  78     uint16_t type;
  79 } MchkQueue;
  80
  81 typedef struct CPUS390XState {
  82     uint64_t regs[16];     /* GP registers */
  83     /*
  84      * The floating point registers are part of the vector registers.
  85      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  86      */
  87     CPU_DoubleU vregs[32][2];  /* vector registers */
  88     uint32_t aregs[16];    /* access registers */
  89
  90     uint32_t fpc;          /* floating-point control register */
  91     uint32_t cc_op;
  92
  93     float_status fpu_status; /* passed to softfloat lib */
  94
  95     /* The low part of a 128-bit return, or remainder of a divide.  */
  96     uint64_t retxl;
  97
  98     PSW psw;
  99
 100     uint64_t cc_src;
 101     uint64_t cc_dst;
 102     uint64_t cc_vr;
 103
 104     uint64_t __excp_addr;
 105     uint64_t psa;
 106
 107     uint32_t int_pgm_code;
 108     uint32_t int_pgm_ilen;
 109
 110     uint32_t int_svc_code;
 111     uint32_t int_svc_ilen;
 112
 113     uint64_t per_address;
 114     uint16_t per_perc_atmid;
 115
 116     uint64_t cregs[16]; /* control registers */
 117
 118     ExtQueue ext_queue[MAX_EXT_QUEUE];
 119     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 120     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 121
 122     int pending_int;
 123     int ext_index;
 124     int io_index[8];
 125     int mchk_index;
 126
 127     uint64_t ckc;
 128     uint64_t cputm;
 129     uint32_t todpr;
 130
 131     uint64_t pfault_token;
 132     uint64_t pfault_compare;
 133     uint64_t pfault_select;
 134
 135     uint64_t gbea;
 136     uint64_t pp;
 137
 138     CPU_COMMON
 139
 140     /* reset does memset(0) up to here */
 141
 142     uint32_t cpu_num;
 143     uint32_t machine_type;
 144
 145     uint64_t tod_offset;
 146     uint64_t tod_basetime;
 147     QEMUTimer *tod_timer;
 148
 149     QEMUTimer *cpu_timer;
 150
 151     /*
 152      * The cpu state represents the logical state of a cpu. In contrast to other
 153      * architectures, there is a difference between a halt and a stop on s390.
 154      * If all cpus are either stopped (including check stop) or in the disabled
 155      * wait state, the vm can be shut down.
 156      */
 157 #define CPU_STATE_UNINITIALIZED        0x00
 158 #define CPU_STATE_STOPPED              0x01
 159 #define CPU_STATE_CHECK_STOP           0x02
 160 #define CPU_STATE_OPERATING            0x03
 161 #define CPU_STATE_LOAD                 0x04
 162     uint8_t cpu_state;
 163
 164     /* currently processed sigp order */
 165     uint8_t sigp_order;
 166
 167 } CPUS390XState;
 168
 169 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
 170 {
 171     return &cs->vregs[nr][0];
 172 }
 173
 174 #include "cpu-qom.h"
 175 #include <sysemu/kvm.h>
 176
 177 /* distinguish between 24 bit and 31 bit addressing */
 178 #define HIGH_ORDER_BIT 0x80000000
 179
 180 /* Interrupt Codes */
 181 /* Program Interrupts */
 182 #define PGM_OPERATION                   0x0001
 183 #define PGM_PRIVILEGED                  0x0002
 184 #define PGM_EXECUTE                     0x0003
 185 #define PGM_PROTECTION                  0x0004
 186 #define PGM_ADDRESSING                  0x0005
 187 #define PGM_SPECIFICATION               0x0006
 188 #define PGM_DATA                        0x0007
 189 #define PGM_FIXPT_OVERFLOW              0x0008
 190 #define PGM_FIXPT_DIVIDE                0x0009
 191 #define PGM_DEC_OVERFLOW                0x000a
 192 #define PGM_DEC_DIVIDE                  0x000b
 193 #define PGM_HFP_EXP_OVERFLOW            0x000c
 194 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 195 #define PGM_HFP_SIGNIFICANCE            0x000e
 196 #define PGM_HFP_DIVIDE                  0x000f
 197 #define PGM_SEGMENT_TRANS               0x0010
 198 #define PGM_PAGE_TRANS                  0x0011
 199 #define PGM_TRANS_SPEC                  0x0012
 200 #define PGM_SPECIAL_OP                  0x0013
 201 #define PGM_OPERAND                     0x0015
 202 #define PGM_TRACE_TABLE                 0x0016
 203 #define PGM_SPACE_SWITCH                0x001c
 204 #define PGM_HFP_SQRT                    0x001d
 205 #define PGM_PC_TRANS_SPEC               0x001f
 206 #define PGM_AFX_TRANS                   0x0020
 207 #define PGM_ASX_TRANS                   0x0021
 208 #define PGM_LX_TRANS                    0x0022
 209 #define PGM_EX_TRANS                    0x0023
 210 #define PGM_PRIM_AUTH                   0x0024
 211 #define PGM_SEC_AUTH                    0x0025
 212 #define PGM_ALET_SPEC                   0x0028
 213 #define PGM_ALEN_SPEC                   0x0029
 214 #define PGM_ALE_SEQ                     0x002a
 215 #define PGM_ASTE_VALID                  0x002b
 216 #define PGM_ASTE_SEQ                    0x002c
 217 #define PGM_EXT_AUTH                    0x002d
 218 #define PGM_STACK_FULL                  0x0030
 219 #define PGM_STACK_EMPTY                 0x0031
 220 #define PGM_STACK_SPEC                  0x0032
 221 #define PGM_STACK_TYPE                  0x0033
 222 #define PGM_STACK_OP                    0x0034
 223 #define PGM_ASCE_TYPE                   0x0038
 224 #define PGM_REG_FIRST_TRANS             0x0039
 225 #define PGM_REG_SEC_TRANS               0x003a
 226 #define PGM_REG_THIRD_TRANS             0x003b
 227 #define PGM_MONITOR                     0x0040
 228 #define PGM_PER                         0x0080
 229 #define PGM_CRYPTO                      0x0119
 230
 231 /* External Interrupts */
 232 #define EXT_INTERRUPT_KEY               0x0040
 233 #define EXT_CLOCK_COMP                  0x1004
 234 #define EXT_CPU_TIMER                   0x1005
 235 #define EXT_MALFUNCTION                 0x1200
 236 #define EXT_EMERGENCY                   0x1201
 237 #define EXT_EXTERNAL_CALL               0x1202
 238 #define EXT_ETR                         0x1406
 239 #define EXT_SERVICE                     0x2401
 240 #define EXT_VIRTIO                      0x2603
 241
 242 /* PSW defines */
 243 #undef PSW_MASK_PER
 244 #undef PSW_MASK_DAT
 245 #undef PSW_MASK_IO
 246 #undef PSW_MASK_EXT
 247 #undef PSW_MASK_KEY
 248 #undef PSW_SHIFT_KEY
 249 #undef PSW_MASK_MCHECK
 250 #undef PSW_MASK_WAIT
 251 #undef PSW_MASK_PSTATE
 252 #undef PSW_MASK_ASC
 253 #undef PSW_MASK_CC
 254 #undef PSW_MASK_PM
 255 #undef PSW_MASK_64
 256 #undef PSW_MASK_32
 257 #undef PSW_MASK_ESA_ADDR
 258
 259 #define PSW_MASK_PER            0x4000000000000000ULL
 260 #define PSW_MASK_DAT            0x0400000000000000ULL
 261 #define PSW_MASK_IO             0x0200000000000000ULL
 262 #define PSW_MASK_EXT            0x0100000000000000ULL
 263 #define PSW_MASK_KEY            0x00F0000000000000ULL
 264 #define PSW_SHIFT_KEY           56
 265 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 266 #define PSW_MASK_WAIT           0x0002000000000000ULL
 267 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 268 #define PSW_MASK_ASC            0x0000C00000000000ULL
 269 #define PSW_MASK_CC             0x0000300000000000ULL
 270 #define PSW_MASK_PM             0x00000F0000000000ULL
 271 #define PSW_MASK_64             0x0000000100000000ULL
 272 #define PSW_MASK_32             0x0000000080000000ULL
 273 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 274
 275 #undef PSW_ASC_PRIMARY
 276 #undef PSW_ASC_ACCREG
 277 #undef PSW_ASC_SECONDARY
 278 #undef PSW_ASC_HOME
 279
 280 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 281 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 282 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 283 #define PSW_ASC_HOME            0x0000C00000000000ULL
 284
 285 /* tb flags */
 286
 287 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 288 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 289 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 290 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 291 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 292 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 293 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 294 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 295 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 296 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 297 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 298 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 299 #define FLAG_MASK_32            0x00001000
 300
 301 /* Control register 0 bits */
 302 #define CR0_LOWPROT             0x0000000010000000ULL
 303 #define CR0_EDAT                0x0000000000800000ULL
 304
 305 /* MMU */
 306 #define MMU_PRIMARY_IDX         0
 307 #define MMU_SECONDARY_IDX       1
 308 #define MMU_HOME_IDX            2
 309
 310 static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
 311 {
 312     switch (env->psw.mask & PSW_MASK_ASC) {
 313     case PSW_ASC_PRIMARY:
 314         return MMU_PRIMARY_IDX;
 315     case PSW_ASC_SECONDARY:
 316         return MMU_SECONDARY_IDX;
 317     case PSW_ASC_HOME:
 318         return MMU_HOME_IDX;
 319     case PSW_ASC_ACCREG:
 320         /* Fallthrough: access register mode is not yet supported */
 321     default:
 322         abort();
 323     }
 324 }
 325
 326 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
 327 {
 328     switch (mmu_idx) {
 329     case MMU_PRIMARY_IDX:
 330         return PSW_ASC_PRIMARY;
 331     case MMU_SECONDARY_IDX:
 332         return PSW_ASC_SECONDARY;
 333     case MMU_HOME_IDX:
 334         return PSW_ASC_HOME;
 335     default:
 336         abort();
 337     }
 338 }
 339
 340 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 341                                         target_ulong *cs_base, int *flags)
 342 {
 343     *pc = env->psw.addr;
 344     *cs_base = 0;
 345     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 346              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 347 }
 348
 349 /* While the PoO talks about ILC (a number between 1-3) what is actually
 350    stored in LowCore is shifted left one bit (an even between 2-6).  As
 351    this is the actual length of the insn and therefore more useful, that
 352    is what we want to pass around and manipulate.  To make sure that we
 353    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 354 static inline int get_ilen(uint8_t opc)
 355 {
 356     switch (opc >> 6) {
 357     case 0:
 358         return 2;
 359     case 1:
 360     case 2:
 361         return 4;
 362     default:
 363         return 6;
 364     }
 365 }
 366
 367 /* PER bits from control register 9 */
 368 #define PER_CR9_EVENT_BRANCH           0x80000000
 369 #define PER_CR9_EVENT_IFETCH           0x40000000
 370 #define PER_CR9_EVENT_STORE            0x20000000
 371 #define PER_CR9_EVENT_STORE_REAL       0x08000000
 372 #define PER_CR9_EVENT_NULLIFICATION    0x01000000
 373 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
 374 #define PER_CR9_CONTROL_ALTERATION     0x00200000
 375
 376 /* PER bits from the PER CODE/ATMID/AI in lowcore */
 377 #define PER_CODE_EVENT_BRANCH          0x8000
 378 #define PER_CODE_EVENT_IFETCH          0x4000
 379 #define PER_CODE_EVENT_STORE           0x2000
 380 #define PER_CODE_EVENT_STORE_REAL      0x0800
 381 #define PER_CODE_EVENT_NULLIFICATION   0x0100
 382
 383 /* Compute the ATMID field that is stored in the per_perc_atmid lowcore
 384    entry when a PER exception is triggered.  */
 385 static inline uint8_t get_per_atmid(CPUS390XState *env)
 386 {
 387     return ((env->psw.mask & PSW_MASK_64) ?      (1 << 7) : 0) |
 388            (                                     (1 << 6)    ) |
 389            ((env->psw.mask & PSW_MASK_32) ?      (1 << 5) : 0) |
 390            ((env->psw.mask & PSW_MASK_DAT)?      (1 << 4) : 0) |
 391            ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
 392            ((env->psw.mask & PSW_ASC_ACCREG)?    (1 << 2) : 0);
 393 }
 394
 395 /* Check if an address is within the PER starting address and the PER
 396    ending address.  The address range might loop.  */
 397 static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
 398 {
 399     if (env->cregs[10] <= env->cregs[11]) {
 400         return env->cregs[10] <= addr && addr <= env->cregs[11];
 401     } else {
 402         return env->cregs[10] <= addr || addr <= env->cregs[11];
 403     }
 404 }
 405
 406 #ifndef CONFIG_USER_ONLY
 407 /* In several cases of runtime exceptions, we havn't recorded the true
 408    instruction length.  Use these codes when raising exceptions in order
 409    to re-compute the length by examining the insn in memory.  */
 410 #define ILEN_LATER       0x20
 411 #define ILEN_LATER_INC   0x21
 412 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
 413 #endif
 414
 415 S390CPU *cpu_s390x_init(const char *cpu_model);
 416 void s390x_translate_init(void);
 417 int cpu_s390x_exec(CPUState *cpu);
 418
 419 /* you can call this signal handler from your SIGBUS and SIGSEGV
 420    signal handlers to inform the virtual CPU of exceptions. non zero
 421    is returned if the signal was handled by the virtual CPU.  */
 422 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 423                            void *puc);
 424 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 425                               int mmu_idx);
 426
 427 #include "ioinst.h"
 428
 429
 430 #ifndef CONFIG_USER_ONLY
 431 void do_restart_interrupt(CPUS390XState *env);
 432
 433 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
 434                                        uint8_t *ar)
 435 {
 436     hwaddr addr = 0;
 437     uint8_t reg;
 438
 439     reg = ipb >> 28;
 440     if (reg > 0) {
 441         addr = env->regs[reg];
 442     }
 443     addr += (ipb >> 16) & 0xfff;
 444     if (ar) {
 445         *ar = reg;
 446     }
 447
 448     return addr;
 449 }
 450
 451 /* Base/displacement are at the same locations. */
 452 #define decode_basedisp_rs decode_basedisp_s
 453
 454 /* helper functions for run_on_cpu() */
 455 static inline void s390_do_cpu_reset(void *arg)
 456 {
 457     CPUState *cs = arg;
 458     S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
 459
 460     scc->cpu_reset(cs);
 461 }
 462 static inline void s390_do_cpu_full_reset(void *arg)
 463 {
 464     CPUState *cs = arg;
 465
 466     cpu_reset(cs);
 467 }
 468
 469 void s390x_tod_timer(void *opaque);
 470 void s390x_cpu_timer(void *opaque);
 471
 472 int s390_virtio_hypercall(CPUS390XState *env);
 473
 474 #ifdef CONFIG_KVM
 475 void kvm_s390_service_interrupt(uint32_t parm);
 476 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 477 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 478 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 479 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
 480 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
 481                     int len, bool is_write);
 482 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
 483 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
 484 #else
 485 static inline void kvm_s390_service_interrupt(uint32_t parm)
 486 {
 487 }
 488 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 489 {
 490     return -ENOSYS;
 491 }
 492 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 493 {
 494     return -ENOSYS;
 495 }
 496 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
 497                                   void *hostbuf, int len, bool is_write)
 498 {
 499     return -ENOSYS;
 500 }
 501 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
 502                                              uint64_t te_code)
 503 {
 504 }
 505 #endif
 506
 507 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 508 {
 509     if (kvm_enabled()) {
 510         return kvm_s390_get_clock(tod_high, tod_low);
 511     }
 512     /* Fixme TCG */
 513     *tod_high = 0;
 514     *tod_low = 0;
 515     return 0;
 516 }
 517
 518 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 519 {
 520     if (kvm_enabled()) {
 521         return kvm_s390_set_clock(tod_high, tod_low);
 522     }
 523     /* Fixme TCG */
 524     return 0;
 525 }
 526
 527 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 528 unsigned int s390_cpu_halt(S390CPU *cpu);
 529 void s390_cpu_unhalt(S390CPU *cpu);
 530 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 531 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
 532 {
 533     return cpu->env.cpu_state;
 534 }
 535
 536 void gtod_save(QEMUFile *f, void *opaque);
 537 int gtod_load(QEMUFile *f, void *opaque, int version_id);
 538
 539 /* service interrupts are floating therefore we must not pass an cpustate */
 540 void s390_sclp_extint(uint32_t parm);
 541
 542 #else
 543 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
 544 {
 545     return 0;
 546 }
 547
 548 static inline void s390_cpu_unhalt(S390CPU *cpu)
 549 {
 550 }
 551
 552 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 553 {
 554     return 0;
 555 }
 556 #endif
 557 void cpu_lock(void);
 558 void cpu_unlock(void);
 559
 560 typedef struct SubchDev SubchDev;
 561
 562 #ifndef CONFIG_USER_ONLY
 563 extern void subsystem_reset(void);
 564 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 565                          uint16_t schid);
 566 bool css_subch_visible(SubchDev *sch);
 567 void css_conditional_io_interrupt(SubchDev *sch);
 568 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 569 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 570 int css_do_msch(SubchDev *sch, const SCHIB *schib);
 571 int css_do_xsch(SubchDev *sch);
 572 int css_do_csch(SubchDev *sch);
 573 int css_do_hsch(SubchDev *sch);
 574 int css_do_ssch(SubchDev *sch, ORB *orb);
 575 int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
 576 void css_do_tsch_update_subch(SubchDev *sch);
 577 int css_do_stcrw(CRW *crw);
 578 void css_undo_stcrw(CRW *crw);
 579 int css_do_tpi(IOIntCode *int_code, int lowcore);
 580 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 581                          int rfmt, void *buf);
 582 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 583 int css_enable_mcsse(void);
 584 int css_enable_mss(void);
 585 int css_do_rsch(SubchDev *sch);
 586 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 587 bool css_present(uint8_t cssid);
 588 #endif
 589
 590 #define cpu_init(model) CPU(cpu_s390x_init(model))
 591 #define cpu_exec cpu_s390x_exec
 592 #define cpu_signal_handler cpu_s390x_signal_handler
 593
 594 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 595 #define cpu_list s390_cpu_list
 596
 597 #include "exec/exec-all.h"
 598
 599 #define EXCP_EXT 1 /* external interrupt */
 600 #define EXCP_SVC 2 /* supervisor call (syscall) */
 601 #define EXCP_PGM 3 /* program interruption */
 602 #define EXCP_IO  7 /* I/O interrupt */
 603 #define EXCP_MCHK 8 /* machine check */
 604
 605 #define INTERRUPT_EXT        (1 << 0)
 606 #define INTERRUPT_TOD        (1 << 1)
 607 #define INTERRUPT_CPUTIMER   (1 << 2)
 608 #define INTERRUPT_IO         (1 << 3)
 609 #define INTERRUPT_MCHK       (1 << 4)
 610
 611 /* Program Status Word.  */
 612 #define S390_PSWM_REGNUM 0
 613 #define S390_PSWA_REGNUM 1
 614 /* General Purpose Registers.  */
 615 #define S390_R0_REGNUM 2
 616 #define S390_R1_REGNUM 3
 617 #define S390_R2_REGNUM 4
 618 #define S390_R3_REGNUM 5
 619 #define S390_R4_REGNUM 6
 620 #define S390_R5_REGNUM 7
 621 #define S390_R6_REGNUM 8
 622 #define S390_R7_REGNUM 9
 623 #define S390_R8_REGNUM 10
 624 #define S390_R9_REGNUM 11
 625 #define S390_R10_REGNUM 12
 626 #define S390_R11_REGNUM 13
 627 #define S390_R12_REGNUM 14
 628 #define S390_R13_REGNUM 15
 629 #define S390_R14_REGNUM 16
 630 #define S390_R15_REGNUM 17
 631 /* Total Core Registers. */
 632 #define S390_NUM_CORE_REGS 18
 633
 634 /* CC optimization */
 635
 636 enum cc_op {
 637     CC_OP_CONST0 = 0,           /* CC is 0 */
 638     CC_OP_CONST1,               /* CC is 1 */
 639     CC_OP_CONST2,               /* CC is 2 */
 640     CC_OP_CONST3,               /* CC is 3 */
 641
 642     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 643     CC_OP_STATIC,               /* CC value is env->cc_op */
 644
 645     CC_OP_NZ,                   /* env->cc_dst != 0 */
 646     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 647     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 648     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 649     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 650     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 651     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 652
 653     CC_OP_ADD_64,               /* overflow on add (64bit) */
 654     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 655     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 656     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 657     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 658     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 659     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 660     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 661
 662     CC_OP_ADD_32,               /* overflow on add (32bit) */
 663     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 664     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 665     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 666     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 667     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 668     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 669     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 670
 671     CC_OP_COMP_32,              /* complement */
 672     CC_OP_COMP_64,              /* complement */
 673
 674     CC_OP_TM_32,                /* test under mask (32bit) */
 675     CC_OP_TM_64,                /* test under mask (64bit) */
 676
 677     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 678     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 679     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 680
 681     CC_OP_ICM,                  /* insert characters under mask */
 682     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 683     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 684     CC_OP_FLOGR,                /* find leftmost one */
 685     CC_OP_MAX
 686 };
 687
 688 static const char *cc_names[] = {
 689     [CC_OP_CONST0]    = "CC_OP_CONST0",
 690     [CC_OP_CONST1]    = "CC_OP_CONST1",
 691     [CC_OP_CONST2]    = "CC_OP_CONST2",
 692     [CC_OP_CONST3]    = "CC_OP_CONST3",
 693     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 694     [CC_OP_STATIC]    = "CC_OP_STATIC",
 695     [CC_OP_NZ]        = "CC_OP_NZ",
 696     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 697     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 698     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 699     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 700     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 701     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 702     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 703     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 704     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 705     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 706     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 707     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 708     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 709     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 710     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 711     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 712     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 713     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 714     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 715     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 716     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 717     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 718     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 719     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 720     [CC_OP_TM_32]     = "CC_OP_TM_32",
 721     [CC_OP_TM_64]     = "CC_OP_TM_64",
 722     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 723     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 724     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 725     [CC_OP_ICM]       = "CC_OP_ICM",
 726     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 727     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 728     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 729 };
 730
 731 static inline const char *cc_name(int cc_op)
 732 {
 733     return cc_names[cc_op];
 734 }
 735
 736 static inline void setcc(S390CPU *cpu, uint64_t cc)
 737 {
 738     CPUS390XState *env = &cpu->env;
 739
 740     env->psw.mask &= ~(3ull << 44);
 741     env->psw.mask |= (cc & 3) << 44;
 742     env->cc_op = cc;
 743 }
 744
 745 typedef struct LowCore
 746 {
 747     /* prefix area: defined by architecture */
 748     uint32_t        ccw1[2];                  /* 0x000 */
 749     uint32_t        ccw2[4];                  /* 0x008 */
 750     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 751     uint32_t        ext_params;               /* 0x080 */
 752     uint16_t        cpu_addr;                 /* 0x084 */
 753     uint16_t        ext_int_code;             /* 0x086 */
 754     uint16_t        svc_ilen;                 /* 0x088 */
 755     uint16_t        svc_code;                 /* 0x08a */
 756     uint16_t        pgm_ilen;                 /* 0x08c */
 757     uint16_t        pgm_code;                 /* 0x08e */
 758     uint32_t        data_exc_code;            /* 0x090 */
 759     uint16_t        mon_class_num;            /* 0x094 */
 760     uint16_t        per_perc_atmid;           /* 0x096 */
 761     uint64_t        per_address;              /* 0x098 */
 762     uint8_t         exc_access_id;            /* 0x0a0 */
 763     uint8_t         per_access_id;            /* 0x0a1 */
 764     uint8_t         op_access_id;             /* 0x0a2 */
 765     uint8_t         ar_access_id;             /* 0x0a3 */
 766     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 767     uint64_t        trans_exc_code;           /* 0x0a8 */
 768     uint64_t        monitor_code;             /* 0x0b0 */
 769     uint16_t        subchannel_id;            /* 0x0b8 */
 770     uint16_t        subchannel_nr;            /* 0x0ba */
 771     uint32_t        io_int_parm;              /* 0x0bc */
 772     uint32_t        io_int_word;              /* 0x0c0 */
 773     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 774     uint32_t        stfl_fac_list;            /* 0x0c8 */
 775     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 776     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 777     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 778     uint32_t        external_damage_code;     /* 0x0f4 */
 779     uint64_t        failing_storage_address;  /* 0x0f8 */
 780     uint8_t         pad6[0x110-0x100];        /* 0x100 */
 781     uint64_t        per_breaking_event_addr;  /* 0x110 */
 782     uint8_t         pad7[0x120-0x118];        /* 0x118 */
 783     PSW             restart_old_psw;          /* 0x120 */
 784     PSW             external_old_psw;         /* 0x130 */
 785     PSW             svc_old_psw;              /* 0x140 */
 786     PSW             program_old_psw;          /* 0x150 */
 787     PSW             mcck_old_psw;             /* 0x160 */
 788     PSW             io_old_psw;               /* 0x170 */
 789     uint8_t         pad8[0x1a0-0x180];        /* 0x180 */
 790     PSW             restart_new_psw;          /* 0x1a0 */
 791     PSW             external_new_psw;         /* 0x1b0 */
 792     PSW             svc_new_psw;              /* 0x1c0 */
 793     PSW             program_new_psw;          /* 0x1d0 */
 794     PSW             mcck_new_psw;             /* 0x1e0 */
 795     PSW             io_new_psw;               /* 0x1f0 */
 796     PSW             return_psw;               /* 0x200 */
 797     uint8_t         irb[64];                  /* 0x210 */
 798     uint64_t        sync_enter_timer;         /* 0x250 */
 799     uint64_t        async_enter_timer;        /* 0x258 */
 800     uint64_t        exit_timer;               /* 0x260 */
 801     uint64_t        last_update_timer;        /* 0x268 */
 802     uint64_t        user_timer;               /* 0x270 */
 803     uint64_t        system_timer;             /* 0x278 */
 804     uint64_t        last_update_clock;        /* 0x280 */
 805     uint64_t        steal_clock;              /* 0x288 */
 806     PSW             return_mcck_psw;          /* 0x290 */
 807     uint8_t         pad9[0xc00-0x2a0];        /* 0x2a0 */
 808     /* System info area */
 809     uint64_t        save_area[16];            /* 0xc00 */
 810     uint8_t         pad10[0xd40-0xc80];       /* 0xc80 */
 811     uint64_t        kernel_stack;             /* 0xd40 */
 812     uint64_t        thread_info;              /* 0xd48 */
 813     uint64_t        async_stack;              /* 0xd50 */
 814     uint64_t        kernel_asce;              /* 0xd58 */
 815     uint64_t        user_asce;                /* 0xd60 */
 816     uint64_t        panic_stack;              /* 0xd68 */
 817     uint64_t        user_exec_asce;           /* 0xd70 */
 818     uint8_t         pad11[0xdc0-0xd78];       /* 0xd78 */
 819
 820     /* SMP info area: defined by DJB */
 821     uint64_t        clock_comparator;         /* 0xdc0 */
 822     uint64_t        ext_call_fast;            /* 0xdc8 */
 823     uint64_t        percpu_offset;            /* 0xdd0 */
 824     uint64_t        current_task;             /* 0xdd8 */
 825     uint32_t        softirq_pending;          /* 0xde0 */
 826     uint32_t        pad_0x0de4;               /* 0xde4 */
 827     uint64_t        int_clock;                /* 0xde8 */
 828     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 829
 830     /* 0xe00 is used as indicator for dump tools */
 831     /* whether the kernel died with panic() or not */
 832     uint32_t        panic_magic;              /* 0xe00 */
 833
 834     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 835
 836     /* 64 bit extparam used for pfault, diag 250 etc  */
 837     uint64_t        ext_params2;               /* 0x11B8 */
 838
 839     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 840
 841     /* System info area */
 842
 843     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 844     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 845     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 846     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 847     uint32_t        prefixreg_save_area;       /* 0x1318 */
 848     uint32_t        fpt_creg_save_area;        /* 0x131c */
 849     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 850     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 851     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 852     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 853     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 854     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 855     uint64_t        cregs_save_area[16];       /* 0x1380 */
 856
 857     /* align to the top of the prefix area */
 858
 859     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 860 } QEMU_PACKED LowCore;
 861
 862 /* STSI */
 863 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 864 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 865 #define STSI_LEVEL_1            0x0000000010000000ULL
 866 #define STSI_LEVEL_2            0x0000000020000000ULL
 867 #define STSI_LEVEL_3            0x0000000030000000ULL
 868 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 869 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 870 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 871 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 872
 873 /* Basic Machine Configuration */
 874 struct sysib_111 {
 875     uint32_t res1[8];
 876     uint8_t  manuf[16];
 877     uint8_t  type[4];
 878     uint8_t  res2[12];
 879     uint8_t  model[16];
 880     uint8_t  sequence[16];
 881     uint8_t  plant[4];
 882     uint8_t  res3[156];
 883 };
 884
 885 /* Basic Machine CPU */
 886 struct sysib_121 {
 887     uint32_t res1[80];
 888     uint8_t  sequence[16];
 889     uint8_t  plant[4];
 890     uint8_t  res2[2];
 891     uint16_t cpu_addr;
 892     uint8_t  res3[152];
 893 };
 894
 895 /* Basic Machine CPUs */
 896 struct sysib_122 {
 897     uint8_t res1[32];
 898     uint32_t capability;
 899     uint16_t total_cpus;
 900     uint16_t active_cpus;
 901     uint16_t standby_cpus;
 902     uint16_t reserved_cpus;
 903     uint16_t adjustments[2026];
 904 };
 905
 906 /* LPAR CPU */
 907 struct sysib_221 {
 908     uint32_t res1[80];
 909     uint8_t  sequence[16];
 910     uint8_t  plant[4];
 911     uint16_t cpu_id;
 912     uint16_t cpu_addr;
 913     uint8_t  res3[152];
 914 };
 915
 916 /* LPAR CPUs */
 917 struct sysib_222 {
 918     uint32_t res1[32];
 919     uint16_t lpar_num;
 920     uint8_t  res2;
 921     uint8_t  lcpuc;
 922     uint16_t total_cpus;
 923     uint16_t conf_cpus;
 924     uint16_t standby_cpus;
 925     uint16_t reserved_cpus;
 926     uint8_t  name[8];
 927     uint32_t caf;
 928     uint8_t  res3[16];
 929     uint16_t dedicated_cpus;
 930     uint16_t shared_cpus;
 931     uint8_t  res4[180];
 932 };
 933
 934 /* VM CPUs */
 935 struct sysib_322 {
 936     uint8_t  res1[31];
 937     uint8_t  count;
 938     struct {
 939         uint8_t  res2[4];
 940         uint16_t total_cpus;
 941         uint16_t conf_cpus;
 942         uint16_t standby_cpus;
 943         uint16_t reserved_cpus;
 944         uint8_t  name[8];
 945         uint32_t caf;
 946         uint8_t  cpi[16];
 947         uint8_t res5[3];
 948         uint8_t ext_name_encoding;
 949         uint32_t res3;
 950         uint8_t uuid[16];
 951     } vm[8];
 952     uint8_t res4[1504];
 953     uint8_t ext_names[8][256];
 954 };
 955
 956 /* MMU defines */
 957 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 958 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 959 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 960 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 961 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 962 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 963 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 964 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 965 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 966 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 967 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 968 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 969
 970 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 971 #define _REGION_ENTRY_RO        0x200     /* region/segment protection bit    */
 972 #define _REGION_ENTRY_TF        0xc0      /* region/segment table offset      */
 973 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 974 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 975 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 976 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 977 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 978 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 979
 980 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 981 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 982 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 983 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 984
 985 #define _PAGE_RO        0x200            /* HW read-only bit  */
 986 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 987 #define _PAGE_RES0      0x800            /* bit must be zero  */
 988
 989 #define SK_C                    (0x1 << 1)
 990 #define SK_R                    (0x1 << 2)
 991 #define SK_F                    (0x1 << 3)
 992 #define SK_ACC_MASK             (0xf << 4)
 993
 994 /* SIGP order codes */
 995 #define SIGP_SENSE             0x01
 996 #define SIGP_EXTERNAL_CALL     0x02
 997 #define SIGP_EMERGENCY         0x03
 998 #define SIGP_START             0x04
 999 #define SIGP_STOP              0x05
1000 #define SIGP_RESTART           0x06
1001 #define SIGP_STOP_STORE_STATUS 0x09
1002 #define SIGP_INITIAL_CPU_RESET 0x0b
1003 #define SIGP_CPU_RESET         0x0c
1004 #define SIGP_SET_PREFIX        0x0d
1005 #define SIGP_STORE_STATUS_ADDR 0x0e
1006 #define SIGP_SET_ARCH          0x12
1007 #define SIGP_STORE_ADTL_STATUS 0x17
1008
1009 /* SIGP condition codes */
1010 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
1011 #define SIGP_CC_STATUS_STORED       1
1012 #define SIGP_CC_BUSY                2
1013 #define SIGP_CC_NOT_OPERATIONAL     3
1014
1015 /* SIGP status bits */
1016 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
1017 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
1018 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1019 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
1020 #define SIGP_STAT_STOPPED           0x00000040UL
1021 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
1022 #define SIGP_STAT_CHECK_STOP        0x00000010UL
1023 #define SIGP_STAT_INOPERATIVE       0x00000004UL
1024 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
1025 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
1026
1027 /* SIGP SET ARCHITECTURE modes */
1028 #define SIGP_MODE_ESA_S390 0
1029 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1030 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1031
1032 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1033 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1034                   target_ulong *raddr, int *flags, bool exc);
1035 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1036 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1037                  uint64_t vr);
1038 void s390_cpu_recompute_watchpoints(CPUState *cs);
1039
1040 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1041                          int len, bool is_write);
1042
1043 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
1044         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1045 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
1046         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1047 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
1048         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1049
1050 /* The value of the TOD clock for 1.1.1970. */
1051 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1052
1053 /* Converts ns to s390's clock format */
1054 static inline uint64_t time2tod(uint64_t ns) {
1055     return (ns << 9) / 125;
1056 }
1057
1058 /* Converts s390's clock format to ns */
1059 static inline uint64_t tod2time(uint64_t t) {
1060     return (t * 125) >> 9;
1061 }
1062
1063 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
1064                                   uint64_t param64)
1065 {
1066     CPUS390XState *env = &cpu->env;
1067
1068     if (env->ext_index == MAX_EXT_QUEUE - 1) {
1069         /* ugh - can't queue anymore. Let's drop. */
1070         return;
1071     }
1072
1073     env->ext_index++;
1074     assert(env->ext_index < MAX_EXT_QUEUE);
1075
1076     env->ext_queue[env->ext_index].code = code;
1077     env->ext_queue[env->ext_index].param = param;
1078     env->ext_queue[env->ext_index].param64 = param64;
1079
1080     env->pending_int |= INTERRUPT_EXT;
1081     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1082 }
1083
1084 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1085                                  uint16_t subchannel_number,
1086                                  uint32_t io_int_parm, uint32_t io_int_word)
1087 {
1088     CPUS390XState *env = &cpu->env;
1089     int isc = IO_INT_WORD_ISC(io_int_word);
1090
1091     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1092         /* ugh - can't queue anymore. Let's drop. */
1093         return;
1094     }
1095
1096     env->io_index[isc]++;
1097     assert(env->io_index[isc] < MAX_IO_QUEUE);
1098
1099     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1100     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1101     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1102     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1103
1104     env->pending_int |= INTERRUPT_IO;
1105     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1106 }
1107
1108 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1109 {
1110     CPUS390XState *env = &cpu->env;
1111
1112     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1113         /* ugh - can't queue anymore. Let's drop. */
1114         return;
1115     }
1116
1117     env->mchk_index++;
1118     assert(env->mchk_index < MAX_MCHK_QUEUE);
1119
1120     env->mchk_queue[env->mchk_index].type = 1;
1121
1122     env->pending_int |= INTERRUPT_MCHK;
1123     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1124 }
1125
1126 /* from s390-virtio-ccw */
1127 #define MEM_SECTION_SIZE             0x10000000UL
1128 #define MAX_AVAIL_SLOTS              32
1129
1130 /* fpu_helper.c */
1131 uint32_t set_cc_nz_f32(float32 v);
1132 uint32_t set_cc_nz_f64(float64 v);
1133 uint32_t set_cc_nz_f128(float128 v);
1134
1135 /* misc_helper.c */
1136 #ifndef CONFIG_USER_ONLY
1137 int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1138 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1139 #endif
1140 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1141 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1142                                      uintptr_t retaddr);
1143
1144 #ifdef CONFIG_KVM
1145 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1146                            uint16_t subchannel_nr, uint32_t io_int_parm,
1147                            uint32_t io_int_word);
1148 void kvm_s390_crw_mchk(void);
1149 void kvm_s390_enable_css_support(S390CPU *cpu);
1150 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1151                                     int vq, bool assign);
1152 int kvm_s390_cpu_restart(S390CPU *cpu);
1153 int kvm_s390_get_memslot_count(KVMState *s);
1154 void kvm_s390_cmma_reset(void);
1155 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1156 void kvm_s390_reset_vcpu(S390CPU *cpu);
1157 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1158 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1159 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1160 void kvm_s390_crypto_reset(void);
1161 #else
1162 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1163                                         uint16_t subchannel_nr,
1164                                         uint32_t io_int_parm,
1165                                         uint32_t io_int_word)
1166 {
1167 }
1168 static inline void kvm_s390_crw_mchk(void)
1169 {
1170 }
1171 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1172 {
1173 }
1174 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1175                                                   uint32_t sch, int vq,
1176                                                   bool assign)
1177 {
1178     return -ENOSYS;
1179 }
1180 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1181 {
1182     return -ENOSYS;
1183 }
1184 static inline void kvm_s390_cmma_reset(void)
1185 {
1186 }
1187 static inline int kvm_s390_get_memslot_count(KVMState *s)
1188 {
1189   return MAX_AVAIL_SLOTS;
1190 }
1191 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1192 {
1193     return -ENOSYS;
1194 }
1195 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1196 {
1197 }
1198 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1199                                          uint64_t *hw_limit)
1200 {
1201     return 0;
1202 }
1203 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1204 {
1205 }
1206 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1207 {
1208     return 0;
1209 }
1210 static inline void kvm_s390_crypto_reset(void)
1211 {
1212 }
1213 #endif
1214
1215 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1216 {
1217     if (kvm_enabled()) {
1218         return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1219     }
1220     return 0;
1221 }
1222
1223 static inline void s390_cmma_reset(void)
1224 {
1225     if (kvm_enabled()) {
1226         kvm_s390_cmma_reset();
1227     }
1228 }
1229
1230 static inline int s390_cpu_restart(S390CPU *cpu)
1231 {
1232     if (kvm_enabled()) {
1233         return kvm_s390_cpu_restart(cpu);
1234     }
1235     return -ENOSYS;
1236 }
1237
1238 static inline int s390_get_memslot_count(KVMState *s)
1239 {
1240     if (kvm_enabled()) {
1241         return kvm_s390_get_memslot_count(s);
1242     } else {
1243         return MAX_AVAIL_SLOTS;
1244     }
1245 }
1246
1247 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1248                        uint32_t io_int_parm, uint32_t io_int_word);
1249 void s390_crw_mchk(void);
1250
1251 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1252                                               uint32_t sch_id, int vq,
1253                                               bool assign)
1254 {
1255     return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1256 }
1257
1258 static inline void s390_crypto_reset(void)
1259 {
1260     if (kvm_enabled()) {
1261         kvm_s390_crypto_reset();
1262     }
1263 }
1264
1265 #ifdef CONFIG_KVM
1266 static inline bool vregs_needed(void *opaque)
1267 {
1268     if (kvm_enabled()) {
1269         return kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS);
1270     }
1271     return 0;
1272 }
1273 #else
1274 static inline bool vregs_needed(void *opaque)
1275 {
1276     return 0;
1277 }
1278 #endif
1279
1280 /* machine check interruption code */
1281
1282 /* subclasses */
1283 #define MCIC_SC_SD 0x8000000000000000ULL
1284 #define MCIC_SC_PD 0x4000000000000000ULL
1285 #define MCIC_SC_SR 0x2000000000000000ULL
1286 #define MCIC_SC_CD 0x0800000000000000ULL
1287 #define MCIC_SC_ED 0x0400000000000000ULL
1288 #define MCIC_SC_DG 0x0100000000000000ULL
1289 #define MCIC_SC_W  0x0080000000000000ULL
1290 #define MCIC_SC_CP 0x0040000000000000ULL
1291 #define MCIC_SC_SP 0x0020000000000000ULL
1292 #define MCIC_SC_CK 0x0010000000000000ULL
1293
1294 /* subclass modifiers */
1295 #define MCIC_SCM_B  0x0002000000000000ULL
1296 #define MCIC_SCM_DA 0x0000000020000000ULL
1297 #define MCIC_SCM_AP 0x0000000000080000ULL
1298
1299 /* storage errors */
1300 #define MCIC_SE_SE 0x0000800000000000ULL
1301 #define MCIC_SE_SC 0x0000400000000000ULL
1302 #define MCIC_SE_KE 0x0000200000000000ULL
1303 #define MCIC_SE_DS 0x0000100000000000ULL
1304 #define MCIC_SE_IE 0x0000000080000000ULL
1305
1306 /* validity bits */
1307 #define MCIC_VB_WP 0x0000080000000000ULL
1308 #define MCIC_VB_MS 0x0000040000000000ULL
1309 #define MCIC_VB_PM 0x0000020000000000ULL
1310 #define MCIC_VB_IA 0x0000010000000000ULL
1311 #define MCIC_VB_FA 0x0000008000000000ULL
1312 #define MCIC_VB_VR 0x0000004000000000ULL
1313 #define MCIC_VB_EC 0x0000002000000000ULL
1314 #define MCIC_VB_FP 0x0000001000000000ULL
1315 #define MCIC_VB_GR 0x0000000800000000ULL
1316 #define MCIC_VB_CR 0x0000000400000000ULL
1317 #define MCIC_VB_ST 0x0000000100000000ULL
1318 #define MCIC_VB_AR 0x0000000040000000ULL
1319 #define MCIC_VB_PR 0x0000000000200000ULL
1320 #define MCIC_VB_FC 0x0000000000100000ULL
1321 #define MCIC_VB_CT 0x0000000000020000ULL
1322 #define MCIC_VB_CC 0x0000000000010000ULL
1323
1324 #endif