target-cris/helper.c

   1 /*
   2  *  CRIS helper routines.
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "mmu.h"
  24 #include "qemu/host-utils.h"
  25 #include "exec/cpu_ldst.h"
  26
  27
  28 //#define CRIS_HELPER_DEBUG
  29
  30
  31 #ifdef CRIS_HELPER_DEBUG
  32 #define D(x) x
  33 #define D_LOG(...) qemu_log(__VA_ARGS__)
  34 #else
  35 #define D(x)
  36 #define D_LOG(...) do { } while (0)
  37 #endif
  38
  39 #if defined(CONFIG_USER_ONLY)
  40
  41 void cris_cpu_do_interrupt(CPUState *cs)
  42 {
  43     CRISCPU *cpu = CRIS_CPU(cs);
  44     CPUCRISState *env = &cpu->env;
  45
  46     cs->exception_index = -1;
  47     env->pregs[PR_ERP] = env->pc;
  48 }
  49
  50 void crisv10_cpu_do_interrupt(CPUState *cs)
  51 {
  52     cris_cpu_do_interrupt(cs);
  53 }
  54
  55 int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  56                               int mmu_idx)
  57 {
  58     CRISCPU *cpu = CRIS_CPU(cs);
  59
  60     cs->exception_index = 0xaa;
  61     cpu->env.pregs[PR_EDA] = address;
  62     cpu_dump_state(cs, stderr, fprintf, 0);
  63     return 1;
  64 }
  65
  66 #else /* !CONFIG_USER_ONLY */
  67
  68
  69 static void cris_shift_ccs(CPUCRISState *env)
  70 {
  71     uint32_t ccs;
  72     /* Apply the ccs shift.  */
  73     ccs = env->pregs[PR_CCS];
  74     ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
  75     env->pregs[PR_CCS] = ccs;
  76 }
  77
  78 int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  79                               int mmu_idx)
  80 {
  81     CRISCPU *cpu = CRIS_CPU(cs);
  82     CPUCRISState *env = &cpu->env;
  83     struct cris_mmu_result res;
  84     int prot, miss;
  85     int r = -1;
  86     target_ulong phy;
  87
  88     qemu_log_mask(CPU_LOG_MMU, "%s addr=%" VADDR_PRIx " pc=%x rw=%x\n",
  89             __func__, address, env->pc, rw);
  90     miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
  91                               rw, mmu_idx, 0);
  92     if (miss) {
  93         if (cs->exception_index == EXCP_BUSFAULT) {
  94             cpu_abort(cs,
  95                       "CRIS: Illegal recursive bus fault."
  96                       "addr=%" VADDR_PRIx " rw=%d\n",
  97                       address, rw);
  98         }
  99
 100         env->pregs[PR_EDA] = address;
 101         cs->exception_index = EXCP_BUSFAULT;
 102         env->fault_vector = res.bf_vec;
 103         r = 1;
 104     } else {
 105         /*
 106          * Mask off the cache selection bit. The ETRAX busses do not
 107          * see the top bit.
 108          */
 109         phy = res.phy & ~0x80000000;
 110         prot = res.prot;
 111         tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
 112                      prot, mmu_idx, TARGET_PAGE_SIZE);
 113         r = 0;
 114     }
 115     if (r > 0) {
 116         qemu_log_mask(CPU_LOG_MMU,
 117                 "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x"
 118                 " pc=%x\n", __func__, r, cs->interrupt_request, address,
 119                 res.phy, res.bf_vec, env->pc);
 120     }
 121     return r;
 122 }
 123
 124 void crisv10_cpu_do_interrupt(CPUState *cs)
 125 {
 126     CRISCPU *cpu = CRIS_CPU(cs);
 127     CPUCRISState *env = &cpu->env;
 128     int ex_vec = -1;
 129
 130     D_LOG("exception index=%d interrupt_req=%d\n",
 131           cs->exception_index,
 132           cs->interrupt_request);
 133
 134     if (env->dslot) {
 135         /* CRISv10 never takes interrupts while in a delay-slot.  */
 136         cpu_abort(cs, "CRIS: Interrupt on delay-slot\n");
 137     }
 138
 139     assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
 140     switch (cs->exception_index) {
 141     case EXCP_BREAK:
 142         /* These exceptions are genereated by the core itself.
 143            ERP should point to the insn following the brk.  */
 144         ex_vec = env->trap_vector;
 145         env->pregs[PRV10_BRP] = env->pc;
 146         break;
 147
 148     case EXCP_NMI:
 149         /* NMI is hardwired to vector zero.  */
 150         ex_vec = 0;
 151         env->pregs[PR_CCS] &= ~M_FLAG_V10;
 152         env->pregs[PRV10_BRP] = env->pc;
 153         break;
 154
 155     case EXCP_BUSFAULT:
 156         cpu_abort(cs, "Unhandled busfault");
 157         break;
 158
 159     default:
 160         /* The interrupt controller gives us the vector.  */
 161         ex_vec = env->interrupt_vector;
 162         /* Normal interrupts are taken between
 163            TB's.  env->pc is valid here.  */
 164         env->pregs[PR_ERP] = env->pc;
 165         break;
 166     }
 167
 168     if (env->pregs[PR_CCS] & U_FLAG) {
 169         /* Swap stack pointers.  */
 170         env->pregs[PR_USP] = env->regs[R_SP];
 171         env->regs[R_SP] = env->ksp;
 172     }
 173
 174     /* Now that we are in kernel mode, load the handlers address.  */
 175     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 176     env->locked_irq = 1;
 177     env->pregs[PR_CCS] |= F_FLAG_V10; /* set F.  */
 178
 179     qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 180                   __func__, env->pc, ex_vec,
 181                   env->pregs[PR_CCS],
 182                   env->pregs[PR_PID],
 183                   env->pregs[PR_ERP]);
 184 }
 185
 186 void cris_cpu_do_interrupt(CPUState *cs)
 187 {
 188     CRISCPU *cpu = CRIS_CPU(cs);
 189     CPUCRISState *env = &cpu->env;
 190     int ex_vec = -1;
 191
 192     D_LOG("exception index=%d interrupt_req=%d\n",
 193           cs->exception_index,
 194           cs->interrupt_request);
 195
 196     switch (cs->exception_index) {
 197     case EXCP_BREAK:
 198         /* These exceptions are genereated by the core itself.
 199            ERP should point to the insn following the brk.  */
 200         ex_vec = env->trap_vector;
 201         env->pregs[PR_ERP] = env->pc;
 202         break;
 203
 204     case EXCP_NMI:
 205         /* NMI is hardwired to vector zero.  */
 206         ex_vec = 0;
 207         env->pregs[PR_CCS] &= ~M_FLAG_V32;
 208         env->pregs[PR_NRP] = env->pc;
 209         break;
 210
 211     case EXCP_BUSFAULT:
 212         ex_vec = env->fault_vector;
 213         env->pregs[PR_ERP] = env->pc;
 214         break;
 215
 216     default:
 217         /* The interrupt controller gives us the vector.  */
 218         ex_vec = env->interrupt_vector;
 219         /* Normal interrupts are taken between
 220            TB's.  env->pc is valid here.  */
 221         env->pregs[PR_ERP] = env->pc;
 222         break;
 223     }
 224
 225     /* Fill in the IDX field.  */
 226     env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
 227
 228     if (env->dslot) {
 229         D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
 230               " ERP=%x pid=%x ccs=%x cc=%d %x\n",
 231               ex_vec, env->pc, env->dslot,
 232               env->regs[R_SP],
 233               env->pregs[PR_ERP], env->pregs[PR_PID],
 234               env->pregs[PR_CCS],
 235               env->cc_op, env->cc_mask);
 236         /* We loose the btarget, btaken state here so rexec the
 237            branch.  */
 238         env->pregs[PR_ERP] -= env->dslot;
 239         /* Exception starts with dslot cleared.  */
 240         env->dslot = 0;
 241     }
 242
 243     if (env->pregs[PR_CCS] & U_FLAG) {
 244         /* Swap stack pointers.  */
 245         env->pregs[PR_USP] = env->regs[R_SP];
 246         env->regs[R_SP] = env->ksp;
 247     }
 248
 249     /* Apply the CRIS CCS shift. Clears U if set.  */
 250     cris_shift_ccs(env);
 251
 252     /* Now that we are in kernel mode, load the handlers address.
 253        This load may not fault, real hw leaves that behaviour as
 254        undefined.  */
 255     env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
 256
 257     /* Clear the excption_index to avoid spurios hw_aborts for recursive
 258        bus faults.  */
 259     cs->exception_index = -1;
 260
 261     D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
 262           __func__, env->pc, ex_vec,
 263           env->pregs[PR_CCS],
 264           env->pregs[PR_PID],
 265           env->pregs[PR_ERP]);
 266 }
 267
 268 hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 269 {
 270     CRISCPU *cpu = CRIS_CPU(cs);
 271     uint32_t phy = addr;
 272     struct cris_mmu_result res;
 273     int miss;
 274
 275     miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
 276     /* If D TLB misses, try I TLB.  */
 277     if (miss) {
 278         miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
 279     }
 280
 281     if (!miss) {
 282         phy = res.phy;
 283     }
 284     D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
 285     return phy;
 286 }
 287 #endif
 288
 289 bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 290 {
 291     CPUClass *cc = CPU_GET_CLASS(cs);
 292     CRISCPU *cpu = CRIS_CPU(cs);
 293     CPUCRISState *env = &cpu->env;
 294     bool ret = false;
 295
 296     if (interrupt_request & CPU_INTERRUPT_HARD
 297         && (env->pregs[PR_CCS] & I_FLAG)
 298         && !env->locked_irq) {
 299         cs->exception_index = EXCP_IRQ;
 300         cc->do_interrupt(cs);
 301         ret = true;
 302     }
 303     if (interrupt_request & CPU_INTERRUPT_NMI) {
 304         unsigned int m_flag_archval;
 305         if (env->pregs[PR_VR] < 32) {
 306             m_flag_archval = M_FLAG_V10;
 307         } else {
 308             m_flag_archval = M_FLAG_V32;
 309         }
 310         if ((env->pregs[PR_CCS] & m_flag_archval)) {
 311             cs->exception_index = EXCP_NMI;
 312             cc->do_interrupt(cs);
 313             ret = true;
 314         }
 315     }
 316
 317     return ret;
 318 }