target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26
  27 //#define DEBUG_KVM
  28
  29 #ifdef DEBUG_KVM
  30 #define dprintf(fmt, ...) \
  31     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  32 #else
  33 #define dprintf(fmt, ...) \
  34     do { } while (0)
  35 #endif
  36
  37 #ifdef KVM_CAP_EXT_CPUID
  38
  39 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  40 {
  41     struct kvm_cpuid2 *cpuid;
  42     int r, size;
  43
  44     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  45     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  46     cpuid->nent = max;
  47     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  48     if (r == 0 && cpuid->nent >= max) {
  49         r = -E2BIG;
  50     }
  51     if (r < 0) {
  52         if (r == -E2BIG) {
  53             qemu_free(cpuid);
  54             return NULL;
  55         } else {
  56             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  57                     strerror(-r));
  58             exit(1);
  59         }
  60     }
  61     return cpuid;
  62 }
  63
  64 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  65 {
  66     struct kvm_cpuid2 *cpuid;
  67     int i, max;
  68     uint32_t ret = 0;
  69     uint32_t cpuid_1_edx;
  70
  71     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  72         return -1U;
  73     }
  74
  75     max = 1;
  76     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  77         max *= 2;
  78     }
  79
  80     for (i = 0; i < cpuid->nent; ++i) {
  81         if (cpuid->entries[i].function == function) {
  82             switch (reg) {
  83             case R_EAX:
  84                 ret = cpuid->entries[i].eax;
  85                 break;
  86             case R_EBX:
  87                 ret = cpuid->entries[i].ebx;
  88                 break;
  89             case R_ECX:
  90                 ret = cpuid->entries[i].ecx;
  91                 break;
  92             case R_EDX:
  93                 ret = cpuid->entries[i].edx;
  94                 if (function == 0x80000001) {
  95                     /* On Intel, kvm returns cpuid according to the Intel spec,
  96                      * so add missing bits according to the AMD spec:
  97                      */
  98                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
  99                     ret |= cpuid_1_edx & 0xdfeff7ff;
 100                 }
 101                 break;
 102             }
 103         }
 104     }
 105
 106     qemu_free(cpuid);
 107
 108     return ret;
 109 }
 110
 111 #else
 112
 113 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 114 {
 115     return -1U;
 116 }
 117
 118 #endif
 119
 120 int kvm_arch_init_vcpu(CPUState *env)
 121 {
 122     struct {
 123         struct kvm_cpuid2 cpuid;
 124         struct kvm_cpuid_entry2 entries[100];
 125     } __attribute__((packed)) cpuid_data;
 126     uint32_t limit, i, j, cpuid_i;
 127     uint32_t unused;
 128
 129     cpuid_i = 0;
 130
 131     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 132
 133     for (i = 0; i <= limit; i++) {
 134         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 135
 136         switch (i) {
 137         case 2: {
 138             /* Keep reading function 2 till all the input is received */
 139             int times;
 140
 141             c->function = i;
 142             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 143                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 144             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 145             times = c->eax & 0xff;
 146
 147             for (j = 1; j < times; ++j) {
 148                 c = &cpuid_data.entries[cpuid_i++];
 149                 c->function = i;
 150                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 151                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 152             }
 153             break;
 154         }
 155         case 4:
 156         case 0xb:
 157         case 0xd:
 158             for (j = 0; ; j++) {
 159                 c->function = i;
 160                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 161                 c->index = j;
 162                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 163
 164                 if (i == 4 && c->eax == 0)
 165                     break;
 166                 if (i == 0xb && !(c->ecx & 0xff00))
 167                     break;
 168                 if (i == 0xd && c->eax == 0)
 169                     break;
 170
 171                 c = &cpuid_data.entries[cpuid_i++];
 172             }
 173             break;
 174         default:
 175             c->function = i;
 176             c->flags = 0;
 177             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 178             break;
 179         }
 180     }
 181     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 182
 183     for (i = 0x80000000; i <= limit; i++) {
 184         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 185
 186         c->function = i;
 187         c->flags = 0;
 188         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 189     }
 190
 191     cpuid_data.cpuid.nent = cpuid_i;
 192
 193     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 194 }
 195
 196 static int kvm_has_msr_star(CPUState *env)
 197 {
 198     static int has_msr_star;
 199     int ret;
 200
 201     /* first time */
 202     if (has_msr_star == 0) {
 203         struct kvm_msr_list msr_list, *kvm_msr_list;
 204
 205         has_msr_star = -1;
 206
 207         /* Obtain MSR list from KVM.  These are the MSRs that we must
 208          * save/restore */
 209         msr_list.nmsrs = 0;
 210         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 211         if (ret < 0)
 212             return 0;
 213
 214         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 215                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 216
 217         kvm_msr_list->nmsrs = msr_list.nmsrs;
 218         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 219         if (ret >= 0) {
 220             int i;
 221
 222             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 223                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 224                     has_msr_star = 1;
 225                     break;
 226                 }
 227             }
 228         }
 229
 230         free(kvm_msr_list);
 231     }
 232
 233     if (has_msr_star == 1)
 234         return 1;
 235     return 0;
 236 }
 237
 238 int kvm_arch_init(KVMState *s, int smp_cpus)
 239 {
 240     int ret;
 241
 242     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 243      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 244      * must be part of guest physical memory, we need to allocate it.  Older
 245      * versions of KVM just assumed that it would be at the end of physical
 246      * memory but that doesn't work with more than 4GB of memory.  We simply
 247      * refuse to work with those older versions of KVM. */
 248     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 249     if (ret <= 0) {
 250         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 251         return ret;
 252     }
 253
 254     /* this address is 3 pages before the bios, and the bios should present
 255      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 256      * this?
 257      */
 258     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 259 }
 260
 261 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 262 {
 263     lhs->selector = rhs->selector;
 264     lhs->base = rhs->base;
 265     lhs->limit = rhs->limit;
 266     lhs->type = 3;
 267     lhs->present = 1;
 268     lhs->dpl = 3;
 269     lhs->db = 0;
 270     lhs->s = 1;
 271     lhs->l = 0;
 272     lhs->g = 0;
 273     lhs->avl = 0;
 274     lhs->unusable = 0;
 275 }
 276
 277 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 278 {
 279     unsigned flags = rhs->flags;
 280     lhs->selector = rhs->selector;
 281     lhs->base = rhs->base;
 282     lhs->limit = rhs->limit;
 283     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 284     lhs->present = (flags & DESC_P_MASK) != 0;
 285     lhs->dpl = rhs->selector & 3;
 286     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 287     lhs->s = (flags & DESC_S_MASK) != 0;
 288     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 289     lhs->g = (flags & DESC_G_MASK) != 0;
 290     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 291     lhs->unusable = 0;
 292 }
 293
 294 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 295 {
 296     lhs->selector = rhs->selector;
 297     lhs->base = rhs->base;
 298     lhs->limit = rhs->limit;
 299     lhs->flags =
 300         (rhs->type << DESC_TYPE_SHIFT)
 301         | (rhs->present * DESC_P_MASK)
 302         | (rhs->dpl << DESC_DPL_SHIFT)
 303         | (rhs->db << DESC_B_SHIFT)
 304         | (rhs->s * DESC_S_MASK)
 305         | (rhs->l << DESC_L_SHIFT)
 306         | (rhs->g * DESC_G_MASK)
 307         | (rhs->avl * DESC_AVL_MASK);
 308 }
 309
 310 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 311 {
 312     if (set)
 313         *kvm_reg = *qemu_reg;
 314     else
 315         *qemu_reg = *kvm_reg;
 316 }
 317
 318 static int kvm_getput_regs(CPUState *env, int set)
 319 {
 320     struct kvm_regs regs;
 321     int ret = 0;
 322
 323     if (!set) {
 324         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 325         if (ret < 0)
 326             return ret;
 327     }
 328
 329     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 330     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 331     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 332     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 333     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 334     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 335     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 336     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 337 #ifdef TARGET_X86_64
 338     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 339     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 340     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 341     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 342     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 343     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 344     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 345     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 346 #endif
 347
 348     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 349     kvm_getput_reg(&regs.rip, &env->eip, set);
 350
 351     if (set)
 352         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 353
 354     return ret;
 355 }
 356
 357 static int kvm_put_fpu(CPUState *env)
 358 {
 359     struct kvm_fpu fpu;
 360     int i;
 361
 362     memset(&fpu, 0, sizeof fpu);
 363     fpu.fsw = env->fpus & ~(7 << 11);
 364     fpu.fsw |= (env->fpstt & 7) << 11;
 365     fpu.fcw = env->fpuc;
 366     for (i = 0; i < 8; ++i)
 367         fpu.ftwx |= (!env->fptags[i]) << i;
 368     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 369     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 370     fpu.mxcsr = env->mxcsr;
 371
 372     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 373 }
 374
 375 static int kvm_put_sregs(CPUState *env)
 376 {
 377     struct kvm_sregs sregs;
 378
 379     memcpy(sregs.interrupt_bitmap,
 380            env->interrupt_bitmap,
 381            sizeof(sregs.interrupt_bitmap));
 382
 383     if ((env->eflags & VM_MASK)) {
 384             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 385             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 386             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 387             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 388             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 389             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 390     } else {
 391             set_seg(&sregs.cs, &env->segs[R_CS]);
 392             set_seg(&sregs.ds, &env->segs[R_DS]);
 393             set_seg(&sregs.es, &env->segs[R_ES]);
 394             set_seg(&sregs.fs, &env->segs[R_FS]);
 395             set_seg(&sregs.gs, &env->segs[R_GS]);
 396             set_seg(&sregs.ss, &env->segs[R_SS]);
 397
 398             if (env->cr[0] & CR0_PE_MASK) {
 399                 /* force ss cpl to cs cpl */
 400                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 401                         (sregs.cs.selector & 3);
 402                 sregs.ss.dpl = sregs.ss.selector & 3;
 403             }
 404     }
 405
 406     set_seg(&sregs.tr, &env->tr);
 407     set_seg(&sregs.ldt, &env->ldt);
 408
 409     sregs.idt.limit = env->idt.limit;
 410     sregs.idt.base = env->idt.base;
 411     sregs.gdt.limit = env->gdt.limit;
 412     sregs.gdt.base = env->gdt.base;
 413
 414     sregs.cr0 = env->cr[0];
 415     sregs.cr2 = env->cr[2];
 416     sregs.cr3 = env->cr[3];
 417     sregs.cr4 = env->cr[4];
 418
 419     sregs.cr8 = cpu_get_apic_tpr(env);
 420     sregs.apic_base = cpu_get_apic_base(env);
 421
 422     sregs.efer = env->efer;
 423
 424     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 425 }
 426
 427 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 428                               uint32_t index, uint64_t value)
 429 {
 430     entry->index = index;
 431     entry->data = value;
 432 }
 433
 434 static int kvm_put_msrs(CPUState *env)
 435 {
 436     struct {
 437         struct kvm_msrs info;
 438         struct kvm_msr_entry entries[100];
 439     } msr_data;
 440     struct kvm_msr_entry *msrs = msr_data.entries;
 441     int n = 0;
 442
 443     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 444     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 445     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 446     if (kvm_has_msr_star(env))
 447         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 448     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 449 #ifdef TARGET_X86_64
 450     /* FIXME if lm capable */
 451     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 452     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 453     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 454     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 455 #endif
 456     msr_data.info.nmsrs = n;
 457
 458     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 459
 460 }
 461
 462
 463 static int kvm_get_fpu(CPUState *env)
 464 {
 465     struct kvm_fpu fpu;
 466     int i, ret;
 467
 468     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 469     if (ret < 0)
 470         return ret;
 471
 472     env->fpstt = (fpu.fsw >> 11) & 7;
 473     env->fpus = fpu.fsw;
 474     env->fpuc = fpu.fcw;
 475     for (i = 0; i < 8; ++i)
 476         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 477     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 478     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 479     env->mxcsr = fpu.mxcsr;
 480
 481     return 0;
 482 }
 483
 484 static int kvm_get_sregs(CPUState *env)
 485 {
 486     struct kvm_sregs sregs;
 487     uint32_t hflags;
 488     int ret;
 489
 490     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 491     if (ret < 0)
 492         return ret;
 493
 494     memcpy(env->interrupt_bitmap,
 495            sregs.interrupt_bitmap,
 496            sizeof(sregs.interrupt_bitmap));
 497
 498     get_seg(&env->segs[R_CS], &sregs.cs);
 499     get_seg(&env->segs[R_DS], &sregs.ds);
 500     get_seg(&env->segs[R_ES], &sregs.es);
 501     get_seg(&env->segs[R_FS], &sregs.fs);
 502     get_seg(&env->segs[R_GS], &sregs.gs);
 503     get_seg(&env->segs[R_SS], &sregs.ss);
 504
 505     get_seg(&env->tr, &sregs.tr);
 506     get_seg(&env->ldt, &sregs.ldt);
 507
 508     env->idt.limit = sregs.idt.limit;
 509     env->idt.base = sregs.idt.base;
 510     env->gdt.limit = sregs.gdt.limit;
 511     env->gdt.base = sregs.gdt.base;
 512
 513     env->cr[0] = sregs.cr0;
 514     env->cr[2] = sregs.cr2;
 515     env->cr[3] = sregs.cr3;
 516     env->cr[4] = sregs.cr4;
 517
 518     cpu_set_apic_base(env, sregs.apic_base);
 519
 520     env->efer = sregs.efer;
 521     //cpu_set_apic_tpr(env, sregs.cr8);
 522
 523 #define HFLAG_COPY_MASK ~( \
 524                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 525                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 526                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 527                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 528
 529
 530
 531     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 532     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 533     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 534             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 535     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 536     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 537             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 538
 539     if (env->efer & MSR_EFER_LMA) {
 540         hflags |= HF_LMA_MASK;
 541     }
 542
 543     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 544         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 545     } else {
 546         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 547                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 548         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 549                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 550         if (!(env->cr[0] & CR0_PE_MASK) ||
 551                    (env->eflags & VM_MASK) ||
 552                    !(hflags & HF_CS32_MASK)) {
 553                 hflags |= HF_ADDSEG_MASK;
 554             } else {
 555                 hflags |= ((env->segs[R_DS].base |
 556                                 env->segs[R_ES].base |
 557                                 env->segs[R_SS].base) != 0) <<
 558                     HF_ADDSEG_SHIFT;
 559             }
 560     }
 561     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 562
 563     return 0;
 564 }
 565
 566 static int kvm_get_msrs(CPUState *env)
 567 {
 568     struct {
 569         struct kvm_msrs info;
 570         struct kvm_msr_entry entries[100];
 571     } msr_data;
 572     struct kvm_msr_entry *msrs = msr_data.entries;
 573     int ret, i, n;
 574
 575     n = 0;
 576     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 577     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 578     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 579     if (kvm_has_msr_star(env))
 580         msrs[n++].index = MSR_STAR;
 581     msrs[n++].index = MSR_IA32_TSC;
 582 #ifdef TARGET_X86_64
 583     /* FIXME lm_capable_kernel */
 584     msrs[n++].index = MSR_CSTAR;
 585     msrs[n++].index = MSR_KERNELGSBASE;
 586     msrs[n++].index = MSR_FMASK;
 587     msrs[n++].index = MSR_LSTAR;
 588 #endif
 589     msr_data.info.nmsrs = n;
 590     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 591     if (ret < 0)
 592         return ret;
 593
 594     for (i = 0; i < ret; i++) {
 595         switch (msrs[i].index) {
 596         case MSR_IA32_SYSENTER_CS:
 597             env->sysenter_cs = msrs[i].data;
 598             break;
 599         case MSR_IA32_SYSENTER_ESP:
 600             env->sysenter_esp = msrs[i].data;
 601             break;
 602         case MSR_IA32_SYSENTER_EIP:
 603             env->sysenter_eip = msrs[i].data;
 604             break;
 605         case MSR_STAR:
 606             env->star = msrs[i].data;
 607             break;
 608 #ifdef TARGET_X86_64
 609         case MSR_CSTAR:
 610             env->cstar = msrs[i].data;
 611             break;
 612         case MSR_KERNELGSBASE:
 613             env->kernelgsbase = msrs[i].data;
 614             break;
 615         case MSR_FMASK:
 616             env->fmask = msrs[i].data;
 617             break;
 618         case MSR_LSTAR:
 619             env->lstar = msrs[i].data;
 620             break;
 621 #endif
 622         case MSR_IA32_TSC:
 623             env->tsc = msrs[i].data;
 624             break;
 625         }
 626     }
 627
 628     return 0;
 629 }
 630
 631 int kvm_arch_put_registers(CPUState *env)
 632 {
 633     int ret;
 634
 635     ret = kvm_getput_regs(env, 1);
 636     if (ret < 0)
 637         return ret;
 638
 639     ret = kvm_put_fpu(env);
 640     if (ret < 0)
 641         return ret;
 642
 643     ret = kvm_put_sregs(env);
 644     if (ret < 0)
 645         return ret;
 646
 647     ret = kvm_put_msrs(env);
 648     if (ret < 0)
 649         return ret;
 650
 651     return 0;
 652 }
 653
 654 int kvm_arch_get_registers(CPUState *env)
 655 {
 656     int ret;
 657
 658     ret = kvm_getput_regs(env, 0);
 659     if (ret < 0)
 660         return ret;
 661
 662     ret = kvm_get_fpu(env);
 663     if (ret < 0)
 664         return ret;
 665
 666     ret = kvm_get_sregs(env);
 667     if (ret < 0)
 668         return ret;
 669
 670     ret = kvm_get_msrs(env);
 671     if (ret < 0)
 672         return ret;
 673
 674     return 0;
 675 }
 676
 677 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 678 {
 679     /* Try to inject an interrupt if the guest can accept it */
 680     if (run->ready_for_interrupt_injection &&
 681         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 682         (env->eflags & IF_MASK)) {
 683         int irq;
 684
 685         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 686         irq = cpu_get_pic_interrupt(env);
 687         if (irq >= 0) {
 688             struct kvm_interrupt intr;
 689             intr.irq = irq;
 690             /* FIXME: errors */
 691             dprintf("injected interrupt %d\n", irq);
 692             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 693         }
 694     }
 695
 696     /* If we have an interrupt but the guest is not ready to receive an
 697      * interrupt, request an interrupt window exit.  This will
 698      * cause a return to userspace as soon as the guest is ready to
 699      * receive interrupts. */
 700     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 701         run->request_interrupt_window = 1;
 702     else
 703         run->request_interrupt_window = 0;
 704
 705     dprintf("setting tpr\n");
 706     run->cr8 = cpu_get_apic_tpr(env);
 707
 708     return 0;
 709 }
 710
 711 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 712 {
 713     if (run->if_flag)
 714         env->eflags |= IF_MASK;
 715     else
 716         env->eflags &= ~IF_MASK;
 717
 718     cpu_set_apic_tpr(env, run->cr8);
 719     cpu_set_apic_base(env, run->apic_base);
 720
 721     return 0;
 722 }
 723
 724 static int kvm_handle_halt(CPUState *env)
 725 {
 726     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 727           (env->eflags & IF_MASK)) &&
 728         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 729         env->halted = 1;
 730         env->exception_index = EXCP_HLT;
 731         return 0;
 732     }
 733
 734     return 1;
 735 }
 736
 737 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 738 {
 739     int ret = 0;
 740
 741     switch (run->exit_reason) {
 742     case KVM_EXIT_HLT:
 743         dprintf("handle_hlt\n");
 744         ret = kvm_handle_halt(env);
 745         break;
 746     }
 747
 748     return ret;
 749 }
 750
 751 #ifdef KVM_CAP_SET_GUEST_DEBUG
 752 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 753 {
 754     const static uint8_t int3 = 0xcc;
 755
 756     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 757         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
 758         return -EINVAL;
 759     return 0;
 760 }
 761
 762 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 763 {
 764     uint8_t int3;
 765
 766     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 767         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 768         return -EINVAL;
 769     return 0;
 770 }
 771
 772 static struct {
 773     target_ulong addr;
 774     int len;
 775     int type;
 776 } hw_breakpoint[4];
 777
 778 static int nb_hw_breakpoint;
 779
 780 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 781 {
 782     int n;
 783
 784     for (n = 0; n < nb_hw_breakpoint; n++)
 785         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 786             (hw_breakpoint[n].len == len || len == -1))
 787             return n;
 788     return -1;
 789 }
 790
 791 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 792                                   target_ulong len, int type)
 793 {
 794     switch (type) {
 795     case GDB_BREAKPOINT_HW:
 796         len = 1;
 797         break;
 798     case GDB_WATCHPOINT_WRITE:
 799     case GDB_WATCHPOINT_ACCESS:
 800         switch (len) {
 801         case 1:
 802             break;
 803         case 2:
 804         case 4:
 805         case 8:
 806             if (addr & (len - 1))
 807                 return -EINVAL;
 808             break;
 809         default:
 810             return -EINVAL;
 811         }
 812         break;
 813     default:
 814         return -ENOSYS;
 815     }
 816
 817     if (nb_hw_breakpoint == 4)
 818         return -ENOBUFS;
 819
 820     if (find_hw_breakpoint(addr, len, type) >= 0)
 821         return -EEXIST;
 822
 823     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 824     hw_breakpoint[nb_hw_breakpoint].len = len;
 825     hw_breakpoint[nb_hw_breakpoint].type = type;
 826     nb_hw_breakpoint++;
 827
 828     return 0;
 829 }
 830
 831 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 832                                   target_ulong len, int type)
 833 {
 834     int n;
 835
 836     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
 837     if (n < 0)
 838         return -ENOENT;
 839
 840     nb_hw_breakpoint--;
 841     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
 842
 843     return 0;
 844 }
 845
 846 void kvm_arch_remove_all_hw_breakpoints(void)
 847 {
 848     nb_hw_breakpoint = 0;
 849 }
 850
 851 static CPUWatchpoint hw_watchpoint;
 852
 853 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
 854 {
 855     int handle = 0;
 856     int n;
 857
 858     if (arch_info->exception == 1) {
 859         if (arch_info->dr6 & (1 << 14)) {
 860             if (cpu_single_env->singlestep_enabled)
 861                 handle = 1;
 862         } else {
 863             for (n = 0; n < 4; n++)
 864                 if (arch_info->dr6 & (1 << n))
 865                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
 866                     case 0x0:
 867                         handle = 1;
 868                         break;
 869                     case 0x1:
 870                         handle = 1;
 871                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 872                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 873                         hw_watchpoint.flags = BP_MEM_WRITE;
 874                         break;
 875                     case 0x3:
 876                         handle = 1;
 877                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 878                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 879                         hw_watchpoint.flags = BP_MEM_ACCESS;
 880                         break;
 881                     }
 882         }
 883     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
 884         handle = 1;
 885
 886     if (!handle)
 887         kvm_update_guest_debug(cpu_single_env,
 888                         (arch_info->exception == 1) ?
 889                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
 890
 891     return handle;
 892 }
 893
 894 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
 895 {
 896     const uint8_t type_code[] = {
 897         [GDB_BREAKPOINT_HW] = 0x0,
 898         [GDB_WATCHPOINT_WRITE] = 0x1,
 899         [GDB_WATCHPOINT_ACCESS] = 0x3
 900     };
 901     const uint8_t len_code[] = {
 902         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
 903     };
 904     int n;
 905
 906     if (kvm_sw_breakpoints_active(env))
 907         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
 908
 909     if (nb_hw_breakpoint > 0) {
 910         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
 911         dbg->arch.debugreg[7] = 0x0600;
 912         for (n = 0; n < nb_hw_breakpoint; n++) {
 913             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
 914             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
 915                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
 916                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
 917         }
 918     }
 919 }
 920 #endif /* KVM_CAP_SET_GUEST_DEBUG */