3 * TI X3130 pci express downstream port switch
5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
6 * VA Linux Systems Japan K.K.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "hw/pci/pci_ids.h"
24 #include "hw/pci/msi.h"
25 #include "hw/pci/pcie.h"
26 #include "hw/pci/pcie_port.h"
27 #include "qapi/error.h"
28 #include "qemu/module.h"
30 #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */
31 #define XIO3130_REVISION 0x1
32 #define XIO3130_MSI_OFFSET 0x70
33 #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
34 #define XIO3130_MSI_NR_VECTOR 1
35 #define XIO3130_SSVID_OFFSET 0x80
36 #define XIO3130_SSVID_SVID 0
37 #define XIO3130_SSVID_SSID 0
38 #define XIO3130_EXP_OFFSET 0x90
39 #define XIO3130_AER_OFFSET 0x100
41 static void xio3130_downstream_write_config(PCIDevice
*d
, uint32_t address
,
42 uint32_t val
, int len
)
44 pci_bridge_write_config(d
, address
, val
, len
);
45 pcie_cap_flr_write_config(d
, address
, val
, len
);
46 pcie_cap_slot_write_config(d
, address
, val
, len
);
47 pcie_aer_write_config(d
, address
, val
, len
);
50 static void xio3130_downstream_reset(DeviceState
*qdev
)
52 PCIDevice
*d
= PCI_DEVICE(qdev
);
54 pcie_cap_deverr_reset(d
);
55 pcie_cap_slot_reset(d
);
56 pcie_cap_arifwd_reset(d
);
57 pci_bridge_reset(qdev
);
60 static void xio3130_downstream_realize(PCIDevice
*d
, Error
**errp
)
62 PCIEPort
*p
= PCIE_PORT(d
);
63 PCIESlot
*s
= PCIE_SLOT(d
);
66 pci_bridge_initfn(d
, TYPE_PCIE_BUS
);
67 pcie_port_init_reg(d
);
69 rc
= msi_init(d
, XIO3130_MSI_OFFSET
, XIO3130_MSI_NR_VECTOR
,
70 XIO3130_MSI_SUPPORTED_FLAGS
& PCI_MSI_FLAGS_64BIT
,
71 XIO3130_MSI_SUPPORTED_FLAGS
& PCI_MSI_FLAGS_MASKBIT
,
74 assert(rc
== -ENOTSUP
);
78 rc
= pci_bridge_ssvid_init(d
, XIO3130_SSVID_OFFSET
,
79 XIO3130_SSVID_SVID
, XIO3130_SSVID_SSID
,
85 rc
= pcie_cap_init(d
, XIO3130_EXP_OFFSET
, PCI_EXP_TYPE_DOWNSTREAM
,
91 pcie_cap_deverr_init(d
);
92 pcie_cap_slot_init(d
, s
->slot
);
93 pcie_cap_arifwd_init(d
);
95 pcie_chassis_create(s
->chassis
);
96 rc
= pcie_chassis_add_slot(s
);
98 error_setg(errp
, "Can't add chassis slot, error %d", rc
);
102 rc
= pcie_aer_init(d
, PCI_ERR_VER
, XIO3130_AER_OFFSET
,
103 PCI_ERR_SIZEOF
, errp
);
111 pcie_chassis_del_slot(s
);
117 pci_bridge_exitfn(d
);
120 static void xio3130_downstream_exitfn(PCIDevice
*d
)
122 PCIESlot
*s
= PCIE_SLOT(d
);
125 pcie_chassis_del_slot(s
);
128 pci_bridge_exitfn(d
);
131 static Property xio3130_downstream_props
[] = {
132 DEFINE_PROP_BIT(COMPAT_PROP_PCP
, PCIDevice
, cap_present
,
133 QEMU_PCIE_SLTCAP_PCP_BITNR
, true),
134 DEFINE_PROP_END_OF_LIST()
137 static const VMStateDescription vmstate_xio3130_downstream
= {
138 .name
= "xio3130-express-downstream-port",
139 .priority
= MIG_PRI_PCI_BUS
,
141 .minimum_version_id
= 1,
142 .post_load
= pcie_cap_slot_post_load
,
143 .fields
= (VMStateField
[]) {
144 VMSTATE_PCI_DEVICE(parent_obj
.parent_obj
.parent_obj
, PCIESlot
),
145 VMSTATE_STRUCT(parent_obj
.parent_obj
.parent_obj
.exp
.aer_log
,
146 PCIESlot
, 0, vmstate_pcie_aer_log
, PCIEAERLog
),
147 VMSTATE_END_OF_LIST()
151 static void xio3130_downstream_class_init(ObjectClass
*klass
, void *data
)
153 DeviceClass
*dc
= DEVICE_CLASS(klass
);
154 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
157 k
->config_write
= xio3130_downstream_write_config
;
158 k
->realize
= xio3130_downstream_realize
;
159 k
->exit
= xio3130_downstream_exitfn
;
160 k
->vendor_id
= PCI_VENDOR_ID_TI
;
161 k
->device_id
= PCI_DEVICE_ID_TI_XIO3130D
;
162 k
->revision
= XIO3130_REVISION
;
163 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
164 dc
->desc
= "TI X3130 Downstream Port of PCI Express Switch";
165 dc
->reset
= xio3130_downstream_reset
;
166 dc
->vmsd
= &vmstate_xio3130_downstream
;
167 dc
->props
= xio3130_downstream_props
;
170 static const TypeInfo xio3130_downstream_info
= {
171 .name
= "xio3130-downstream",
172 .parent
= TYPE_PCIE_SLOT
,
173 .class_init
= xio3130_downstream_class_init
,
174 .interfaces
= (InterfaceInfo
[]) {
175 { INTERFACE_PCIE_DEVICE
},
180 static void xio3130_downstream_register_types(void)
182 type_register_static(&xio3130_downstream_info
);
185 type_init(xio3130_downstream_register_types
)