2 * IMX31 Clock Control Module
4 * Copyright (C) 2012 NICTA
5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
10 * To get the timer frequencies right, we need to emulate at least part of
14 #include "qemu/osdep.h"
15 #include "hw/misc/imx31_ccm.h"
17 #include "qemu/module.h"
19 #define CKIH_FREQ 26000000 /* 26MHz crystal input */
21 #ifndef DEBUG_IMX31_CCM
22 #define DEBUG_IMX31_CCM 0
25 #define DPRINTF(fmt, args...) \
27 if (DEBUG_IMX31_CCM) { \
28 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
33 static const char *imx31_ccm_reg_name(uint32_t reg
)
35 static char unknown
[20];
38 case IMX31_CCM_CCMR_REG
:
40 case IMX31_CCM_PDR0_REG
:
42 case IMX31_CCM_PDR1_REG
:
44 case IMX31_CCM_RCSR_REG
:
46 case IMX31_CCM_MPCTL_REG
:
48 case IMX31_CCM_UPCTL_REG
:
50 case IMX31_CCM_SPCTL_REG
:
52 case IMX31_CCM_COSR_REG
:
54 case IMX31_CCM_CGR0_REG
:
56 case IMX31_CCM_CGR1_REG
:
58 case IMX31_CCM_CGR2_REG
:
60 case IMX31_CCM_WIMR_REG
:
62 case IMX31_CCM_LDC_REG
:
64 case IMX31_CCM_DCVR0_REG
:
66 case IMX31_CCM_DCVR1_REG
:
68 case IMX31_CCM_DCVR2_REG
:
70 case IMX31_CCM_DCVR3_REG
:
72 case IMX31_CCM_LTR0_REG
:
74 case IMX31_CCM_LTR1_REG
:
76 case IMX31_CCM_LTR2_REG
:
78 case IMX31_CCM_LTR3_REG
:
80 case IMX31_CCM_LTBR0_REG
:
82 case IMX31_CCM_LTBR1_REG
:
84 case IMX31_CCM_PMCR0_REG
:
86 case IMX31_CCM_PMCR1_REG
:
88 case IMX31_CCM_PDR2_REG
:
91 sprintf(unknown
, "[%d ?]", reg
);
96 static const VMStateDescription vmstate_imx31_ccm
= {
97 .name
= TYPE_IMX31_CCM
,
99 .minimum_version_id
= 2,
100 .fields
= (VMStateField
[]) {
101 VMSTATE_UINT32_ARRAY(reg
, IMX31CCMState
, IMX31_CCM_MAX_REG
),
102 VMSTATE_END_OF_LIST()
106 static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState
*dev
)
109 IMX31CCMState
*s
= IMX31_CCM(dev
);
111 if ((s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_PRCS
) == 2) {
112 if (s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_FPME
) {
114 if (s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_FPMF
) {
122 DPRINTF("freq = %d\n", freq
);
127 static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState
*dev
)
130 IMX31CCMState
*s
= IMX31_CCM(dev
);
132 freq
= imx_ccm_calc_pll(s
->reg
[IMX31_CCM_MPCTL_REG
],
133 imx31_ccm_get_pll_ref_clk(dev
));
135 DPRINTF("freq = %d\n", freq
);
140 static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState
*dev
)
143 IMX31CCMState
*s
= IMX31_CCM(dev
);
145 if ((s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_MDS
) ||
146 !(s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_MPE
)) {
147 freq
= imx31_ccm_get_pll_ref_clk(dev
);
149 freq
= imx31_ccm_get_mpll_clk(dev
);
152 DPRINTF("freq = %d\n", freq
);
157 static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState
*dev
)
160 IMX31CCMState
*s
= IMX31_CCM(dev
);
162 freq
= imx31_ccm_get_mcu_main_clk(dev
)
163 / (1 + EXTRACT(s
->reg
[IMX31_CCM_PDR0_REG
], MAX
));
165 DPRINTF("freq = %d\n", freq
);
170 static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState
*dev
)
173 IMX31CCMState
*s
= IMX31_CCM(dev
);
175 freq
= imx31_ccm_get_hclk_clk(dev
)
176 / (1 + EXTRACT(s
->reg
[IMX31_CCM_PDR0_REG
], IPG
));
178 DPRINTF("freq = %d\n", freq
);
183 static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState
*dev
, IMXClk clock
)
192 freq
= imx31_ccm_get_ipg_clk(dev
);
198 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: unsupported clock %d\n",
199 TYPE_IMX31_CCM
, __func__
, clock
);
203 DPRINTF("Clock = %d) = %d\n", clock
, freq
);
208 static void imx31_ccm_reset(DeviceState
*dev
)
210 IMX31CCMState
*s
= IMX31_CCM(dev
);
214 memset(s
->reg
, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG
);
216 s
->reg
[IMX31_CCM_CCMR_REG
] = 0x074b0b7d;
217 s
->reg
[IMX31_CCM_PDR0_REG
] = 0xff870b48;
218 s
->reg
[IMX31_CCM_PDR1_REG
] = 0x49fcfe7f;
219 s
->reg
[IMX31_CCM_RCSR_REG
] = 0x007f0000;
220 s
->reg
[IMX31_CCM_MPCTL_REG
] = 0x04001800;
221 s
->reg
[IMX31_CCM_UPCTL_REG
] = 0x04051c03;
222 s
->reg
[IMX31_CCM_SPCTL_REG
] = 0x04043001;
223 s
->reg
[IMX31_CCM_COSR_REG
] = 0x00000280;
224 s
->reg
[IMX31_CCM_CGR0_REG
] = 0xffffffff;
225 s
->reg
[IMX31_CCM_CGR1_REG
] = 0xffffffff;
226 s
->reg
[IMX31_CCM_CGR2_REG
] = 0xffffffff;
227 s
->reg
[IMX31_CCM_WIMR_REG
] = 0xffffffff;
228 s
->reg
[IMX31_CCM_LTR1_REG
] = 0x00004040;
229 s
->reg
[IMX31_CCM_PMCR0_REG
] = 0x80209828;
230 s
->reg
[IMX31_CCM_PMCR1_REG
] = 0x00aa0000;
231 s
->reg
[IMX31_CCM_PDR2_REG
] = 0x00000285;
234 static uint64_t imx31_ccm_read(void *opaque
, hwaddr offset
, unsigned size
)
237 IMX31CCMState
*s
= (IMX31CCMState
*)opaque
;
239 if ((offset
>> 2) < IMX31_CCM_MAX_REG
) {
240 value
= s
->reg
[offset
>> 2];
242 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
243 HWADDR_PRIx
"\n", TYPE_IMX31_CCM
, __func__
, offset
);
246 DPRINTF("reg[%s] => 0x%" PRIx32
"\n", imx31_ccm_reg_name(offset
>> 2),
249 return (uint64_t)value
;
252 static void imx31_ccm_write(void *opaque
, hwaddr offset
, uint64_t value
,
255 IMX31CCMState
*s
= (IMX31CCMState
*)opaque
;
257 DPRINTF("reg[%s] <= 0x%" PRIx32
"\n", imx31_ccm_reg_name(offset
>> 2),
260 switch (offset
>> 2) {
261 case IMX31_CCM_CCMR_REG
:
262 s
->reg
[IMX31_CCM_CCMR_REG
] = CCMR_FPMF
| (value
& 0x3b6fdfff);
264 case IMX31_CCM_PDR0_REG
:
265 s
->reg
[IMX31_CCM_PDR0_REG
] = value
& 0xff9f3fff;
267 case IMX31_CCM_PDR1_REG
:
268 s
->reg
[IMX31_CCM_PDR1_REG
] = value
;
270 case IMX31_CCM_MPCTL_REG
:
271 s
->reg
[IMX31_CCM_MPCTL_REG
] = value
& 0xbfff3fff;
273 case IMX31_CCM_SPCTL_REG
:
274 s
->reg
[IMX31_CCM_SPCTL_REG
] = value
& 0xbfff3fff;
276 case IMX31_CCM_CGR0_REG
:
277 s
->reg
[IMX31_CCM_CGR0_REG
] = value
;
279 case IMX31_CCM_CGR1_REG
:
280 s
->reg
[IMX31_CCM_CGR1_REG
] = value
;
282 case IMX31_CCM_CGR2_REG
:
283 s
->reg
[IMX31_CCM_CGR2_REG
] = value
;
286 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
287 HWADDR_PRIx
"\n", TYPE_IMX31_CCM
, __func__
, offset
);
292 static const struct MemoryRegionOps imx31_ccm_ops
= {
293 .read
= imx31_ccm_read
,
294 .write
= imx31_ccm_write
,
295 .endianness
= DEVICE_NATIVE_ENDIAN
,
298 * Our device would not work correctly if the guest was doing
299 * unaligned access. This might not be a limitation on the real
300 * device but in practice there is no reason for a guest to access
301 * this device unaligned.
303 .min_access_size
= 4,
304 .max_access_size
= 4,
310 static void imx31_ccm_init(Object
*obj
)
312 DeviceState
*dev
= DEVICE(obj
);
313 SysBusDevice
*sd
= SYS_BUS_DEVICE(obj
);
314 IMX31CCMState
*s
= IMX31_CCM(obj
);
316 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &imx31_ccm_ops
, s
,
317 TYPE_IMX31_CCM
, 0x1000);
318 sysbus_init_mmio(sd
, &s
->iomem
);
321 static void imx31_ccm_class_init(ObjectClass
*klass
, void *data
)
323 DeviceClass
*dc
= DEVICE_CLASS(klass
);
324 IMXCCMClass
*ccm
= IMX_CCM_CLASS(klass
);
326 dc
->reset
= imx31_ccm_reset
;
327 dc
->vmsd
= &vmstate_imx31_ccm
;
328 dc
->desc
= "i.MX31 Clock Control Module";
330 ccm
->get_clock_frequency
= imx31_ccm_get_clock_frequency
;
333 static const TypeInfo imx31_ccm_info
= {
334 .name
= TYPE_IMX31_CCM
,
335 .parent
= TYPE_IMX_CCM
,
336 .instance_size
= sizeof(IMX31CCMState
),
337 .instance_init
= imx31_ccm_init
,
338 .class_init
= imx31_ccm_class_init
,
341 static void imx31_ccm_register_types(void)
343 type_register_static(&imx31_ccm_info
);
346 type_init(imx31_ccm_register_types
)