hw/xen/xen_pt.h

   1 #ifndef XEN_PT_H
   2 #define XEN_PT_H
   3
   4 #include "qemu-common.h"
   5 #include "hw/xen/xen_common.h"
   6 #include "hw/pci/pci.h"
   7 #include "xen-host-pci-device.h"
   8
   9 void xen_pt_log(const PCIDevice *d, const char *f, ...) GCC_FMT_ATTR(2, 3);
  10
  11 #define XEN_PT_ERR(d, _f, _a...) xen_pt_log(d, "%s: Error: "_f, __func__, ##_a)
  12
  13 #ifdef XEN_PT_LOGGING_ENABLED
  14 #  define XEN_PT_LOG(d, _f, _a...)  xen_pt_log(d, "%s: " _f, __func__, ##_a)
  15 #  define XEN_PT_WARN(d, _f, _a...) \
  16     xen_pt_log(d, "%s: Warning: "_f, __func__, ##_a)
  17 #else
  18 #  define XEN_PT_LOG(d, _f, _a...)
  19 #  define XEN_PT_WARN(d, _f, _a...)
  20 #endif
  21
  22 #ifdef XEN_PT_DEBUG_PCI_CONFIG_ACCESS
  23 #  define XEN_PT_LOG_CONFIG(d, addr, val, len) \
  24     xen_pt_log(d, "%s: address=0x%04x val=0x%08x len=%d\n", \
  25                __func__, addr, val, len)
  26 #else
  27 #  define XEN_PT_LOG_CONFIG(d, addr, val, len)
  28 #endif
  29
  30
  31 /* Helper */
  32 #define XEN_PFN(x) ((x) >> XC_PAGE_SHIFT)
  33
  34 typedef const struct XenPTRegInfo XenPTRegInfo;
  35 typedef struct XenPTReg XenPTReg;
  36
  37 typedef struct XenPCIPassthroughState XenPCIPassthroughState;
  38
  39 #define TYPE_XEN_PT_DEVICE "xen-pci-passthrough"
  40 #define XEN_PT_DEVICE(obj) \
  41     OBJECT_CHECK(XenPCIPassthroughState, (obj), TYPE_XEN_PT_DEVICE)
  42
  43 uint32_t igd_read_opregion(XenPCIPassthroughState *s);
  44 void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val);
  45
  46 /* function type for config reg */
  47 typedef int (*xen_pt_conf_reg_init)
  48     (XenPCIPassthroughState *, XenPTRegInfo *, uint32_t real_offset,
  49      uint32_t *data);
  50 typedef int (*xen_pt_conf_dword_write)
  51     (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  52      uint32_t *val, uint32_t dev_value, uint32_t valid_mask);
  53 typedef int (*xen_pt_conf_word_write)
  54     (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  55      uint16_t *val, uint16_t dev_value, uint16_t valid_mask);
  56 typedef int (*xen_pt_conf_byte_write)
  57     (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  58      uint8_t *val, uint8_t dev_value, uint8_t valid_mask);
  59 typedef int (*xen_pt_conf_dword_read)
  60     (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  61      uint32_t *val, uint32_t valid_mask);
  62 typedef int (*xen_pt_conf_word_read)
  63     (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  64      uint16_t *val, uint16_t valid_mask);
  65 typedef int (*xen_pt_conf_byte_read)
  66     (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  67      uint8_t *val, uint8_t valid_mask);
  68
  69 #define XEN_PT_BAR_ALLF 0xFFFFFFFF
  70 #define XEN_PT_BAR_UNMAPPED (-1)
  71
  72 #define XEN_PCI_CAP_MAX 48
  73
  74 #define XEN_PCI_INTEL_OPREGION 0xfc
  75
  76 typedef enum {
  77     XEN_PT_GRP_TYPE_HARDWIRED = 0,  /* 0 Hardwired reg group */
  78     XEN_PT_GRP_TYPE_EMU,            /* emul reg group */
  79 } XenPTRegisterGroupType;
  80
  81 typedef enum {
  82     XEN_PT_BAR_FLAG_MEM = 0,        /* Memory type BAR */
  83     XEN_PT_BAR_FLAG_IO,             /* I/O type BAR */
  84     XEN_PT_BAR_FLAG_UPPER,          /* upper 64bit BAR */
  85     XEN_PT_BAR_FLAG_UNUSED,         /* unused BAR */
  86 } XenPTBarFlag;
  87
  88
  89 typedef struct XenPTRegion {
  90     /* BAR flag */
  91     XenPTBarFlag bar_flag;
  92     /* Translation of the emulated address */
  93     union {
  94         uint64_t maddr;
  95         uint64_t pio_base;
  96         uint64_t u;
  97     } access;
  98 } XenPTRegion;
  99
 100 /* XenPTRegInfo declaration
 101  * - only for emulated register (either a part or whole bit).
 102  * - for passthrough register that need special behavior (like interacting with
 103  *   other component), set emu_mask to all 0 and specify r/w func properly.
 104  * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
 105  */
 106
 107 /* emulated register information */
 108 struct XenPTRegInfo {
 109     uint32_t offset;
 110     uint32_t size;
 111     uint32_t init_val;
 112     /* reg reserved field mask (ON:reserved, OFF:defined) */
 113     uint32_t res_mask;
 114     /* reg read only field mask (ON:RO/ROS, OFF:other) */
 115     uint32_t ro_mask;
 116     /* reg emulate field mask (ON:emu, OFF:passthrough) */
 117     uint32_t emu_mask;
 118     xen_pt_conf_reg_init init;
 119     /* read/write function pointer
 120      * for double_word/word/byte size */
 121     union {
 122         struct {
 123             xen_pt_conf_dword_write write;
 124             xen_pt_conf_dword_read read;
 125         } dw;
 126         struct {
 127             xen_pt_conf_word_write write;
 128             xen_pt_conf_word_read read;
 129         } w;
 130         struct {
 131             xen_pt_conf_byte_write write;
 132             xen_pt_conf_byte_read read;
 133         } b;
 134     } u;
 135 };
 136
 137 /* emulated register management */
 138 struct XenPTReg {
 139     QLIST_ENTRY(XenPTReg) entries;
 140     XenPTRegInfo *reg;
 141     union {
 142         uint8_t *byte;
 143         uint16_t *half_word;
 144         uint32_t *word;
 145     } ptr; /* pointer to dev.config. */
 146 };
 147
 148 typedef const struct XenPTRegGroupInfo XenPTRegGroupInfo;
 149
 150 /* emul reg group size initialize method */
 151 typedef int (*xen_pt_reg_size_init_fn)
 152     (XenPCIPassthroughState *, XenPTRegGroupInfo *,
 153      uint32_t base_offset, uint8_t *size);
 154
 155 /* emulated register group information */
 156 struct XenPTRegGroupInfo {
 157     uint8_t grp_id;
 158     XenPTRegisterGroupType grp_type;
 159     uint8_t grp_size;
 160     xen_pt_reg_size_init_fn size_init;
 161     XenPTRegInfo *emu_regs;
 162 };
 163
 164 /* emul register group management table */
 165 typedef struct XenPTRegGroup {
 166     QLIST_ENTRY(XenPTRegGroup) entries;
 167     XenPTRegGroupInfo *reg_grp;
 168     uint32_t base_offset;
 169     uint8_t size;
 170     QLIST_HEAD(, XenPTReg) reg_tbl_list;
 171 } XenPTRegGroup;
 172
 173
 174 #define XEN_PT_UNASSIGNED_PIRQ (-1)
 175 typedef struct XenPTMSI {
 176     uint16_t flags;
 177     uint32_t addr_lo;  /* guest message address */
 178     uint32_t addr_hi;  /* guest message upper address */
 179     uint16_t data;     /* guest message data */
 180     uint32_t ctrl_offset; /* saved control offset */
 181     int pirq;          /* guest pirq corresponding */
 182     bool initialized;  /* when guest MSI is initialized */
 183     bool mapped;       /* when pirq is mapped */
 184 } XenPTMSI;
 185
 186 typedef struct XenPTMSIXEntry {
 187     int pirq;
 188     uint64_t addr;
 189     uint32_t data;
 190     uint32_t vector_ctrl;
 191     bool updated; /* indicate whether MSI ADDR or DATA is updated */
 192     bool warned;  /* avoid issuing (bogus) warning more than once */
 193 } XenPTMSIXEntry;
 194 typedef struct XenPTMSIX {
 195     uint32_t ctrl_offset;
 196     bool enabled;
 197     int total_entries;
 198     int bar_index;
 199     uint64_t table_base;
 200     uint32_t table_offset_adjust; /* page align mmap */
 201     uint64_t mmio_base_addr;
 202     MemoryRegion mmio;
 203     void *phys_iomem_base;
 204     XenPTMSIXEntry msix_entry[0];
 205 } XenPTMSIX;
 206
 207 struct XenPCIPassthroughState {
 208     PCIDevice dev;
 209
 210     PCIHostDeviceAddress hostaddr;
 211     bool is_virtfn;
 212     bool permissive;
 213     bool permissive_warned;
 214     XenHostPCIDevice real_device;
 215     XenPTRegion bases[PCI_NUM_REGIONS]; /* Access regions */
 216     QLIST_HEAD(, XenPTRegGroup) reg_grps;
 217
 218     uint32_t machine_irq;
 219
 220     XenPTMSI *msi;
 221     XenPTMSIX *msix;
 222
 223     MemoryRegion bar[PCI_NUM_REGIONS - 1];
 224     MemoryRegion rom;
 225
 226     MemoryListener memory_listener;
 227     MemoryListener io_listener;
 228     bool listener_set;
 229 };
 230
 231 int xen_pt_config_init(XenPCIPassthroughState *s);
 232 void xen_pt_config_delete(XenPCIPassthroughState *s);
 233 XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address);
 234 XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address);
 235 int xen_pt_bar_offset_to_index(uint32_t offset);
 236
 237 static inline pcibus_t xen_pt_get_emul_size(XenPTBarFlag flag, pcibus_t r_size)
 238 {
 239     /* align resource size (memory type only) */
 240     if (flag == XEN_PT_BAR_FLAG_MEM) {
 241         return (r_size + XC_PAGE_SIZE - 1) & XC_PAGE_MASK;
 242     } else {
 243         return r_size;
 244     }
 245 }
 246
 247 /* INTx */
 248 /* The PCI Local Bus Specification, Rev. 3.0,
 249  * Section 6.2.4 Miscellaneous Registers, pp 223
 250  * outlines 5 valid values for the interrupt pin (intx).
 251  *  0: For devices (or device functions) that don't use an interrupt in
 252  *  1: INTA#
 253  *  2: INTB#
 254  *  3: INTC#
 255  *  4: INTD#
 256  *
 257  * Xen uses the following 4 values for intx
 258  *  0: INTA#
 259  *  1: INTB#
 260  *  2: INTC#
 261  *  3: INTD#
 262  *
 263  * Observing that these list of values are not the same, xen_pt_pci_read_intx()
 264  * uses the following mapping from hw to xen values.
 265  * This seems to reflect the current usage within Xen.
 266  *
 267  * PCI hardware    | Xen | Notes
 268  * ----------------+-----+----------------------------------------------------
 269  * 0               | 0   | No interrupt
 270  * 1               | 0   | INTA#
 271  * 2               | 1   | INTB#
 272  * 3               | 2   | INTC#
 273  * 4               | 3   | INTD#
 274  * any other value | 0   | This should never happen, log error message
 275  */
 276
 277 static inline uint8_t xen_pt_pci_read_intx(XenPCIPassthroughState *s)
 278 {
 279     uint8_t v = 0;
 280     xen_host_pci_get_byte(&s->real_device, PCI_INTERRUPT_PIN, &v);
 281     return v;
 282 }
 283
 284 static inline uint8_t xen_pt_pci_intx(XenPCIPassthroughState *s)
 285 {
 286     uint8_t r_val = xen_pt_pci_read_intx(s);
 287
 288     XEN_PT_LOG(&s->dev, "intx=%i\n", r_val);
 289     if (r_val < 1 || r_val > 4) {
 290         XEN_PT_LOG(&s->dev, "Interrupt pin read from hardware is out of range:"
 291                    " value=%i, acceptable range is 1 - 4\n", r_val);
 292         r_val = 0;
 293     } else {
 294         /* Note that if s.real_device.config_fd is closed we make 0xff. */
 295         r_val -= 1;
 296     }
 297
 298     return r_val;
 299 }
 300
 301 /* MSI/MSI-X */
 302 int xen_pt_msi_setup(XenPCIPassthroughState *s);
 303 int xen_pt_msi_update(XenPCIPassthroughState *d);
 304 void xen_pt_msi_disable(XenPCIPassthroughState *s);
 305
 306 int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base);
 307 void xen_pt_msix_delete(XenPCIPassthroughState *s);
 308 int xen_pt_msix_update(XenPCIPassthroughState *s);
 309 int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index);
 310 void xen_pt_msix_disable(XenPCIPassthroughState *s);
 311
 312 static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
 313 {
 314     return s->msix && s->msix->bar_index == bar;
 315 }
 316
 317 extern void *pci_assign_dev_load_option_rom(PCIDevice *dev,
 318                                             struct Object *owner, int *size,
 319                                             unsigned int domain,
 320                                             unsigned int bus, unsigned int slot,
 321                                             unsigned int function);
 322 extern bool has_igd_gfx_passthru;
 323 static inline bool is_igd_vga_passthrough(XenHostPCIDevice *dev)
 324 {
 325     return (has_igd_gfx_passthru
 326             && ((dev->class_code >> 0x8) == PCI_CLASS_DISPLAY_VGA));
 327 }
 328 int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
 329 int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
 330 int xen_pt_setup_vga(XenPCIPassthroughState *s, XenHostPCIDevice *dev);
 331 #endif /* !XEN_PT_H */