4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "internals.h"
25 #include "disas/disas.h"
26 #include "exec/exec-all.h"
28 #include "tcg-op-gvec.h"
30 #include "qemu/bitops.h"
32 #include "hw/semihosting/semihost.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
41 #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T)
42 #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
43 /* currently all emulated v5 cores are also v5TE, so don't bother */
44 #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
45 #define ENABLE_ARCH_5J dc_isar_feature(jazelle, s)
46 #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
47 #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
48 #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
49 #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7)
50 #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8)
52 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
54 #include "translate.h"
56 #if defined(CONFIG_USER_ONLY)
59 #define IS_USER(s) (s->user)
62 /* We reuse the same 64-bit temporaries for efficiency. */
63 static TCGv_i64 cpu_V0
, cpu_V1
, cpu_M0
;
64 static TCGv_i32 cpu_R
[16];
65 TCGv_i32 cpu_CF
, cpu_NF
, cpu_VF
, cpu_ZF
;
66 TCGv_i64 cpu_exclusive_addr
;
67 TCGv_i64 cpu_exclusive_val
;
69 #include "exec/gen-icount.h"
71 static const char * const regnames
[] =
72 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
73 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
75 /* Function prototypes for gen_ functions calling Neon helpers. */
76 typedef void NeonGenThreeOpEnvFn(TCGv_i32
, TCGv_env
, TCGv_i32
,
78 /* Function prototypes for gen_ functions for fix point conversions */
79 typedef void VFPGenFixPointFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 /* initialize TCG globals. */
82 void arm_translate_init(void)
86 for (i
= 0; i
< 16; i
++) {
87 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
88 offsetof(CPUARMState
, regs
[i
]),
91 cpu_CF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, CF
), "CF");
92 cpu_NF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, NF
), "NF");
93 cpu_VF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, VF
), "VF");
94 cpu_ZF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, ZF
), "ZF");
96 cpu_exclusive_addr
= tcg_global_mem_new_i64(cpu_env
,
97 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
98 cpu_exclusive_val
= tcg_global_mem_new_i64(cpu_env
,
99 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
101 a64_translate_init();
104 /* Flags for the disas_set_da_iss info argument:
105 * lower bits hold the Rt register number, higher bits are flags.
107 typedef enum ISSInfo
{
110 ISSInvalid
= (1 << 5),
111 ISSIsAcqRel
= (1 << 6),
112 ISSIsWrite
= (1 << 7),
113 ISSIs16Bit
= (1 << 8),
116 /* Save the syndrome information for a Data Abort */
117 static void disas_set_da_iss(DisasContext
*s
, MemOp memop
, ISSInfo issinfo
)
120 int sas
= memop
& MO_SIZE
;
121 bool sse
= memop
& MO_SIGN
;
122 bool is_acqrel
= issinfo
& ISSIsAcqRel
;
123 bool is_write
= issinfo
& ISSIsWrite
;
124 bool is_16bit
= issinfo
& ISSIs16Bit
;
125 int srt
= issinfo
& ISSRegMask
;
127 if (issinfo
& ISSInvalid
) {
128 /* Some callsites want to conditionally provide ISS info,
129 * eg "only if this was not a writeback"
135 /* For AArch32, insns where the src/dest is R15 never generate
136 * ISS information. Catching that here saves checking at all
142 syn
= syn_data_abort_with_iss(0, sas
, sse
, srt
, 0, is_acqrel
,
143 0, 0, 0, is_write
, 0, is_16bit
);
144 disas_set_insn_syndrome(s
, syn
);
147 static inline int get_a32_user_mem_index(DisasContext
*s
)
149 /* Return the core mmu_idx to use for A32/T32 "unprivileged load/store"
151 * if PL2, UNPREDICTABLE (we choose to implement as if PL0)
152 * otherwise, access as if at PL0.
154 switch (s
->mmu_idx
) {
155 case ARMMMUIdx_S1E2
: /* this one is UNPREDICTABLE */
156 case ARMMMUIdx_S12NSE0
:
157 case ARMMMUIdx_S12NSE1
:
158 return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0
);
160 case ARMMMUIdx_S1SE0
:
161 case ARMMMUIdx_S1SE1
:
162 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0
);
163 case ARMMMUIdx_MUser
:
164 case ARMMMUIdx_MPriv
:
165 return arm_to_core_mmu_idx(ARMMMUIdx_MUser
);
166 case ARMMMUIdx_MUserNegPri
:
167 case ARMMMUIdx_MPrivNegPri
:
168 return arm_to_core_mmu_idx(ARMMMUIdx_MUserNegPri
);
169 case ARMMMUIdx_MSUser
:
170 case ARMMMUIdx_MSPriv
:
171 return arm_to_core_mmu_idx(ARMMMUIdx_MSUser
);
172 case ARMMMUIdx_MSUserNegPri
:
173 case ARMMMUIdx_MSPrivNegPri
:
174 return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri
);
177 g_assert_not_reached();
181 static inline TCGv_i32
load_cpu_offset(int offset
)
183 TCGv_i32 tmp
= tcg_temp_new_i32();
184 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
188 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
190 static inline void store_cpu_offset(TCGv_i32 var
, int offset
)
192 tcg_gen_st_i32(var
, cpu_env
, offset
);
193 tcg_temp_free_i32(var
);
196 #define store_cpu_field(var, name) \
197 store_cpu_offset(var, offsetof(CPUARMState, name))
199 /* The architectural value of PC. */
200 static uint32_t read_pc(DisasContext
*s
)
202 return s
->pc_curr
+ (s
->thumb
? 4 : 8);
205 /* Set a variable to the value of a CPU register. */
206 static void load_reg_var(DisasContext
*s
, TCGv_i32 var
, int reg
)
209 tcg_gen_movi_i32(var
, read_pc(s
));
211 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
215 /* Create a new temporary and set it to the value of a CPU register. */
216 static inline TCGv_i32
load_reg(DisasContext
*s
, int reg
)
218 TCGv_i32 tmp
= tcg_temp_new_i32();
219 load_reg_var(s
, tmp
, reg
);
224 * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4).
225 * This is used for load/store for which use of PC implies (literal),
226 * or ADD that implies ADR.
228 static TCGv_i32
add_reg_for_lit(DisasContext
*s
, int reg
, int ofs
)
230 TCGv_i32 tmp
= tcg_temp_new_i32();
233 tcg_gen_movi_i32(tmp
, (read_pc(s
) & ~3) + ofs
);
235 tcg_gen_addi_i32(tmp
, cpu_R
[reg
], ofs
);
240 /* Set a CPU register. The source must be a temporary and will be
242 static void store_reg(DisasContext
*s
, int reg
, TCGv_i32 var
)
245 /* In Thumb mode, we must ignore bit 0.
246 * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0]
247 * are not 0b00, but for ARMv6 and above, we must ignore bits [1:0].
248 * We choose to ignore [1:0] in ARM mode for all architecture versions.
250 tcg_gen_andi_i32(var
, var
, s
->thumb
? ~1 : ~3);
251 s
->base
.is_jmp
= DISAS_JUMP
;
253 tcg_gen_mov_i32(cpu_R
[reg
], var
);
254 tcg_temp_free_i32(var
);
258 * Variant of store_reg which applies v8M stack-limit checks before updating
259 * SP. If the check fails this will result in an exception being taken.
260 * We disable the stack checks for CONFIG_USER_ONLY because we have
261 * no idea what the stack limits should be in that case.
262 * If stack checking is not being done this just acts like store_reg().
264 static void store_sp_checked(DisasContext
*s
, TCGv_i32 var
)
266 #ifndef CONFIG_USER_ONLY
267 if (s
->v8m_stackcheck
) {
268 gen_helper_v8m_stackcheck(cpu_env
, var
);
271 store_reg(s
, 13, var
);
274 /* Value extensions. */
275 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
276 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
277 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
278 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
280 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
281 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
284 static inline void gen_set_cpsr(TCGv_i32 var
, uint32_t mask
)
286 TCGv_i32 tmp_mask
= tcg_const_i32(mask
);
287 gen_helper_cpsr_write(cpu_env
, var
, tmp_mask
);
288 tcg_temp_free_i32(tmp_mask
);
290 /* Set NZCV flags from the high 4 bits of var. */
291 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
293 static void gen_exception_internal(int excp
)
295 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
297 assert(excp_is_internal(excp
));
298 gen_helper_exception_internal(cpu_env
, tcg_excp
);
299 tcg_temp_free_i32(tcg_excp
);
302 static void gen_step_complete_exception(DisasContext
*s
)
304 /* We just completed step of an insn. Move from Active-not-pending
305 * to Active-pending, and then also take the swstep exception.
306 * This corresponds to making the (IMPDEF) choice to prioritize
307 * swstep exceptions over asynchronous exceptions taken to an exception
308 * level where debug is disabled. This choice has the advantage that
309 * we do not need to maintain internal state corresponding to the
310 * ISV/EX syndrome bits between completion of the step and generation
311 * of the exception, and our syndrome information is always correct.
314 gen_swstep_exception(s
, 1, s
->is_ldex
);
315 s
->base
.is_jmp
= DISAS_NORETURN
;
318 static void gen_singlestep_exception(DisasContext
*s
)
320 /* Generate the right kind of exception for singlestep, which is
321 * either the architectural singlestep or EXCP_DEBUG for QEMU's
322 * gdb singlestepping.
325 gen_step_complete_exception(s
);
327 gen_exception_internal(EXCP_DEBUG
);
331 static inline bool is_singlestepping(DisasContext
*s
)
333 /* Return true if we are singlestepping either because of
334 * architectural singlestep or QEMU gdbstub singlestep. This does
335 * not include the command line '-singlestep' mode which is rather
336 * misnamed as it only means "one instruction per TB" and doesn't
337 * affect the code we generate.
339 return s
->base
.singlestep_enabled
|| s
->ss_active
;
342 static void gen_smul_dual(TCGv_i32 a
, TCGv_i32 b
)
344 TCGv_i32 tmp1
= tcg_temp_new_i32();
345 TCGv_i32 tmp2
= tcg_temp_new_i32();
346 tcg_gen_ext16s_i32(tmp1
, a
);
347 tcg_gen_ext16s_i32(tmp2
, b
);
348 tcg_gen_mul_i32(tmp1
, tmp1
, tmp2
);
349 tcg_temp_free_i32(tmp2
);
350 tcg_gen_sari_i32(a
, a
, 16);
351 tcg_gen_sari_i32(b
, b
, 16);
352 tcg_gen_mul_i32(b
, b
, a
);
353 tcg_gen_mov_i32(a
, tmp1
);
354 tcg_temp_free_i32(tmp1
);
357 /* Byteswap each halfword. */
358 static void gen_rev16(TCGv_i32 var
)
360 TCGv_i32 tmp
= tcg_temp_new_i32();
361 TCGv_i32 mask
= tcg_const_i32(0x00ff00ff);
362 tcg_gen_shri_i32(tmp
, var
, 8);
363 tcg_gen_and_i32(tmp
, tmp
, mask
);
364 tcg_gen_and_i32(var
, var
, mask
);
365 tcg_gen_shli_i32(var
, var
, 8);
366 tcg_gen_or_i32(var
, var
, tmp
);
367 tcg_temp_free_i32(mask
);
368 tcg_temp_free_i32(tmp
);
371 /* Byteswap low halfword and sign extend. */
372 static void gen_revsh(TCGv_i32 var
)
374 tcg_gen_ext16u_i32(var
, var
);
375 tcg_gen_bswap16_i32(var
, var
);
376 tcg_gen_ext16s_i32(var
, var
);
379 /* 32x32->64 multiply. Marks inputs as dead. */
380 static TCGv_i64
gen_mulu_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
382 TCGv_i32 lo
= tcg_temp_new_i32();
383 TCGv_i32 hi
= tcg_temp_new_i32();
386 tcg_gen_mulu2_i32(lo
, hi
, a
, b
);
387 tcg_temp_free_i32(a
);
388 tcg_temp_free_i32(b
);
390 ret
= tcg_temp_new_i64();
391 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
392 tcg_temp_free_i32(lo
);
393 tcg_temp_free_i32(hi
);
398 static TCGv_i64
gen_muls_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
400 TCGv_i32 lo
= tcg_temp_new_i32();
401 TCGv_i32 hi
= tcg_temp_new_i32();
404 tcg_gen_muls2_i32(lo
, hi
, a
, b
);
405 tcg_temp_free_i32(a
);
406 tcg_temp_free_i32(b
);
408 ret
= tcg_temp_new_i64();
409 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
410 tcg_temp_free_i32(lo
);
411 tcg_temp_free_i32(hi
);
416 /* Swap low and high halfwords. */
417 static void gen_swap_half(TCGv_i32 var
)
419 tcg_gen_rotri_i32(var
, var
, 16);
422 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
423 tmp = (t0 ^ t1) & 0x8000;
426 t0 = (t0 + t1) ^ tmp;
429 static void gen_add16(TCGv_i32 t0
, TCGv_i32 t1
)
431 TCGv_i32 tmp
= tcg_temp_new_i32();
432 tcg_gen_xor_i32(tmp
, t0
, t1
);
433 tcg_gen_andi_i32(tmp
, tmp
, 0x8000);
434 tcg_gen_andi_i32(t0
, t0
, ~0x8000);
435 tcg_gen_andi_i32(t1
, t1
, ~0x8000);
436 tcg_gen_add_i32(t0
, t0
, t1
);
437 tcg_gen_xor_i32(t0
, t0
, tmp
);
438 tcg_temp_free_i32(tmp
);
439 tcg_temp_free_i32(t1
);
442 /* Set CF to the top bit of var. */
443 static void gen_set_CF_bit31(TCGv_i32 var
)
445 tcg_gen_shri_i32(cpu_CF
, var
, 31);
448 /* Set N and Z flags from var. */
449 static inline void gen_logic_CC(TCGv_i32 var
)
451 tcg_gen_mov_i32(cpu_NF
, var
);
452 tcg_gen_mov_i32(cpu_ZF
, var
);
456 static void gen_adc(TCGv_i32 t0
, TCGv_i32 t1
)
458 tcg_gen_add_i32(t0
, t0
, t1
);
459 tcg_gen_add_i32(t0
, t0
, cpu_CF
);
462 /* dest = T0 + T1 + CF. */
463 static void gen_add_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
465 tcg_gen_add_i32(dest
, t0
, t1
);
466 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
469 /* dest = T0 - T1 + CF - 1. */
470 static void gen_sub_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
472 tcg_gen_sub_i32(dest
, t0
, t1
);
473 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
474 tcg_gen_subi_i32(dest
, dest
, 1);
477 /* dest = T0 + T1. Compute C, N, V and Z flags */
478 static void gen_add_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
480 TCGv_i32 tmp
= tcg_temp_new_i32();
481 tcg_gen_movi_i32(tmp
, 0);
482 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, t1
, tmp
);
483 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
484 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
485 tcg_gen_xor_i32(tmp
, t0
, t1
);
486 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
487 tcg_temp_free_i32(tmp
);
488 tcg_gen_mov_i32(dest
, cpu_NF
);
491 /* dest = T0 + T1 + CF. Compute C, N, V and Z flags */
492 static void gen_adc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
494 TCGv_i32 tmp
= tcg_temp_new_i32();
495 if (TCG_TARGET_HAS_add2_i32
) {
496 tcg_gen_movi_i32(tmp
, 0);
497 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, cpu_CF
, tmp
);
498 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1
, tmp
);
500 TCGv_i64 q0
= tcg_temp_new_i64();
501 TCGv_i64 q1
= tcg_temp_new_i64();
502 tcg_gen_extu_i32_i64(q0
, t0
);
503 tcg_gen_extu_i32_i64(q1
, t1
);
504 tcg_gen_add_i64(q0
, q0
, q1
);
505 tcg_gen_extu_i32_i64(q1
, cpu_CF
);
506 tcg_gen_add_i64(q0
, q0
, q1
);
507 tcg_gen_extr_i64_i32(cpu_NF
, cpu_CF
, q0
);
508 tcg_temp_free_i64(q0
);
509 tcg_temp_free_i64(q1
);
511 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
512 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
513 tcg_gen_xor_i32(tmp
, t0
, t1
);
514 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
515 tcg_temp_free_i32(tmp
);
516 tcg_gen_mov_i32(dest
, cpu_NF
);
519 /* dest = T0 - T1. Compute C, N, V and Z flags */
520 static void gen_sub_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
523 tcg_gen_sub_i32(cpu_NF
, t0
, t1
);
524 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
525 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0
, t1
);
526 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
527 tmp
= tcg_temp_new_i32();
528 tcg_gen_xor_i32(tmp
, t0
, t1
);
529 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
530 tcg_temp_free_i32(tmp
);
531 tcg_gen_mov_i32(dest
, cpu_NF
);
534 /* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */
535 static void gen_sbc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
537 TCGv_i32 tmp
= tcg_temp_new_i32();
538 tcg_gen_not_i32(tmp
, t1
);
539 gen_adc_CC(dest
, t0
, tmp
);
540 tcg_temp_free_i32(tmp
);
543 #define GEN_SHIFT(name) \
544 static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) \
546 TCGv_i32 tmp1, tmp2, tmp3; \
547 tmp1 = tcg_temp_new_i32(); \
548 tcg_gen_andi_i32(tmp1, t1, 0xff); \
549 tmp2 = tcg_const_i32(0); \
550 tmp3 = tcg_const_i32(0x1f); \
551 tcg_gen_movcond_i32(TCG_COND_GTU, tmp2, tmp1, tmp3, tmp2, t0); \
552 tcg_temp_free_i32(tmp3); \
553 tcg_gen_andi_i32(tmp1, tmp1, 0x1f); \
554 tcg_gen_##name##_i32(dest, tmp2, tmp1); \
555 tcg_temp_free_i32(tmp2); \
556 tcg_temp_free_i32(tmp1); \
562 static void gen_sar(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
565 tmp1
= tcg_temp_new_i32();
566 tcg_gen_andi_i32(tmp1
, t1
, 0xff);
567 tmp2
= tcg_const_i32(0x1f);
568 tcg_gen_movcond_i32(TCG_COND_GTU
, tmp1
, tmp1
, tmp2
, tmp2
, tmp1
);
569 tcg_temp_free_i32(tmp2
);
570 tcg_gen_sar_i32(dest
, t0
, tmp1
);
571 tcg_temp_free_i32(tmp1
);
574 static void shifter_out_im(TCGv_i32 var
, int shift
)
576 tcg_gen_extract_i32(cpu_CF
, var
, shift
, 1);
579 /* Shift by immediate. Includes special handling for shift == 0. */
580 static inline void gen_arm_shift_im(TCGv_i32 var
, int shiftop
,
581 int shift
, int flags
)
587 shifter_out_im(var
, 32 - shift
);
588 tcg_gen_shli_i32(var
, var
, shift
);
594 tcg_gen_shri_i32(cpu_CF
, var
, 31);
596 tcg_gen_movi_i32(var
, 0);
599 shifter_out_im(var
, shift
- 1);
600 tcg_gen_shri_i32(var
, var
, shift
);
607 shifter_out_im(var
, shift
- 1);
610 tcg_gen_sari_i32(var
, var
, shift
);
612 case 3: /* ROR/RRX */
615 shifter_out_im(var
, shift
- 1);
616 tcg_gen_rotri_i32(var
, var
, shift
); break;
618 TCGv_i32 tmp
= tcg_temp_new_i32();
619 tcg_gen_shli_i32(tmp
, cpu_CF
, 31);
621 shifter_out_im(var
, 0);
622 tcg_gen_shri_i32(var
, var
, 1);
623 tcg_gen_or_i32(var
, var
, tmp
);
624 tcg_temp_free_i32(tmp
);
629 static inline void gen_arm_shift_reg(TCGv_i32 var
, int shiftop
,
630 TCGv_i32 shift
, int flags
)
634 case 0: gen_helper_shl_cc(var
, cpu_env
, var
, shift
); break;
635 case 1: gen_helper_shr_cc(var
, cpu_env
, var
, shift
); break;
636 case 2: gen_helper_sar_cc(var
, cpu_env
, var
, shift
); break;
637 case 3: gen_helper_ror_cc(var
, cpu_env
, var
, shift
); break;
642 gen_shl(var
, var
, shift
);
645 gen_shr(var
, var
, shift
);
648 gen_sar(var
, var
, shift
);
650 case 3: tcg_gen_andi_i32(shift
, shift
, 0x1f);
651 tcg_gen_rotr_i32(var
, var
, shift
); break;
654 tcg_temp_free_i32(shift
);
657 #define PAS_OP(pfx) \
659 case 0: gen_pas_helper(glue(pfx,add16)); break; \
660 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
661 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
662 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
663 case 4: gen_pas_helper(glue(pfx,add8)); break; \
664 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
666 static void gen_arm_parallel_addsub(int op1
, int op2
, TCGv_i32 a
, TCGv_i32 b
)
671 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
673 tmp
= tcg_temp_new_ptr();
674 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
676 tcg_temp_free_ptr(tmp
);
679 tmp
= tcg_temp_new_ptr();
680 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
682 tcg_temp_free_ptr(tmp
);
684 #undef gen_pas_helper
685 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
698 #undef gen_pas_helper
703 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
704 #define PAS_OP(pfx) \
706 case 0: gen_pas_helper(glue(pfx,add8)); break; \
707 case 1: gen_pas_helper(glue(pfx,add16)); break; \
708 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
709 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
710 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
711 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
713 static void gen_thumb2_parallel_addsub(int op1
, int op2
, TCGv_i32 a
, TCGv_i32 b
)
718 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
720 tmp
= tcg_temp_new_ptr();
721 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
723 tcg_temp_free_ptr(tmp
);
726 tmp
= tcg_temp_new_ptr();
727 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
729 tcg_temp_free_ptr(tmp
);
731 #undef gen_pas_helper
732 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
745 #undef gen_pas_helper
751 * Generate a conditional based on ARM condition code cc.
752 * This is common between ARM and Aarch64 targets.
754 void arm_test_cc(DisasCompare
*cmp
, int cc
)
785 case 8: /* hi: C && !Z */
786 case 9: /* ls: !C || Z -> !(C && !Z) */
788 value
= tcg_temp_new_i32();
790 /* CF is 1 for C, so -CF is an all-bits-set mask for C;
791 ZF is non-zero for !Z; so AND the two subexpressions. */
792 tcg_gen_neg_i32(value
, cpu_CF
);
793 tcg_gen_and_i32(value
, value
, cpu_ZF
);
796 case 10: /* ge: N == V -> N ^ V == 0 */
797 case 11: /* lt: N != V -> N ^ V != 0 */
798 /* Since we're only interested in the sign bit, == 0 is >= 0. */
800 value
= tcg_temp_new_i32();
802 tcg_gen_xor_i32(value
, cpu_VF
, cpu_NF
);
805 case 12: /* gt: !Z && N == V */
806 case 13: /* le: Z || N != V */
808 value
= tcg_temp_new_i32();
810 /* (N == V) is equal to the sign bit of ~(NF ^ VF). Propagate
811 * the sign bit then AND with ZF to yield the result. */
812 tcg_gen_xor_i32(value
, cpu_VF
, cpu_NF
);
813 tcg_gen_sari_i32(value
, value
, 31);
814 tcg_gen_andc_i32(value
, cpu_ZF
, value
);
817 case 14: /* always */
818 case 15: /* always */
819 /* Use the ALWAYS condition, which will fold early.
820 * It doesn't matter what we use for the value. */
821 cond
= TCG_COND_ALWAYS
;
826 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
831 cond
= tcg_invert_cond(cond
);
837 cmp
->value_global
= global
;
840 void arm_free_cc(DisasCompare
*cmp
)
842 if (!cmp
->value_global
) {
843 tcg_temp_free_i32(cmp
->value
);
847 void arm_jump_cc(DisasCompare
*cmp
, TCGLabel
*label
)
849 tcg_gen_brcondi_i32(cmp
->cond
, cmp
->value
, 0, label
);
852 void arm_gen_test_cc(int cc
, TCGLabel
*label
)
855 arm_test_cc(&cmp
, cc
);
856 arm_jump_cc(&cmp
, label
);
860 static const uint8_t table_logic_cc
[16] = {
879 static inline void gen_set_condexec(DisasContext
*s
)
881 if (s
->condexec_mask
) {
882 uint32_t val
= (s
->condexec_cond
<< 4) | (s
->condexec_mask
>> 1);
883 TCGv_i32 tmp
= tcg_temp_new_i32();
884 tcg_gen_movi_i32(tmp
, val
);
885 store_cpu_field(tmp
, condexec_bits
);
889 static inline void gen_set_pc_im(DisasContext
*s
, target_ulong val
)
891 tcg_gen_movi_i32(cpu_R
[15], val
);
894 /* Set PC and Thumb state from an immediate address. */
895 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
899 s
->base
.is_jmp
= DISAS_JUMP
;
900 if (s
->thumb
!= (addr
& 1)) {
901 tmp
= tcg_temp_new_i32();
902 tcg_gen_movi_i32(tmp
, addr
& 1);
903 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUARMState
, thumb
));
904 tcg_temp_free_i32(tmp
);
906 tcg_gen_movi_i32(cpu_R
[15], addr
& ~1);
909 /* Set PC and Thumb state from var. var is marked as dead. */
910 static inline void gen_bx(DisasContext
*s
, TCGv_i32 var
)
912 s
->base
.is_jmp
= DISAS_JUMP
;
913 tcg_gen_andi_i32(cpu_R
[15], var
, ~1);
914 tcg_gen_andi_i32(var
, var
, 1);
915 store_cpu_field(var
, thumb
);
919 * Set PC and Thumb state from var. var is marked as dead.
920 * For M-profile CPUs, include logic to detect exception-return
921 * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC,
922 * and BX reg, and no others, and happens only for code in Handler mode.
923 * The Security Extension also requires us to check for the FNC_RETURN
924 * which signals a function return from non-secure state; this can happen
925 * in both Handler and Thread mode.
926 * To avoid having to do multiple comparisons in inline generated code,
927 * we make the check we do here loose, so it will match for EXC_RETURN
928 * in Thread mode. For system emulation do_v7m_exception_exit() checks
929 * for these spurious cases and returns without doing anything (giving
930 * the same behaviour as for a branch to a non-magic address).
932 * In linux-user mode it is unclear what the right behaviour for an
933 * attempted FNC_RETURN should be, because in real hardware this will go
934 * directly to Secure code (ie not the Linux kernel) which will then treat
935 * the error in any way it chooses. For QEMU we opt to make the FNC_RETURN
936 * attempt behave the way it would on a CPU without the security extension,
937 * which is to say "like a normal branch". That means we can simply treat
938 * all branches as normal with no magic address behaviour.
940 static inline void gen_bx_excret(DisasContext
*s
, TCGv_i32 var
)
942 /* Generate the same code here as for a simple bx, but flag via
943 * s->base.is_jmp that we need to do the rest of the work later.
946 #ifndef CONFIG_USER_ONLY
947 if (arm_dc_feature(s
, ARM_FEATURE_M_SECURITY
) ||
948 (s
->v7m_handler_mode
&& arm_dc_feature(s
, ARM_FEATURE_M
))) {
949 s
->base
.is_jmp
= DISAS_BX_EXCRET
;
954 static inline void gen_bx_excret_final_code(DisasContext
*s
)
956 /* Generate the code to finish possible exception return and end the TB */
957 TCGLabel
*excret_label
= gen_new_label();
960 if (arm_dc_feature(s
, ARM_FEATURE_M_SECURITY
)) {
961 /* Covers FNC_RETURN and EXC_RETURN magic */
962 min_magic
= FNC_RETURN_MIN_MAGIC
;
964 /* EXC_RETURN magic only */
965 min_magic
= EXC_RETURN_MIN_MAGIC
;
968 /* Is the new PC value in the magic range indicating exception return? */
969 tcg_gen_brcondi_i32(TCG_COND_GEU
, cpu_R
[15], min_magic
, excret_label
);
970 /* No: end the TB as we would for a DISAS_JMP */
971 if (is_singlestepping(s
)) {
972 gen_singlestep_exception(s
);
974 tcg_gen_exit_tb(NULL
, 0);
976 gen_set_label(excret_label
);
977 /* Yes: this is an exception return.
978 * At this point in runtime env->regs[15] and env->thumb will hold
979 * the exception-return magic number, which do_v7m_exception_exit()
980 * will read. Nothing else will be able to see those values because
981 * the cpu-exec main loop guarantees that we will always go straight
982 * from raising the exception to the exception-handling code.
984 * gen_ss_advance(s) does nothing on M profile currently but
985 * calling it is conceptually the right thing as we have executed
986 * this instruction (compare SWI, HVC, SMC handling).
989 gen_exception_internal(EXCP_EXCEPTION_EXIT
);
992 static inline void gen_bxns(DisasContext
*s
, int rm
)
994 TCGv_i32 var
= load_reg(s
, rm
);
996 /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
997 * we need to sync state before calling it, but:
998 * - we don't need to do gen_set_pc_im() because the bxns helper will
999 * always set the PC itself
1000 * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE
1001 * unless it's outside an IT block or the last insn in an IT block,
1002 * so we know that condexec == 0 (already set at the top of the TB)
1003 * is correct in the non-UNPREDICTABLE cases, and we can choose
1004 * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise.
1006 gen_helper_v7m_bxns(cpu_env
, var
);
1007 tcg_temp_free_i32(var
);
1008 s
->base
.is_jmp
= DISAS_EXIT
;
1011 static inline void gen_blxns(DisasContext
*s
, int rm
)
1013 TCGv_i32 var
= load_reg(s
, rm
);
1015 /* We don't need to sync condexec state, for the same reason as bxns.
1016 * We do however need to set the PC, because the blxns helper reads it.
1017 * The blxns helper may throw an exception.
1019 gen_set_pc_im(s
, s
->base
.pc_next
);
1020 gen_helper_v7m_blxns(cpu_env
, var
);
1021 tcg_temp_free_i32(var
);
1022 s
->base
.is_jmp
= DISAS_EXIT
;
1025 /* Variant of store_reg which uses branch&exchange logic when storing
1026 to r15 in ARM architecture v7 and above. The source must be a temporary
1027 and will be marked as dead. */
1028 static inline void store_reg_bx(DisasContext
*s
, int reg
, TCGv_i32 var
)
1030 if (reg
== 15 && ENABLE_ARCH_7
) {
1033 store_reg(s
, reg
, var
);
1037 /* Variant of store_reg which uses branch&exchange logic when storing
1038 * to r15 in ARM architecture v5T and above. This is used for storing
1039 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
1040 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
1041 static inline void store_reg_from_load(DisasContext
*s
, int reg
, TCGv_i32 var
)
1043 if (reg
== 15 && ENABLE_ARCH_5
) {
1044 gen_bx_excret(s
, var
);
1046 store_reg(s
, reg
, var
);
1050 #ifdef CONFIG_USER_ONLY
1051 #define IS_USER_ONLY 1
1053 #define IS_USER_ONLY 0
1056 /* Abstractions of "generate code to do a guest load/store for
1057 * AArch32", where a vaddr is always 32 bits (and is zero
1058 * extended if we're a 64 bit core) and data is also
1059 * 32 bits unless specifically doing a 64 bit access.
1060 * These functions work like tcg_gen_qemu_{ld,st}* except
1061 * that the address argument is TCGv_i32 rather than TCGv.
1064 static inline TCGv
gen_aa32_addr(DisasContext
*s
, TCGv_i32 a32
, MemOp op
)
1066 TCGv addr
= tcg_temp_new();
1067 tcg_gen_extu_i32_tl(addr
, a32
);
1069 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1070 if (!IS_USER_ONLY
&& s
->sctlr_b
&& (op
& MO_SIZE
) < MO_32
) {
1071 tcg_gen_xori_tl(addr
, addr
, 4 - (1 << (op
& MO_SIZE
)));
1076 static void gen_aa32_ld_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
1077 int index
, MemOp opc
)
1081 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
1082 !arm_dc_feature(s
, ARM_FEATURE_M_MAIN
)) {
1086 addr
= gen_aa32_addr(s
, a32
, opc
);
1087 tcg_gen_qemu_ld_i32(val
, addr
, index
, opc
);
1088 tcg_temp_free(addr
);
1091 static void gen_aa32_st_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
1092 int index
, MemOp opc
)
1096 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
1097 !arm_dc_feature(s
, ARM_FEATURE_M_MAIN
)) {
1101 addr
= gen_aa32_addr(s
, a32
, opc
);
1102 tcg_gen_qemu_st_i32(val
, addr
, index
, opc
);
1103 tcg_temp_free(addr
);
1106 #define DO_GEN_LD(SUFF, OPC) \
1107 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
1108 TCGv_i32 a32, int index) \
1110 gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
1112 static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \
1114 TCGv_i32 a32, int index, \
1117 gen_aa32_ld##SUFF(s, val, a32, index); \
1118 disas_set_da_iss(s, OPC, issinfo); \
1121 #define DO_GEN_ST(SUFF, OPC) \
1122 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
1123 TCGv_i32 a32, int index) \
1125 gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
1127 static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \
1129 TCGv_i32 a32, int index, \
1132 gen_aa32_st##SUFF(s, val, a32, index); \
1133 disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \
1136 static inline void gen_aa32_frob64(DisasContext
*s
, TCGv_i64 val
)
1138 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1139 if (!IS_USER_ONLY
&& s
->sctlr_b
) {
1140 tcg_gen_rotri_i64(val
, val
, 32);
1144 static void gen_aa32_ld_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
1145 int index
, MemOp opc
)
1147 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
1148 tcg_gen_qemu_ld_i64(val
, addr
, index
, opc
);
1149 gen_aa32_frob64(s
, val
);
1150 tcg_temp_free(addr
);
1153 static inline void gen_aa32_ld64(DisasContext
*s
, TCGv_i64 val
,
1154 TCGv_i32 a32
, int index
)
1156 gen_aa32_ld_i64(s
, val
, a32
, index
, MO_Q
| s
->be_data
);
1159 static void gen_aa32_st_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
1160 int index
, MemOp opc
)
1162 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
1164 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1165 if (!IS_USER_ONLY
&& s
->sctlr_b
) {
1166 TCGv_i64 tmp
= tcg_temp_new_i64();
1167 tcg_gen_rotri_i64(tmp
, val
, 32);
1168 tcg_gen_qemu_st_i64(tmp
, addr
, index
, opc
);
1169 tcg_temp_free_i64(tmp
);
1171 tcg_gen_qemu_st_i64(val
, addr
, index
, opc
);
1173 tcg_temp_free(addr
);
1176 static inline void gen_aa32_st64(DisasContext
*s
, TCGv_i64 val
,
1177 TCGv_i32 a32
, int index
)
1179 gen_aa32_st_i64(s
, val
, a32
, index
, MO_Q
| s
->be_data
);
1182 DO_GEN_LD(8s
, MO_SB
)
1183 DO_GEN_LD(8u, MO_UB
)
1184 DO_GEN_LD(16s
, MO_SW
)
1185 DO_GEN_LD(16u, MO_UW
)
1186 DO_GEN_LD(32u, MO_UL
)
1188 DO_GEN_ST(16, MO_UW
)
1189 DO_GEN_ST(32, MO_UL
)
1191 static inline void gen_hvc(DisasContext
*s
, int imm16
)
1193 /* The pre HVC helper handles cases when HVC gets trapped
1194 * as an undefined insn by runtime configuration (ie before
1195 * the insn really executes).
1197 gen_set_pc_im(s
, s
->pc_curr
);
1198 gen_helper_pre_hvc(cpu_env
);
1199 /* Otherwise we will treat this as a real exception which
1200 * happens after execution of the insn. (The distinction matters
1201 * for the PC value reported to the exception handler and also
1202 * for single stepping.)
1205 gen_set_pc_im(s
, s
->base
.pc_next
);
1206 s
->base
.is_jmp
= DISAS_HVC
;
1209 static inline void gen_smc(DisasContext
*s
)
1211 /* As with HVC, we may take an exception either before or after
1212 * the insn executes.
1216 gen_set_pc_im(s
, s
->pc_curr
);
1217 tmp
= tcg_const_i32(syn_aa32_smc());
1218 gen_helper_pre_smc(cpu_env
, tmp
);
1219 tcg_temp_free_i32(tmp
);
1220 gen_set_pc_im(s
, s
->base
.pc_next
);
1221 s
->base
.is_jmp
= DISAS_SMC
;
1224 static void gen_exception_internal_insn(DisasContext
*s
, uint32_t pc
, int excp
)
1226 gen_set_condexec(s
);
1227 gen_set_pc_im(s
, pc
);
1228 gen_exception_internal(excp
);
1229 s
->base
.is_jmp
= DISAS_NORETURN
;
1232 static void gen_exception_insn(DisasContext
*s
, uint32_t pc
, int excp
,
1233 int syn
, uint32_t target_el
)
1235 gen_set_condexec(s
);
1236 gen_set_pc_im(s
, pc
);
1237 gen_exception(excp
, syn
, target_el
);
1238 s
->base
.is_jmp
= DISAS_NORETURN
;
1241 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syn
)
1245 gen_set_condexec(s
);
1246 gen_set_pc_im(s
, s
->pc_curr
);
1247 tcg_syn
= tcg_const_i32(syn
);
1248 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
1249 tcg_temp_free_i32(tcg_syn
);
1250 s
->base
.is_jmp
= DISAS_NORETURN
;
1253 static void unallocated_encoding(DisasContext
*s
)
1255 /* Unallocated and reserved encodings are uncategorized */
1256 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
1257 default_exception_el(s
));
1260 /* Force a TB lookup after an instruction that changes the CPU state. */
1261 static inline void gen_lookup_tb(DisasContext
*s
)
1263 tcg_gen_movi_i32(cpu_R
[15], s
->base
.pc_next
);
1264 s
->base
.is_jmp
= DISAS_EXIT
;
1267 static inline void gen_hlt(DisasContext
*s
, int imm
)
1269 /* HLT. This has two purposes.
1270 * Architecturally, it is an external halting debug instruction.
1271 * Since QEMU doesn't implement external debug, we treat this as
1272 * it is required for halting debug disabled: it will UNDEF.
1273 * Secondly, "HLT 0x3C" is a T32 semihosting trap instruction,
1274 * and "HLT 0xF000" is an A32 semihosting syscall. These traps
1275 * must trigger semihosting even for ARMv7 and earlier, where
1276 * HLT was an undefined encoding.
1277 * In system mode, we don't allow userspace access to
1278 * semihosting, to provide some semblance of security
1279 * (and for consistency with our 32-bit semihosting).
1281 if (semihosting_enabled() &&
1282 #ifndef CONFIG_USER_ONLY
1283 s
->current_el
!= 0 &&
1285 (imm
== (s
->thumb
? 0x3c : 0xf000))) {
1286 gen_exception_internal_insn(s
, s
->base
.pc_next
, EXCP_SEMIHOST
);
1290 unallocated_encoding(s
);
1293 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
1296 int val
, rm
, shift
, shiftop
;
1299 if (!(insn
& (1 << 25))) {
1302 if (!(insn
& (1 << 23)))
1305 tcg_gen_addi_i32(var
, var
, val
);
1307 /* shift/register */
1309 shift
= (insn
>> 7) & 0x1f;
1310 shiftop
= (insn
>> 5) & 3;
1311 offset
= load_reg(s
, rm
);
1312 gen_arm_shift_im(offset
, shiftop
, shift
, 0);
1313 if (!(insn
& (1 << 23)))
1314 tcg_gen_sub_i32(var
, var
, offset
);
1316 tcg_gen_add_i32(var
, var
, offset
);
1317 tcg_temp_free_i32(offset
);
1321 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
1322 int extra
, TCGv_i32 var
)
1327 if (insn
& (1 << 22)) {
1329 val
= (insn
& 0xf) | ((insn
>> 4) & 0xf0);
1330 if (!(insn
& (1 << 23)))
1334 tcg_gen_addi_i32(var
, var
, val
);
1338 tcg_gen_addi_i32(var
, var
, extra
);
1340 offset
= load_reg(s
, rm
);
1341 if (!(insn
& (1 << 23)))
1342 tcg_gen_sub_i32(var
, var
, offset
);
1344 tcg_gen_add_i32(var
, var
, offset
);
1345 tcg_temp_free_i32(offset
);
1349 static TCGv_ptr
get_fpstatus_ptr(int neon
)
1351 TCGv_ptr statusptr
= tcg_temp_new_ptr();
1354 offset
= offsetof(CPUARMState
, vfp
.standard_fp_status
);
1356 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
1358 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
1362 static inline long vfp_reg_offset(bool dp
, unsigned reg
)
1365 return offsetof(CPUARMState
, vfp
.zregs
[reg
>> 1].d
[reg
& 1]);
1367 long ofs
= offsetof(CPUARMState
, vfp
.zregs
[reg
>> 2].d
[(reg
>> 1) & 1]);
1369 ofs
+= offsetof(CPU_DoubleU
, l
.upper
);
1371 ofs
+= offsetof(CPU_DoubleU
, l
.lower
);
1377 /* Return the offset of a 32-bit piece of a NEON register.
1378 zero is the least significant end of the register. */
1380 neon_reg_offset (int reg
, int n
)
1384 return vfp_reg_offset(0, sreg
);
1387 /* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
1388 * where 0 is the least significant end of the register.
1391 neon_element_offset(int reg
, int element
, MemOp size
)
1393 int element_size
= 1 << size
;
1394 int ofs
= element
* element_size
;
1395 #ifdef HOST_WORDS_BIGENDIAN
1396 /* Calculate the offset assuming fully little-endian,
1397 * then XOR to account for the order of the 8-byte units.
1399 if (element_size
< 8) {
1400 ofs
^= 8 - element_size
;
1403 return neon_reg_offset(reg
, 0) + ofs
;
1406 static TCGv_i32
neon_load_reg(int reg
, int pass
)
1408 TCGv_i32 tmp
= tcg_temp_new_i32();
1409 tcg_gen_ld_i32(tmp
, cpu_env
, neon_reg_offset(reg
, pass
));
1413 static void neon_load_element(TCGv_i32 var
, int reg
, int ele
, MemOp mop
)
1415 long offset
= neon_element_offset(reg
, ele
, mop
& MO_SIZE
);
1419 tcg_gen_ld8u_i32(var
, cpu_env
, offset
);
1422 tcg_gen_ld16u_i32(var
, cpu_env
, offset
);
1425 tcg_gen_ld_i32(var
, cpu_env
, offset
);
1428 g_assert_not_reached();
1432 static void neon_load_element64(TCGv_i64 var
, int reg
, int ele
, MemOp mop
)
1434 long offset
= neon_element_offset(reg
, ele
, mop
& MO_SIZE
);
1438 tcg_gen_ld8u_i64(var
, cpu_env
, offset
);
1441 tcg_gen_ld16u_i64(var
, cpu_env
, offset
);
1444 tcg_gen_ld32u_i64(var
, cpu_env
, offset
);
1447 tcg_gen_ld_i64(var
, cpu_env
, offset
);
1450 g_assert_not_reached();
1454 static void neon_store_reg(int reg
, int pass
, TCGv_i32 var
)
1456 tcg_gen_st_i32(var
, cpu_env
, neon_reg_offset(reg
, pass
));
1457 tcg_temp_free_i32(var
);
1460 static void neon_store_element(int reg
, int ele
, MemOp size
, TCGv_i32 var
)
1462 long offset
= neon_element_offset(reg
, ele
, size
);
1466 tcg_gen_st8_i32(var
, cpu_env
, offset
);
1469 tcg_gen_st16_i32(var
, cpu_env
, offset
);
1472 tcg_gen_st_i32(var
, cpu_env
, offset
);
1475 g_assert_not_reached();
1479 static void neon_store_element64(int reg
, int ele
, MemOp size
, TCGv_i64 var
)
1481 long offset
= neon_element_offset(reg
, ele
, size
);
1485 tcg_gen_st8_i64(var
, cpu_env
, offset
);
1488 tcg_gen_st16_i64(var
, cpu_env
, offset
);
1491 tcg_gen_st32_i64(var
, cpu_env
, offset
);
1494 tcg_gen_st_i64(var
, cpu_env
, offset
);
1497 g_assert_not_reached();
1501 static inline void neon_load_reg64(TCGv_i64 var
, int reg
)
1503 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1506 static inline void neon_store_reg64(TCGv_i64 var
, int reg
)
1508 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1511 static inline void neon_load_reg32(TCGv_i32 var
, int reg
)
1513 tcg_gen_ld_i32(var
, cpu_env
, vfp_reg_offset(false, reg
));
1516 static inline void neon_store_reg32(TCGv_i32 var
, int reg
)
1518 tcg_gen_st_i32(var
, cpu_env
, vfp_reg_offset(false, reg
));
1521 static TCGv_ptr
vfp_reg_ptr(bool dp
, int reg
)
1523 TCGv_ptr ret
= tcg_temp_new_ptr();
1524 tcg_gen_addi_ptr(ret
, cpu_env
, vfp_reg_offset(dp
, reg
));
1528 #define ARM_CP_RW_BIT (1 << 20)
1530 /* Include the VFP decoder */
1531 #include "translate-vfp.inc.c"
1533 static inline void iwmmxt_load_reg(TCGv_i64 var
, int reg
)
1535 tcg_gen_ld_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1538 static inline void iwmmxt_store_reg(TCGv_i64 var
, int reg
)
1540 tcg_gen_st_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1543 static inline TCGv_i32
iwmmxt_load_creg(int reg
)
1545 TCGv_i32 var
= tcg_temp_new_i32();
1546 tcg_gen_ld_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1550 static inline void iwmmxt_store_creg(int reg
, TCGv_i32 var
)
1552 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1553 tcg_temp_free_i32(var
);
1556 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn
)
1558 iwmmxt_store_reg(cpu_M0
, rn
);
1561 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn
)
1563 iwmmxt_load_reg(cpu_M0
, rn
);
1566 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn
)
1568 iwmmxt_load_reg(cpu_V1
, rn
);
1569 tcg_gen_or_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1572 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn
)
1574 iwmmxt_load_reg(cpu_V1
, rn
);
1575 tcg_gen_and_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1578 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn
)
1580 iwmmxt_load_reg(cpu_V1
, rn
);
1581 tcg_gen_xor_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1584 #define IWMMXT_OP(name) \
1585 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1587 iwmmxt_load_reg(cpu_V1, rn); \
1588 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1591 #define IWMMXT_OP_ENV(name) \
1592 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1594 iwmmxt_load_reg(cpu_V1, rn); \
1595 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1598 #define IWMMXT_OP_ENV_SIZE(name) \
1599 IWMMXT_OP_ENV(name##b) \
1600 IWMMXT_OP_ENV(name##w) \
1601 IWMMXT_OP_ENV(name##l)
1603 #define IWMMXT_OP_ENV1(name) \
1604 static inline void gen_op_iwmmxt_##name##_M0(void) \
1606 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1620 IWMMXT_OP_ENV_SIZE(unpackl
)
1621 IWMMXT_OP_ENV_SIZE(unpackh
)
1623 IWMMXT_OP_ENV1(unpacklub
)
1624 IWMMXT_OP_ENV1(unpackluw
)
1625 IWMMXT_OP_ENV1(unpacklul
)
1626 IWMMXT_OP_ENV1(unpackhub
)
1627 IWMMXT_OP_ENV1(unpackhuw
)
1628 IWMMXT_OP_ENV1(unpackhul
)
1629 IWMMXT_OP_ENV1(unpacklsb
)
1630 IWMMXT_OP_ENV1(unpacklsw
)
1631 IWMMXT_OP_ENV1(unpacklsl
)
1632 IWMMXT_OP_ENV1(unpackhsb
)
1633 IWMMXT_OP_ENV1(unpackhsw
)
1634 IWMMXT_OP_ENV1(unpackhsl
)
1636 IWMMXT_OP_ENV_SIZE(cmpeq
)
1637 IWMMXT_OP_ENV_SIZE(cmpgtu
)
1638 IWMMXT_OP_ENV_SIZE(cmpgts
)
1640 IWMMXT_OP_ENV_SIZE(mins
)
1641 IWMMXT_OP_ENV_SIZE(minu
)
1642 IWMMXT_OP_ENV_SIZE(maxs
)
1643 IWMMXT_OP_ENV_SIZE(maxu
)
1645 IWMMXT_OP_ENV_SIZE(subn
)
1646 IWMMXT_OP_ENV_SIZE(addn
)
1647 IWMMXT_OP_ENV_SIZE(subu
)
1648 IWMMXT_OP_ENV_SIZE(addu
)
1649 IWMMXT_OP_ENV_SIZE(subs
)
1650 IWMMXT_OP_ENV_SIZE(adds
)
1652 IWMMXT_OP_ENV(avgb0
)
1653 IWMMXT_OP_ENV(avgb1
)
1654 IWMMXT_OP_ENV(avgw0
)
1655 IWMMXT_OP_ENV(avgw1
)
1657 IWMMXT_OP_ENV(packuw
)
1658 IWMMXT_OP_ENV(packul
)
1659 IWMMXT_OP_ENV(packuq
)
1660 IWMMXT_OP_ENV(packsw
)
1661 IWMMXT_OP_ENV(packsl
)
1662 IWMMXT_OP_ENV(packsq
)
1664 static void gen_op_iwmmxt_set_mup(void)
1667 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1668 tcg_gen_ori_i32(tmp
, tmp
, 2);
1669 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1672 static void gen_op_iwmmxt_set_cup(void)
1675 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1676 tcg_gen_ori_i32(tmp
, tmp
, 1);
1677 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1680 static void gen_op_iwmmxt_setpsr_nz(void)
1682 TCGv_i32 tmp
= tcg_temp_new_i32();
1683 gen_helper_iwmmxt_setpsr_nz(tmp
, cpu_M0
);
1684 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCASF
]);
1687 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn
)
1689 iwmmxt_load_reg(cpu_V1
, rn
);
1690 tcg_gen_ext32u_i64(cpu_V1
, cpu_V1
);
1691 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1694 static inline int gen_iwmmxt_address(DisasContext
*s
, uint32_t insn
,
1701 rd
= (insn
>> 16) & 0xf;
1702 tmp
= load_reg(s
, rd
);
1704 offset
= (insn
& 0xff) << ((insn
>> 7) & 2);
1705 if (insn
& (1 << 24)) {
1707 if (insn
& (1 << 23))
1708 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1710 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1711 tcg_gen_mov_i32(dest
, tmp
);
1712 if (insn
& (1 << 21))
1713 store_reg(s
, rd
, tmp
);
1715 tcg_temp_free_i32(tmp
);
1716 } else if (insn
& (1 << 21)) {
1718 tcg_gen_mov_i32(dest
, tmp
);
1719 if (insn
& (1 << 23))
1720 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1722 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1723 store_reg(s
, rd
, tmp
);
1724 } else if (!(insn
& (1 << 23)))
1729 static inline int gen_iwmmxt_shift(uint32_t insn
, uint32_t mask
, TCGv_i32 dest
)
1731 int rd
= (insn
>> 0) & 0xf;
1734 if (insn
& (1 << 8)) {
1735 if (rd
< ARM_IWMMXT_wCGR0
|| rd
> ARM_IWMMXT_wCGR3
) {
1738 tmp
= iwmmxt_load_creg(rd
);
1741 tmp
= tcg_temp_new_i32();
1742 iwmmxt_load_reg(cpu_V0
, rd
);
1743 tcg_gen_extrl_i64_i32(tmp
, cpu_V0
);
1745 tcg_gen_andi_i32(tmp
, tmp
, mask
);
1746 tcg_gen_mov_i32(dest
, tmp
);
1747 tcg_temp_free_i32(tmp
);
1751 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
1752 (ie. an undefined instruction). */
1753 static int disas_iwmmxt_insn(DisasContext
*s
, uint32_t insn
)
1756 int rdhi
, rdlo
, rd0
, rd1
, i
;
1758 TCGv_i32 tmp
, tmp2
, tmp3
;
1760 if ((insn
& 0x0e000e00) == 0x0c000000) {
1761 if ((insn
& 0x0fe00ff0) == 0x0c400000) {
1763 rdlo
= (insn
>> 12) & 0xf;
1764 rdhi
= (insn
>> 16) & 0xf;
1765 if (insn
& ARM_CP_RW_BIT
) { /* TMRRC */
1766 iwmmxt_load_reg(cpu_V0
, wrd
);
1767 tcg_gen_extrl_i64_i32(cpu_R
[rdlo
], cpu_V0
);
1768 tcg_gen_extrh_i64_i32(cpu_R
[rdhi
], cpu_V0
);
1769 } else { /* TMCRR */
1770 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
1771 iwmmxt_store_reg(cpu_V0
, wrd
);
1772 gen_op_iwmmxt_set_mup();
1777 wrd
= (insn
>> 12) & 0xf;
1778 addr
= tcg_temp_new_i32();
1779 if (gen_iwmmxt_address(s
, insn
, addr
)) {
1780 tcg_temp_free_i32(addr
);
1783 if (insn
& ARM_CP_RW_BIT
) {
1784 if ((insn
>> 28) == 0xf) { /* WLDRW wCx */
1785 tmp
= tcg_temp_new_i32();
1786 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1787 iwmmxt_store_creg(wrd
, tmp
);
1790 if (insn
& (1 << 8)) {
1791 if (insn
& (1 << 22)) { /* WLDRD */
1792 gen_aa32_ld64(s
, cpu_M0
, addr
, get_mem_index(s
));
1794 } else { /* WLDRW wRd */
1795 tmp
= tcg_temp_new_i32();
1796 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1799 tmp
= tcg_temp_new_i32();
1800 if (insn
& (1 << 22)) { /* WLDRH */
1801 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
1802 } else { /* WLDRB */
1803 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
1807 tcg_gen_extu_i32_i64(cpu_M0
, tmp
);
1808 tcg_temp_free_i32(tmp
);
1810 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1813 if ((insn
>> 28) == 0xf) { /* WSTRW wCx */
1814 tmp
= iwmmxt_load_creg(wrd
);
1815 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1817 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1818 tmp
= tcg_temp_new_i32();
1819 if (insn
& (1 << 8)) {
1820 if (insn
& (1 << 22)) { /* WSTRD */
1821 gen_aa32_st64(s
, cpu_M0
, addr
, get_mem_index(s
));
1822 } else { /* WSTRW wRd */
1823 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1824 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1827 if (insn
& (1 << 22)) { /* WSTRH */
1828 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1829 gen_aa32_st16(s
, tmp
, addr
, get_mem_index(s
));
1830 } else { /* WSTRB */
1831 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1832 gen_aa32_st8(s
, tmp
, addr
, get_mem_index(s
));
1836 tcg_temp_free_i32(tmp
);
1838 tcg_temp_free_i32(addr
);
1842 if ((insn
& 0x0f000000) != 0x0e000000)
1845 switch (((insn
>> 12) & 0xf00) | ((insn
>> 4) & 0xff)) {
1846 case 0x000: /* WOR */
1847 wrd
= (insn
>> 12) & 0xf;
1848 rd0
= (insn
>> 0) & 0xf;
1849 rd1
= (insn
>> 16) & 0xf;
1850 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1851 gen_op_iwmmxt_orq_M0_wRn(rd1
);
1852 gen_op_iwmmxt_setpsr_nz();
1853 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1854 gen_op_iwmmxt_set_mup();
1855 gen_op_iwmmxt_set_cup();
1857 case 0x011: /* TMCR */
1860 rd
= (insn
>> 12) & 0xf;
1861 wrd
= (insn
>> 16) & 0xf;
1863 case ARM_IWMMXT_wCID
:
1864 case ARM_IWMMXT_wCASF
:
1866 case ARM_IWMMXT_wCon
:
1867 gen_op_iwmmxt_set_cup();
1869 case ARM_IWMMXT_wCSSF
:
1870 tmp
= iwmmxt_load_creg(wrd
);
1871 tmp2
= load_reg(s
, rd
);
1872 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1873 tcg_temp_free_i32(tmp2
);
1874 iwmmxt_store_creg(wrd
, tmp
);
1876 case ARM_IWMMXT_wCGR0
:
1877 case ARM_IWMMXT_wCGR1
:
1878 case ARM_IWMMXT_wCGR2
:
1879 case ARM_IWMMXT_wCGR3
:
1880 gen_op_iwmmxt_set_cup();
1881 tmp
= load_reg(s
, rd
);
1882 iwmmxt_store_creg(wrd
, tmp
);
1888 case 0x100: /* WXOR */
1889 wrd
= (insn
>> 12) & 0xf;
1890 rd0
= (insn
>> 0) & 0xf;
1891 rd1
= (insn
>> 16) & 0xf;
1892 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1893 gen_op_iwmmxt_xorq_M0_wRn(rd1
);
1894 gen_op_iwmmxt_setpsr_nz();
1895 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1896 gen_op_iwmmxt_set_mup();
1897 gen_op_iwmmxt_set_cup();
1899 case 0x111: /* TMRC */
1902 rd
= (insn
>> 12) & 0xf;
1903 wrd
= (insn
>> 16) & 0xf;
1904 tmp
= iwmmxt_load_creg(wrd
);
1905 store_reg(s
, rd
, tmp
);
1907 case 0x300: /* WANDN */
1908 wrd
= (insn
>> 12) & 0xf;
1909 rd0
= (insn
>> 0) & 0xf;
1910 rd1
= (insn
>> 16) & 0xf;
1911 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1912 tcg_gen_neg_i64(cpu_M0
, cpu_M0
);
1913 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1914 gen_op_iwmmxt_setpsr_nz();
1915 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1916 gen_op_iwmmxt_set_mup();
1917 gen_op_iwmmxt_set_cup();
1919 case 0x200: /* WAND */
1920 wrd
= (insn
>> 12) & 0xf;
1921 rd0
= (insn
>> 0) & 0xf;
1922 rd1
= (insn
>> 16) & 0xf;
1923 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1924 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1925 gen_op_iwmmxt_setpsr_nz();
1926 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1927 gen_op_iwmmxt_set_mup();
1928 gen_op_iwmmxt_set_cup();
1930 case 0x810: case 0xa10: /* WMADD */
1931 wrd
= (insn
>> 12) & 0xf;
1932 rd0
= (insn
>> 0) & 0xf;
1933 rd1
= (insn
>> 16) & 0xf;
1934 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1935 if (insn
& (1 << 21))
1936 gen_op_iwmmxt_maddsq_M0_wRn(rd1
);
1938 gen_op_iwmmxt_madduq_M0_wRn(rd1
);
1939 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1940 gen_op_iwmmxt_set_mup();
1942 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1943 wrd
= (insn
>> 12) & 0xf;
1944 rd0
= (insn
>> 16) & 0xf;
1945 rd1
= (insn
>> 0) & 0xf;
1946 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1947 switch ((insn
>> 22) & 3) {
1949 gen_op_iwmmxt_unpacklb_M0_wRn(rd1
);
1952 gen_op_iwmmxt_unpacklw_M0_wRn(rd1
);
1955 gen_op_iwmmxt_unpackll_M0_wRn(rd1
);
1960 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1961 gen_op_iwmmxt_set_mup();
1962 gen_op_iwmmxt_set_cup();
1964 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1965 wrd
= (insn
>> 12) & 0xf;
1966 rd0
= (insn
>> 16) & 0xf;
1967 rd1
= (insn
>> 0) & 0xf;
1968 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1969 switch ((insn
>> 22) & 3) {
1971 gen_op_iwmmxt_unpackhb_M0_wRn(rd1
);
1974 gen_op_iwmmxt_unpackhw_M0_wRn(rd1
);
1977 gen_op_iwmmxt_unpackhl_M0_wRn(rd1
);
1982 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1983 gen_op_iwmmxt_set_mup();
1984 gen_op_iwmmxt_set_cup();
1986 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1987 wrd
= (insn
>> 12) & 0xf;
1988 rd0
= (insn
>> 16) & 0xf;
1989 rd1
= (insn
>> 0) & 0xf;
1990 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1991 if (insn
& (1 << 22))
1992 gen_op_iwmmxt_sadw_M0_wRn(rd1
);
1994 gen_op_iwmmxt_sadb_M0_wRn(rd1
);
1995 if (!(insn
& (1 << 20)))
1996 gen_op_iwmmxt_addl_M0_wRn(wrd
);
1997 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1998 gen_op_iwmmxt_set_mup();
2000 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
2001 wrd
= (insn
>> 12) & 0xf;
2002 rd0
= (insn
>> 16) & 0xf;
2003 rd1
= (insn
>> 0) & 0xf;
2004 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2005 if (insn
& (1 << 21)) {
2006 if (insn
& (1 << 20))
2007 gen_op_iwmmxt_mulshw_M0_wRn(rd1
);
2009 gen_op_iwmmxt_mulslw_M0_wRn(rd1
);
2011 if (insn
& (1 << 20))
2012 gen_op_iwmmxt_muluhw_M0_wRn(rd1
);
2014 gen_op_iwmmxt_mululw_M0_wRn(rd1
);
2016 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2017 gen_op_iwmmxt_set_mup();
2019 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
2020 wrd
= (insn
>> 12) & 0xf;
2021 rd0
= (insn
>> 16) & 0xf;
2022 rd1
= (insn
>> 0) & 0xf;
2023 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2024 if (insn
& (1 << 21))
2025 gen_op_iwmmxt_macsw_M0_wRn(rd1
);
2027 gen_op_iwmmxt_macuw_M0_wRn(rd1
);
2028 if (!(insn
& (1 << 20))) {
2029 iwmmxt_load_reg(cpu_V1
, wrd
);
2030 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
2032 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2033 gen_op_iwmmxt_set_mup();
2035 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
2036 wrd
= (insn
>> 12) & 0xf;
2037 rd0
= (insn
>> 16) & 0xf;
2038 rd1
= (insn
>> 0) & 0xf;
2039 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2040 switch ((insn
>> 22) & 3) {
2042 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1
);
2045 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1
);
2048 gen_op_iwmmxt_cmpeql_M0_wRn(rd1
);
2053 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2054 gen_op_iwmmxt_set_mup();
2055 gen_op_iwmmxt_set_cup();
2057 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
2058 wrd
= (insn
>> 12) & 0xf;
2059 rd0
= (insn
>> 16) & 0xf;
2060 rd1
= (insn
>> 0) & 0xf;
2061 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2062 if (insn
& (1 << 22)) {
2063 if (insn
& (1 << 20))
2064 gen_op_iwmmxt_avgw1_M0_wRn(rd1
);
2066 gen_op_iwmmxt_avgw0_M0_wRn(rd1
);
2068 if (insn
& (1 << 20))
2069 gen_op_iwmmxt_avgb1_M0_wRn(rd1
);
2071 gen_op_iwmmxt_avgb0_M0_wRn(rd1
);
2073 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2074 gen_op_iwmmxt_set_mup();
2075 gen_op_iwmmxt_set_cup();
2077 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
2078 wrd
= (insn
>> 12) & 0xf;
2079 rd0
= (insn
>> 16) & 0xf;
2080 rd1
= (insn
>> 0) & 0xf;
2081 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2082 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCGR0
+ ((insn
>> 20) & 3));
2083 tcg_gen_andi_i32(tmp
, tmp
, 7);
2084 iwmmxt_load_reg(cpu_V1
, rd1
);
2085 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2086 tcg_temp_free_i32(tmp
);
2087 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2088 gen_op_iwmmxt_set_mup();
2090 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
2091 if (((insn
>> 6) & 3) == 3)
2093 rd
= (insn
>> 12) & 0xf;
2094 wrd
= (insn
>> 16) & 0xf;
2095 tmp
= load_reg(s
, rd
);
2096 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2097 switch ((insn
>> 6) & 3) {
2099 tmp2
= tcg_const_i32(0xff);
2100 tmp3
= tcg_const_i32((insn
& 7) << 3);
2103 tmp2
= tcg_const_i32(0xffff);
2104 tmp3
= tcg_const_i32((insn
& 3) << 4);
2107 tmp2
= tcg_const_i32(0xffffffff);
2108 tmp3
= tcg_const_i32((insn
& 1) << 5);
2114 gen_helper_iwmmxt_insr(cpu_M0
, cpu_M0
, tmp
, tmp2
, tmp3
);
2115 tcg_temp_free_i32(tmp3
);
2116 tcg_temp_free_i32(tmp2
);
2117 tcg_temp_free_i32(tmp
);
2118 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2119 gen_op_iwmmxt_set_mup();
2121 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
2122 rd
= (insn
>> 12) & 0xf;
2123 wrd
= (insn
>> 16) & 0xf;
2124 if (rd
== 15 || ((insn
>> 22) & 3) == 3)
2126 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2127 tmp
= tcg_temp_new_i32();
2128 switch ((insn
>> 22) & 3) {
2130 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 7) << 3);
2131 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
2133 tcg_gen_ext8s_i32(tmp
, tmp
);
2135 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
2139 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 3) << 4);
2140 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
2142 tcg_gen_ext16s_i32(tmp
, tmp
);
2144 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
2148 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 1) << 5);
2149 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
2152 store_reg(s
, rd
, tmp
);
2154 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
2155 if ((insn
& 0x000ff008) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2157 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2158 switch ((insn
>> 22) & 3) {
2160 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 7) << 2) + 0);
2163 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 3) << 3) + 4);
2166 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 1) << 4) + 12);
2169 tcg_gen_shli_i32(tmp
, tmp
, 28);
2171 tcg_temp_free_i32(tmp
);
2173 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
2174 if (((insn
>> 6) & 3) == 3)
2176 rd
= (insn
>> 12) & 0xf;
2177 wrd
= (insn
>> 16) & 0xf;
2178 tmp
= load_reg(s
, rd
);
2179 switch ((insn
>> 6) & 3) {
2181 gen_helper_iwmmxt_bcstb(cpu_M0
, tmp
);
2184 gen_helper_iwmmxt_bcstw(cpu_M0
, tmp
);
2187 gen_helper_iwmmxt_bcstl(cpu_M0
, tmp
);
2190 tcg_temp_free_i32(tmp
);
2191 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2192 gen_op_iwmmxt_set_mup();
2194 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
2195 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2197 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2198 tmp2
= tcg_temp_new_i32();
2199 tcg_gen_mov_i32(tmp2
, tmp
);
2200 switch ((insn
>> 22) & 3) {
2202 for (i
= 0; i
< 7; i
++) {
2203 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
2204 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2208 for (i
= 0; i
< 3; i
++) {
2209 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
2210 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2214 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
2215 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2219 tcg_temp_free_i32(tmp2
);
2220 tcg_temp_free_i32(tmp
);
2222 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
2223 wrd
= (insn
>> 12) & 0xf;
2224 rd0
= (insn
>> 16) & 0xf;
2225 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2226 switch ((insn
>> 22) & 3) {
2228 gen_helper_iwmmxt_addcb(cpu_M0
, cpu_M0
);
2231 gen_helper_iwmmxt_addcw(cpu_M0
, cpu_M0
);
2234 gen_helper_iwmmxt_addcl(cpu_M0
, cpu_M0
);
2239 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2240 gen_op_iwmmxt_set_mup();
2242 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
2243 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2245 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2246 tmp2
= tcg_temp_new_i32();
2247 tcg_gen_mov_i32(tmp2
, tmp
);
2248 switch ((insn
>> 22) & 3) {
2250 for (i
= 0; i
< 7; i
++) {
2251 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
2252 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2256 for (i
= 0; i
< 3; i
++) {
2257 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
2258 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2262 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
2263 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2267 tcg_temp_free_i32(tmp2
);
2268 tcg_temp_free_i32(tmp
);
2270 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
2271 rd
= (insn
>> 12) & 0xf;
2272 rd0
= (insn
>> 16) & 0xf;
2273 if ((insn
& 0xf) != 0 || ((insn
>> 22) & 3) == 3)
2275 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2276 tmp
= tcg_temp_new_i32();
2277 switch ((insn
>> 22) & 3) {
2279 gen_helper_iwmmxt_msbb(tmp
, cpu_M0
);
2282 gen_helper_iwmmxt_msbw(tmp
, cpu_M0
);
2285 gen_helper_iwmmxt_msbl(tmp
, cpu_M0
);
2288 store_reg(s
, rd
, tmp
);
2290 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
2291 case 0x906: case 0xb06: case 0xd06: case 0xf06:
2292 wrd
= (insn
>> 12) & 0xf;
2293 rd0
= (insn
>> 16) & 0xf;
2294 rd1
= (insn
>> 0) & 0xf;
2295 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2296 switch ((insn
>> 22) & 3) {
2298 if (insn
& (1 << 21))
2299 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1
);
2301 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1
);
2304 if (insn
& (1 << 21))
2305 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1
);
2307 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1
);
2310 if (insn
& (1 << 21))
2311 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1
);
2313 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1
);
2318 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2319 gen_op_iwmmxt_set_mup();
2320 gen_op_iwmmxt_set_cup();
2322 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2323 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2324 wrd
= (insn
>> 12) & 0xf;
2325 rd0
= (insn
>> 16) & 0xf;
2326 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2327 switch ((insn
>> 22) & 3) {
2329 if (insn
& (1 << 21))
2330 gen_op_iwmmxt_unpacklsb_M0();
2332 gen_op_iwmmxt_unpacklub_M0();
2335 if (insn
& (1 << 21))
2336 gen_op_iwmmxt_unpacklsw_M0();
2338 gen_op_iwmmxt_unpackluw_M0();
2341 if (insn
& (1 << 21))
2342 gen_op_iwmmxt_unpacklsl_M0();
2344 gen_op_iwmmxt_unpacklul_M0();
2349 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2350 gen_op_iwmmxt_set_mup();
2351 gen_op_iwmmxt_set_cup();
2353 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2354 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2355 wrd
= (insn
>> 12) & 0xf;
2356 rd0
= (insn
>> 16) & 0xf;
2357 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2358 switch ((insn
>> 22) & 3) {
2360 if (insn
& (1 << 21))
2361 gen_op_iwmmxt_unpackhsb_M0();
2363 gen_op_iwmmxt_unpackhub_M0();
2366 if (insn
& (1 << 21))
2367 gen_op_iwmmxt_unpackhsw_M0();
2369 gen_op_iwmmxt_unpackhuw_M0();
2372 if (insn
& (1 << 21))
2373 gen_op_iwmmxt_unpackhsl_M0();
2375 gen_op_iwmmxt_unpackhul_M0();
2380 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2381 gen_op_iwmmxt_set_mup();
2382 gen_op_iwmmxt_set_cup();
2384 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2385 case 0x214: case 0x614: case 0xa14: case 0xe14:
2386 if (((insn
>> 22) & 3) == 0)
2388 wrd
= (insn
>> 12) & 0xf;
2389 rd0
= (insn
>> 16) & 0xf;
2390 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2391 tmp
= tcg_temp_new_i32();
2392 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2393 tcg_temp_free_i32(tmp
);
2396 switch ((insn
>> 22) & 3) {
2398 gen_helper_iwmmxt_srlw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2401 gen_helper_iwmmxt_srll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2404 gen_helper_iwmmxt_srlq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2407 tcg_temp_free_i32(tmp
);
2408 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2409 gen_op_iwmmxt_set_mup();
2410 gen_op_iwmmxt_set_cup();
2412 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2413 case 0x014: case 0x414: case 0x814: case 0xc14:
2414 if (((insn
>> 22) & 3) == 0)
2416 wrd
= (insn
>> 12) & 0xf;
2417 rd0
= (insn
>> 16) & 0xf;
2418 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2419 tmp
= tcg_temp_new_i32();
2420 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2421 tcg_temp_free_i32(tmp
);
2424 switch ((insn
>> 22) & 3) {
2426 gen_helper_iwmmxt_sraw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2429 gen_helper_iwmmxt_sral(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2432 gen_helper_iwmmxt_sraq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2435 tcg_temp_free_i32(tmp
);
2436 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2437 gen_op_iwmmxt_set_mup();
2438 gen_op_iwmmxt_set_cup();
2440 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2441 case 0x114: case 0x514: case 0x914: case 0xd14:
2442 if (((insn
>> 22) & 3) == 0)
2444 wrd
= (insn
>> 12) & 0xf;
2445 rd0
= (insn
>> 16) & 0xf;
2446 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2447 tmp
= tcg_temp_new_i32();
2448 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2449 tcg_temp_free_i32(tmp
);
2452 switch ((insn
>> 22) & 3) {
2454 gen_helper_iwmmxt_sllw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2457 gen_helper_iwmmxt_slll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2460 gen_helper_iwmmxt_sllq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2463 tcg_temp_free_i32(tmp
);
2464 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2465 gen_op_iwmmxt_set_mup();
2466 gen_op_iwmmxt_set_cup();
2468 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2469 case 0x314: case 0x714: case 0xb14: case 0xf14:
2470 if (((insn
>> 22) & 3) == 0)
2472 wrd
= (insn
>> 12) & 0xf;
2473 rd0
= (insn
>> 16) & 0xf;
2474 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2475 tmp
= tcg_temp_new_i32();
2476 switch ((insn
>> 22) & 3) {
2478 if (gen_iwmmxt_shift(insn
, 0xf, tmp
)) {
2479 tcg_temp_free_i32(tmp
);
2482 gen_helper_iwmmxt_rorw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2485 if (gen_iwmmxt_shift(insn
, 0x1f, tmp
)) {
2486 tcg_temp_free_i32(tmp
);
2489 gen_helper_iwmmxt_rorl(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2492 if (gen_iwmmxt_shift(insn
, 0x3f, tmp
)) {
2493 tcg_temp_free_i32(tmp
);
2496 gen_helper_iwmmxt_rorq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2499 tcg_temp_free_i32(tmp
);
2500 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2501 gen_op_iwmmxt_set_mup();
2502 gen_op_iwmmxt_set_cup();
2504 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2505 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2506 wrd
= (insn
>> 12) & 0xf;
2507 rd0
= (insn
>> 16) & 0xf;
2508 rd1
= (insn
>> 0) & 0xf;
2509 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2510 switch ((insn
>> 22) & 3) {
2512 if (insn
& (1 << 21))
2513 gen_op_iwmmxt_minsb_M0_wRn(rd1
);
2515 gen_op_iwmmxt_minub_M0_wRn(rd1
);
2518 if (insn
& (1 << 21))
2519 gen_op_iwmmxt_minsw_M0_wRn(rd1
);
2521 gen_op_iwmmxt_minuw_M0_wRn(rd1
);
2524 if (insn
& (1 << 21))
2525 gen_op_iwmmxt_minsl_M0_wRn(rd1
);
2527 gen_op_iwmmxt_minul_M0_wRn(rd1
);
2532 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2533 gen_op_iwmmxt_set_mup();
2535 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2536 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2537 wrd
= (insn
>> 12) & 0xf;
2538 rd0
= (insn
>> 16) & 0xf;
2539 rd1
= (insn
>> 0) & 0xf;
2540 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2541 switch ((insn
>> 22) & 3) {
2543 if (insn
& (1 << 21))
2544 gen_op_iwmmxt_maxsb_M0_wRn(rd1
);
2546 gen_op_iwmmxt_maxub_M0_wRn(rd1
);
2549 if (insn
& (1 << 21))
2550 gen_op_iwmmxt_maxsw_M0_wRn(rd1
);
2552 gen_op_iwmmxt_maxuw_M0_wRn(rd1
);
2555 if (insn
& (1 << 21))
2556 gen_op_iwmmxt_maxsl_M0_wRn(rd1
);
2558 gen_op_iwmmxt_maxul_M0_wRn(rd1
);
2563 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2564 gen_op_iwmmxt_set_mup();
2566 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2567 case 0x402: case 0x502: case 0x602: case 0x702:
2568 wrd
= (insn
>> 12) & 0xf;
2569 rd0
= (insn
>> 16) & 0xf;
2570 rd1
= (insn
>> 0) & 0xf;
2571 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2572 tmp
= tcg_const_i32((insn
>> 20) & 3);
2573 iwmmxt_load_reg(cpu_V1
, rd1
);
2574 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2575 tcg_temp_free_i32(tmp
);
2576 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2577 gen_op_iwmmxt_set_mup();
2579 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2580 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2581 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2582 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2583 wrd
= (insn
>> 12) & 0xf;
2584 rd0
= (insn
>> 16) & 0xf;
2585 rd1
= (insn
>> 0) & 0xf;
2586 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2587 switch ((insn
>> 20) & 0xf) {
2589 gen_op_iwmmxt_subnb_M0_wRn(rd1
);
2592 gen_op_iwmmxt_subub_M0_wRn(rd1
);
2595 gen_op_iwmmxt_subsb_M0_wRn(rd1
);
2598 gen_op_iwmmxt_subnw_M0_wRn(rd1
);
2601 gen_op_iwmmxt_subuw_M0_wRn(rd1
);
2604 gen_op_iwmmxt_subsw_M0_wRn(rd1
);
2607 gen_op_iwmmxt_subnl_M0_wRn(rd1
);
2610 gen_op_iwmmxt_subul_M0_wRn(rd1
);
2613 gen_op_iwmmxt_subsl_M0_wRn(rd1
);
2618 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2619 gen_op_iwmmxt_set_mup();
2620 gen_op_iwmmxt_set_cup();
2622 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2623 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2624 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2625 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2626 wrd
= (insn
>> 12) & 0xf;
2627 rd0
= (insn
>> 16) & 0xf;
2628 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2629 tmp
= tcg_const_i32(((insn
>> 16) & 0xf0) | (insn
& 0x0f));
2630 gen_helper_iwmmxt_shufh(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2631 tcg_temp_free_i32(tmp
);
2632 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2633 gen_op_iwmmxt_set_mup();
2634 gen_op_iwmmxt_set_cup();
2636 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2637 case 0x418: case 0x518: case 0x618: case 0x718:
2638 case 0x818: case 0x918: case 0xa18: case 0xb18:
2639 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2640 wrd
= (insn
>> 12) & 0xf;
2641 rd0
= (insn
>> 16) & 0xf;
2642 rd1
= (insn
>> 0) & 0xf;
2643 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2644 switch ((insn
>> 20) & 0xf) {
2646 gen_op_iwmmxt_addnb_M0_wRn(rd1
);
2649 gen_op_iwmmxt_addub_M0_wRn(rd1
);
2652 gen_op_iwmmxt_addsb_M0_wRn(rd1
);
2655 gen_op_iwmmxt_addnw_M0_wRn(rd1
);
2658 gen_op_iwmmxt_adduw_M0_wRn(rd1
);
2661 gen_op_iwmmxt_addsw_M0_wRn(rd1
);
2664 gen_op_iwmmxt_addnl_M0_wRn(rd1
);
2667 gen_op_iwmmxt_addul_M0_wRn(rd1
);
2670 gen_op_iwmmxt_addsl_M0_wRn(rd1
);
2675 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2676 gen_op_iwmmxt_set_mup();
2677 gen_op_iwmmxt_set_cup();
2679 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2680 case 0x408: case 0x508: case 0x608: case 0x708:
2681 case 0x808: case 0x908: case 0xa08: case 0xb08:
2682 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2683 if (!(insn
& (1 << 20)) || ((insn
>> 22) & 3) == 0)
2685 wrd
= (insn
>> 12) & 0xf;
2686 rd0
= (insn
>> 16) & 0xf;
2687 rd1
= (insn
>> 0) & 0xf;
2688 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2689 switch ((insn
>> 22) & 3) {
2691 if (insn
& (1 << 21))
2692 gen_op_iwmmxt_packsw_M0_wRn(rd1
);
2694 gen_op_iwmmxt_packuw_M0_wRn(rd1
);
2697 if (insn
& (1 << 21))
2698 gen_op_iwmmxt_packsl_M0_wRn(rd1
);
2700 gen_op_iwmmxt_packul_M0_wRn(rd1
);
2703 if (insn
& (1 << 21))
2704 gen_op_iwmmxt_packsq_M0_wRn(rd1
);
2706 gen_op_iwmmxt_packuq_M0_wRn(rd1
);
2709 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2710 gen_op_iwmmxt_set_mup();
2711 gen_op_iwmmxt_set_cup();
2713 case 0x201: case 0x203: case 0x205: case 0x207:
2714 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2715 case 0x211: case 0x213: case 0x215: case 0x217:
2716 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2717 wrd
= (insn
>> 5) & 0xf;
2718 rd0
= (insn
>> 12) & 0xf;
2719 rd1
= (insn
>> 0) & 0xf;
2720 if (rd0
== 0xf || rd1
== 0xf)
2722 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2723 tmp
= load_reg(s
, rd0
);
2724 tmp2
= load_reg(s
, rd1
);
2725 switch ((insn
>> 16) & 0xf) {
2726 case 0x0: /* TMIA */
2727 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2729 case 0x8: /* TMIAPH */
2730 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2732 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2733 if (insn
& (1 << 16))
2734 tcg_gen_shri_i32(tmp
, tmp
, 16);
2735 if (insn
& (1 << 17))
2736 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2737 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2740 tcg_temp_free_i32(tmp2
);
2741 tcg_temp_free_i32(tmp
);
2744 tcg_temp_free_i32(tmp2
);
2745 tcg_temp_free_i32(tmp
);
2746 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2747 gen_op_iwmmxt_set_mup();
2756 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
2757 (ie. an undefined instruction). */
2758 static int disas_dsp_insn(DisasContext
*s
, uint32_t insn
)
2760 int acc
, rd0
, rd1
, rdhi
, rdlo
;
2763 if ((insn
& 0x0ff00f10) == 0x0e200010) {
2764 /* Multiply with Internal Accumulate Format */
2765 rd0
= (insn
>> 12) & 0xf;
2767 acc
= (insn
>> 5) & 7;
2772 tmp
= load_reg(s
, rd0
);
2773 tmp2
= load_reg(s
, rd1
);
2774 switch ((insn
>> 16) & 0xf) {
2776 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2778 case 0x8: /* MIAPH */
2779 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2781 case 0xc: /* MIABB */
2782 case 0xd: /* MIABT */
2783 case 0xe: /* MIATB */
2784 case 0xf: /* MIATT */
2785 if (insn
& (1 << 16))
2786 tcg_gen_shri_i32(tmp
, tmp
, 16);
2787 if (insn
& (1 << 17))
2788 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2789 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2794 tcg_temp_free_i32(tmp2
);
2795 tcg_temp_free_i32(tmp
);
2797 gen_op_iwmmxt_movq_wRn_M0(acc
);
2801 if ((insn
& 0x0fe00ff8) == 0x0c400000) {
2802 /* Internal Accumulator Access Format */
2803 rdhi
= (insn
>> 16) & 0xf;
2804 rdlo
= (insn
>> 12) & 0xf;
2810 if (insn
& ARM_CP_RW_BIT
) { /* MRA */
2811 iwmmxt_load_reg(cpu_V0
, acc
);
2812 tcg_gen_extrl_i64_i32(cpu_R
[rdlo
], cpu_V0
);
2813 tcg_gen_extrh_i64_i32(cpu_R
[rdhi
], cpu_V0
);
2814 tcg_gen_andi_i32(cpu_R
[rdhi
], cpu_R
[rdhi
], (1 << (40 - 32)) - 1);
2816 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
2817 iwmmxt_store_reg(cpu_V0
, acc
);
2825 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2826 #define VFP_SREG(insn, bigbit, smallbit) \
2827 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2828 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2829 if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \
2830 reg = (((insn) >> (bigbit)) & 0x0f) \
2831 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2833 if (insn & (1 << (smallbit))) \
2835 reg = ((insn) >> (bigbit)) & 0x0f; \
2838 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2839 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2840 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2841 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2842 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2843 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2845 static void gen_neon_dup_low16(TCGv_i32 var
)
2847 TCGv_i32 tmp
= tcg_temp_new_i32();
2848 tcg_gen_ext16u_i32(var
, var
);
2849 tcg_gen_shli_i32(tmp
, var
, 16);
2850 tcg_gen_or_i32(var
, var
, tmp
);
2851 tcg_temp_free_i32(tmp
);
2854 static void gen_neon_dup_high16(TCGv_i32 var
)
2856 TCGv_i32 tmp
= tcg_temp_new_i32();
2857 tcg_gen_andi_i32(var
, var
, 0xffff0000);
2858 tcg_gen_shri_i32(tmp
, var
, 16);
2859 tcg_gen_or_i32(var
, var
, tmp
);
2860 tcg_temp_free_i32(tmp
);
2864 * Disassemble a VFP instruction. Returns nonzero if an error occurred
2865 * (ie. an undefined instruction).
2867 static int disas_vfp_insn(DisasContext
*s
, uint32_t insn
)
2869 if (!arm_dc_feature(s
, ARM_FEATURE_VFP
)) {
2874 * If the decodetree decoder handles this insn it will always
2875 * emit code to either execute the insn or generate an appropriate
2876 * exception; so we don't need to ever return non-zero to tell
2877 * the calling code to emit an UNDEF exception.
2879 if (extract32(insn
, 28, 4) == 0xf) {
2880 if (disas_vfp_uncond(s
, insn
)) {
2884 if (disas_vfp(s
, insn
)) {
2888 /* If the decodetree decoder didn't handle this insn, it must be UNDEF */
2892 static inline bool use_goto_tb(DisasContext
*s
, target_ulong dest
)
2894 #ifndef CONFIG_USER_ONLY
2895 return (s
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
2896 ((s
->base
.pc_next
- 1) & TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
2902 static void gen_goto_ptr(void)
2904 tcg_gen_lookup_and_goto_ptr();
2907 /* This will end the TB but doesn't guarantee we'll return to
2908 * cpu_loop_exec. Any live exit_requests will be processed as we
2909 * enter the next TB.
2911 static void gen_goto_tb(DisasContext
*s
, int n
, target_ulong dest
)
2913 if (use_goto_tb(s
, dest
)) {
2915 gen_set_pc_im(s
, dest
);
2916 tcg_gen_exit_tb(s
->base
.tb
, n
);
2918 gen_set_pc_im(s
, dest
);
2921 s
->base
.is_jmp
= DISAS_NORETURN
;
2924 static inline void gen_jmp (DisasContext
*s
, uint32_t dest
)
2926 if (unlikely(is_singlestepping(s
))) {
2927 /* An indirect jump so that we still trigger the debug exception. */
2932 gen_goto_tb(s
, 0, dest
);
2936 static inline void gen_mulxy(TCGv_i32 t0
, TCGv_i32 t1
, int x
, int y
)
2939 tcg_gen_sari_i32(t0
, t0
, 16);
2943 tcg_gen_sari_i32(t1
, t1
, 16);
2946 tcg_gen_mul_i32(t0
, t0
, t1
);
2949 /* Return the mask of PSR bits set by a MSR instruction. */
2950 static uint32_t msr_mask(DisasContext
*s
, int flags
, int spsr
)
2955 if (flags
& (1 << 0))
2957 if (flags
& (1 << 1))
2959 if (flags
& (1 << 2))
2961 if (flags
& (1 << 3))
2964 /* Mask out undefined bits. */
2965 mask
&= ~CPSR_RESERVED
;
2966 if (!arm_dc_feature(s
, ARM_FEATURE_V4T
)) {
2969 if (!arm_dc_feature(s
, ARM_FEATURE_V5
)) {
2970 mask
&= ~CPSR_Q
; /* V5TE in reality*/
2972 if (!arm_dc_feature(s
, ARM_FEATURE_V6
)) {
2973 mask
&= ~(CPSR_E
| CPSR_GE
);
2975 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB2
)) {
2978 /* Mask out execution state and reserved bits. */
2980 mask
&= ~(CPSR_EXEC
| CPSR_RESERVED
);
2982 /* Mask out privileged bits. */
2988 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
2989 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int spsr
, TCGv_i32 t0
)
2993 /* ??? This is also undefined in system mode. */
2997 tmp
= load_cpu_field(spsr
);
2998 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
2999 tcg_gen_andi_i32(t0
, t0
, mask
);
3000 tcg_gen_or_i32(tmp
, tmp
, t0
);
3001 store_cpu_field(tmp
, spsr
);
3003 gen_set_cpsr(t0
, mask
);
3005 tcg_temp_free_i32(t0
);
3010 /* Returns nonzero if access to the PSR is not permitted. */
3011 static int gen_set_psr_im(DisasContext
*s
, uint32_t mask
, int spsr
, uint32_t val
)
3014 tmp
= tcg_temp_new_i32();
3015 tcg_gen_movi_i32(tmp
, val
);
3016 return gen_set_psr(s
, mask
, spsr
, tmp
);
3019 static bool msr_banked_access_decode(DisasContext
*s
, int r
, int sysm
, int rn
,
3020 int *tgtmode
, int *regno
)
3022 /* Decode the r and sysm fields of MSR/MRS banked accesses into
3023 * the target mode and register number, and identify the various
3024 * unpredictable cases.
3025 * MSR (banked) and MRS (banked) are CONSTRAINED UNPREDICTABLE if:
3026 * + executed in user mode
3027 * + using R15 as the src/dest register
3028 * + accessing an unimplemented register
3029 * + accessing a register that's inaccessible at current PL/security state*
3030 * + accessing a register that you could access with a different insn
3031 * We choose to UNDEF in all these cases.
3032 * Since we don't know which of the various AArch32 modes we are in
3033 * we have to defer some checks to runtime.
3034 * Accesses to Monitor mode registers from Secure EL1 (which implies
3035 * that EL3 is AArch64) must trap to EL3.
3037 * If the access checks fail this function will emit code to take
3038 * an exception and return false. Otherwise it will return true,
3039 * and set *tgtmode and *regno appropriately.
3041 int exc_target
= default_exception_el(s
);
3043 /* These instructions are present only in ARMv8, or in ARMv7 with the
3044 * Virtualization Extensions.
3046 if (!arm_dc_feature(s
, ARM_FEATURE_V8
) &&
3047 !arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
3051 if (IS_USER(s
) || rn
== 15) {
3055 /* The table in the v8 ARM ARM section F5.2.3 describes the encoding
3056 * of registers into (r, sysm).
3059 /* SPSRs for other modes */
3061 case 0xe: /* SPSR_fiq */
3062 *tgtmode
= ARM_CPU_MODE_FIQ
;
3064 case 0x10: /* SPSR_irq */
3065 *tgtmode
= ARM_CPU_MODE_IRQ
;
3067 case 0x12: /* SPSR_svc */
3068 *tgtmode
= ARM_CPU_MODE_SVC
;
3070 case 0x14: /* SPSR_abt */
3071 *tgtmode
= ARM_CPU_MODE_ABT
;
3073 case 0x16: /* SPSR_und */
3074 *tgtmode
= ARM_CPU_MODE_UND
;
3076 case 0x1c: /* SPSR_mon */
3077 *tgtmode
= ARM_CPU_MODE_MON
;
3079 case 0x1e: /* SPSR_hyp */
3080 *tgtmode
= ARM_CPU_MODE_HYP
;
3082 default: /* unallocated */
3085 /* We arbitrarily assign SPSR a register number of 16. */
3088 /* general purpose registers for other modes */
3090 case 0x0 ... 0x6: /* 0b00xxx : r8_usr ... r14_usr */
3091 *tgtmode
= ARM_CPU_MODE_USR
;
3094 case 0x8 ... 0xe: /* 0b01xxx : r8_fiq ... r14_fiq */
3095 *tgtmode
= ARM_CPU_MODE_FIQ
;
3098 case 0x10 ... 0x11: /* 0b1000x : r14_irq, r13_irq */
3099 *tgtmode
= ARM_CPU_MODE_IRQ
;
3100 *regno
= sysm
& 1 ? 13 : 14;
3102 case 0x12 ... 0x13: /* 0b1001x : r14_svc, r13_svc */
3103 *tgtmode
= ARM_CPU_MODE_SVC
;
3104 *regno
= sysm
& 1 ? 13 : 14;
3106 case 0x14 ... 0x15: /* 0b1010x : r14_abt, r13_abt */
3107 *tgtmode
= ARM_CPU_MODE_ABT
;
3108 *regno
= sysm
& 1 ? 13 : 14;
3110 case 0x16 ... 0x17: /* 0b1011x : r14_und, r13_und */
3111 *tgtmode
= ARM_CPU_MODE_UND
;
3112 *regno
= sysm
& 1 ? 13 : 14;
3114 case 0x1c ... 0x1d: /* 0b1110x : r14_mon, r13_mon */
3115 *tgtmode
= ARM_CPU_MODE_MON
;
3116 *regno
= sysm
& 1 ? 13 : 14;
3118 case 0x1e ... 0x1f: /* 0b1111x : elr_hyp, r13_hyp */
3119 *tgtmode
= ARM_CPU_MODE_HYP
;
3120 /* Arbitrarily pick 17 for ELR_Hyp (which is not a banked LR!) */
3121 *regno
= sysm
& 1 ? 13 : 17;
3123 default: /* unallocated */
3128 /* Catch the 'accessing inaccessible register' cases we can detect
3129 * at translate time.
3132 case ARM_CPU_MODE_MON
:
3133 if (!arm_dc_feature(s
, ARM_FEATURE_EL3
) || s
->ns
) {
3136 if (s
->current_el
== 1) {
3137 /* If we're in Secure EL1 (which implies that EL3 is AArch64)
3138 * then accesses to Mon registers trap to EL3
3144 case ARM_CPU_MODE_HYP
:
3146 * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
3147 * (and so we can forbid accesses from EL2 or below). elr_hyp
3148 * can be accessed also from Hyp mode, so forbid accesses from
3151 if (!arm_dc_feature(s
, ARM_FEATURE_EL2
) || s
->current_el
< 2 ||
3152 (s
->current_el
< 3 && *regno
!= 17)) {
3163 /* If we get here then some access check did not pass */
3164 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
3165 syn_uncategorized(), exc_target
);
3169 static void gen_msr_banked(DisasContext
*s
, int r
, int sysm
, int rn
)
3171 TCGv_i32 tcg_reg
, tcg_tgtmode
, tcg_regno
;
3172 int tgtmode
= 0, regno
= 0;
3174 if (!msr_banked_access_decode(s
, r
, sysm
, rn
, &tgtmode
, ®no
)) {
3178 /* Sync state because msr_banked() can raise exceptions */
3179 gen_set_condexec(s
);
3180 gen_set_pc_im(s
, s
->pc_curr
);
3181 tcg_reg
= load_reg(s
, rn
);
3182 tcg_tgtmode
= tcg_const_i32(tgtmode
);
3183 tcg_regno
= tcg_const_i32(regno
);
3184 gen_helper_msr_banked(cpu_env
, tcg_reg
, tcg_tgtmode
, tcg_regno
);
3185 tcg_temp_free_i32(tcg_tgtmode
);
3186 tcg_temp_free_i32(tcg_regno
);
3187 tcg_temp_free_i32(tcg_reg
);
3188 s
->base
.is_jmp
= DISAS_UPDATE
;
3191 static void gen_mrs_banked(DisasContext
*s
, int r
, int sysm
, int rn
)
3193 TCGv_i32 tcg_reg
, tcg_tgtmode
, tcg_regno
;
3194 int tgtmode
= 0, regno
= 0;
3196 if (!msr_banked_access_decode(s
, r
, sysm
, rn
, &tgtmode
, ®no
)) {
3200 /* Sync state because mrs_banked() can raise exceptions */
3201 gen_set_condexec(s
);
3202 gen_set_pc_im(s
, s
->pc_curr
);
3203 tcg_reg
= tcg_temp_new_i32();
3204 tcg_tgtmode
= tcg_const_i32(tgtmode
);
3205 tcg_regno
= tcg_const_i32(regno
);
3206 gen_helper_mrs_banked(tcg_reg
, cpu_env
, tcg_tgtmode
, tcg_regno
);
3207 tcg_temp_free_i32(tcg_tgtmode
);
3208 tcg_temp_free_i32(tcg_regno
);
3209 store_reg(s
, rn
, tcg_reg
);
3210 s
->base
.is_jmp
= DISAS_UPDATE
;
3213 /* Store value to PC as for an exception return (ie don't
3214 * mask bits). The subsequent call to gen_helper_cpsr_write_eret()
3215 * will do the masking based on the new value of the Thumb bit.
3217 static void store_pc_exc_ret(DisasContext
*s
, TCGv_i32 pc
)
3219 tcg_gen_mov_i32(cpu_R
[15], pc
);
3220 tcg_temp_free_i32(pc
);
3223 /* Generate a v6 exception return. Marks both values as dead. */
3224 static void gen_rfe(DisasContext
*s
, TCGv_i32 pc
, TCGv_i32 cpsr
)
3226 store_pc_exc_ret(s
, pc
);
3227 /* The cpsr_write_eret helper will mask the low bits of PC
3228 * appropriately depending on the new Thumb bit, so it must
3229 * be called after storing the new PC.
3231 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
3234 gen_helper_cpsr_write_eret(cpu_env
, cpsr
);
3235 tcg_temp_free_i32(cpsr
);
3236 /* Must exit loop to check un-masked IRQs */
3237 s
->base
.is_jmp
= DISAS_EXIT
;
3240 /* Generate an old-style exception return. Marks pc as dead. */
3241 static void gen_exception_return(DisasContext
*s
, TCGv_i32 pc
)
3243 gen_rfe(s
, pc
, load_cpu_field(spsr
));
3247 * For WFI we will halt the vCPU until an IRQ. For WFE and YIELD we
3248 * only call the helper when running single threaded TCG code to ensure
3249 * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we
3250 * just skip this instruction. Currently the SEV/SEVL instructions
3251 * which are *one* of many ways to wake the CPU from WFE are not
3252 * implemented so we can't sleep like WFI does.
3254 static void gen_nop_hint(DisasContext
*s
, int val
)
3257 /* When running in MTTCG we don't generate jumps to the yield and
3258 * WFE helpers as it won't affect the scheduling of other vCPUs.
3259 * If we wanted to more completely model WFE/SEV so we don't busy
3260 * spin unnecessarily we would need to do something more involved.
3263 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
3264 gen_set_pc_im(s
, s
->base
.pc_next
);
3265 s
->base
.is_jmp
= DISAS_YIELD
;
3269 gen_set_pc_im(s
, s
->base
.pc_next
);
3270 s
->base
.is_jmp
= DISAS_WFI
;
3273 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
3274 gen_set_pc_im(s
, s
->base
.pc_next
);
3275 s
->base
.is_jmp
= DISAS_WFE
;
3280 /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */
3286 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3288 static inline void gen_neon_add(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
3291 case 0: gen_helper_neon_add_u8(t0
, t0
, t1
); break;
3292 case 1: gen_helper_neon_add_u16(t0
, t0
, t1
); break;
3293 case 2: tcg_gen_add_i32(t0
, t0
, t1
); break;
3298 static inline void gen_neon_rsb(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
3301 case 0: gen_helper_neon_sub_u8(t0
, t1
, t0
); break;
3302 case 1: gen_helper_neon_sub_u16(t0
, t1
, t0
); break;
3303 case 2: tcg_gen_sub_i32(t0
, t1
, t0
); break;
3308 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3309 #define gen_helper_neon_pmax_s32 tcg_gen_smax_i32
3310 #define gen_helper_neon_pmax_u32 tcg_gen_umax_i32
3311 #define gen_helper_neon_pmin_s32 tcg_gen_smin_i32
3312 #define gen_helper_neon_pmin_u32 tcg_gen_umin_i32
3314 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3315 switch ((size << 1) | u) { \
3317 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3320 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3323 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3326 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3329 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3332 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3334 default: return 1; \
3337 #define GEN_NEON_INTEGER_OP(name) do { \
3338 switch ((size << 1) | u) { \
3340 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3343 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3346 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3349 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3352 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3355 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3357 default: return 1; \
3360 static TCGv_i32
neon_load_scratch(int scratch
)
3362 TCGv_i32 tmp
= tcg_temp_new_i32();
3363 tcg_gen_ld_i32(tmp
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3367 static void neon_store_scratch(int scratch
, TCGv_i32 var
)
3369 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3370 tcg_temp_free_i32(var
);
3373 static inline TCGv_i32
neon_get_scalar(int size
, int reg
)
3377 tmp
= neon_load_reg(reg
& 7, reg
>> 4);
3379 gen_neon_dup_high16(tmp
);
3381 gen_neon_dup_low16(tmp
);
3384 tmp
= neon_load_reg(reg
& 15, reg
>> 4);
3389 static int gen_neon_unzip(int rd
, int rm
, int size
, int q
)
3393 if (!q
&& size
== 2) {
3396 pd
= vfp_reg_ptr(true, rd
);
3397 pm
= vfp_reg_ptr(true, rm
);
3401 gen_helper_neon_qunzip8(pd
, pm
);
3404 gen_helper_neon_qunzip16(pd
, pm
);
3407 gen_helper_neon_qunzip32(pd
, pm
);
3415 gen_helper_neon_unzip8(pd
, pm
);
3418 gen_helper_neon_unzip16(pd
, pm
);
3424 tcg_temp_free_ptr(pd
);
3425 tcg_temp_free_ptr(pm
);
3429 static int gen_neon_zip(int rd
, int rm
, int size
, int q
)
3433 if (!q
&& size
== 2) {
3436 pd
= vfp_reg_ptr(true, rd
);
3437 pm
= vfp_reg_ptr(true, rm
);
3441 gen_helper_neon_qzip8(pd
, pm
);
3444 gen_helper_neon_qzip16(pd
, pm
);
3447 gen_helper_neon_qzip32(pd
, pm
);
3455 gen_helper_neon_zip8(pd
, pm
);
3458 gen_helper_neon_zip16(pd
, pm
);
3464 tcg_temp_free_ptr(pd
);
3465 tcg_temp_free_ptr(pm
);
3469 static void gen_neon_trn_u8(TCGv_i32 t0
, TCGv_i32 t1
)
3473 rd
= tcg_temp_new_i32();
3474 tmp
= tcg_temp_new_i32();
3476 tcg_gen_shli_i32(rd
, t0
, 8);
3477 tcg_gen_andi_i32(rd
, rd
, 0xff00ff00);
3478 tcg_gen_andi_i32(tmp
, t1
, 0x00ff00ff);
3479 tcg_gen_or_i32(rd
, rd
, tmp
);
3481 tcg_gen_shri_i32(t1
, t1
, 8);
3482 tcg_gen_andi_i32(t1
, t1
, 0x00ff00ff);
3483 tcg_gen_andi_i32(tmp
, t0
, 0xff00ff00);
3484 tcg_gen_or_i32(t1
, t1
, tmp
);
3485 tcg_gen_mov_i32(t0
, rd
);
3487 tcg_temp_free_i32(tmp
);
3488 tcg_temp_free_i32(rd
);
3491 static void gen_neon_trn_u16(TCGv_i32 t0
, TCGv_i32 t1
)
3495 rd
= tcg_temp_new_i32();
3496 tmp
= tcg_temp_new_i32();
3498 tcg_gen_shli_i32(rd
, t0
, 16);
3499 tcg_gen_andi_i32(tmp
, t1
, 0xffff);
3500 tcg_gen_or_i32(rd
, rd
, tmp
);
3501 tcg_gen_shri_i32(t1
, t1
, 16);
3502 tcg_gen_andi_i32(tmp
, t0
, 0xffff0000);
3503 tcg_gen_or_i32(t1
, t1
, tmp
);
3504 tcg_gen_mov_i32(t0
, rd
);
3506 tcg_temp_free_i32(tmp
);
3507 tcg_temp_free_i32(rd
);
3515 } const neon_ls_element_type
[11] = {
3529 /* Translate a NEON load/store element instruction. Return nonzero if the
3530 instruction is invalid. */
3531 static int disas_neon_ls_insn(DisasContext
*s
, uint32_t insn
)
3551 /* FIXME: this access check should not take precedence over UNDEF
3552 * for invalid encodings; we will generate incorrect syndrome information
3553 * for attempts to execute invalid vfp/neon encodings with FP disabled.
3555 if (s
->fp_excp_el
) {
3556 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
3557 syn_simd_access_trap(1, 0xe, false), s
->fp_excp_el
);
3561 if (!s
->vfp_enabled
)
3563 VFP_DREG_D(rd
, insn
);
3564 rn
= (insn
>> 16) & 0xf;
3566 load
= (insn
& (1 << 21)) != 0;
3567 endian
= s
->be_data
;
3568 mmu_idx
= get_mem_index(s
);
3569 if ((insn
& (1 << 23)) == 0) {
3570 /* Load store all elements. */
3571 op
= (insn
>> 8) & 0xf;
3572 size
= (insn
>> 6) & 3;
3575 /* Catch UNDEF cases for bad values of align field */
3578 if (((insn
>> 5) & 1) == 1) {
3583 if (((insn
>> 4) & 3) == 3) {
3590 nregs
= neon_ls_element_type
[op
].nregs
;
3591 interleave
= neon_ls_element_type
[op
].interleave
;
3592 spacing
= neon_ls_element_type
[op
].spacing
;
3593 if (size
== 3 && (interleave
| spacing
) != 1) {
3596 /* For our purposes, bytes are always little-endian. */
3600 /* Consecutive little-endian elements from a single register
3601 * can be promoted to a larger little-endian operation.
3603 if (interleave
== 1 && endian
== MO_LE
) {
3606 tmp64
= tcg_temp_new_i64();
3607 addr
= tcg_temp_new_i32();
3608 tmp2
= tcg_const_i32(1 << size
);
3609 load_reg_var(s
, addr
, rn
);
3610 for (reg
= 0; reg
< nregs
; reg
++) {
3611 for (n
= 0; n
< 8 >> size
; n
++) {
3613 for (xs
= 0; xs
< interleave
; xs
++) {
3614 int tt
= rd
+ reg
+ spacing
* xs
;
3617 gen_aa32_ld_i64(s
, tmp64
, addr
, mmu_idx
, endian
| size
);
3618 neon_store_element64(tt
, n
, size
, tmp64
);
3620 neon_load_element64(tmp64
, tt
, n
, size
);
3621 gen_aa32_st_i64(s
, tmp64
, addr
, mmu_idx
, endian
| size
);
3623 tcg_gen_add_i32(addr
, addr
, tmp2
);
3627 tcg_temp_free_i32(addr
);
3628 tcg_temp_free_i32(tmp2
);
3629 tcg_temp_free_i64(tmp64
);
3630 stride
= nregs
* interleave
* 8;
3632 size
= (insn
>> 10) & 3;
3634 /* Load single element to all lanes. */
3635 int a
= (insn
>> 4) & 1;
3639 size
= (insn
>> 6) & 3;
3640 nregs
= ((insn
>> 8) & 3) + 1;
3643 if (nregs
!= 4 || a
== 0) {
3646 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
3649 if (nregs
== 1 && a
== 1 && size
== 0) {
3652 if (nregs
== 3 && a
== 1) {
3655 addr
= tcg_temp_new_i32();
3656 load_reg_var(s
, addr
, rn
);
3658 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write.
3659 * VLD2/3/4 to all lanes: bit 5 indicates register stride.
3661 stride
= (insn
& (1 << 5)) ? 2 : 1;
3662 vec_size
= nregs
== 1 ? stride
* 8 : 8;
3664 tmp
= tcg_temp_new_i32();
3665 for (reg
= 0; reg
< nregs
; reg
++) {
3666 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
),
3668 if ((rd
& 1) && vec_size
== 16) {
3669 /* We cannot write 16 bytes at once because the
3670 * destination is unaligned.
3672 tcg_gen_gvec_dup_i32(size
, neon_reg_offset(rd
, 0),
3674 tcg_gen_gvec_mov(0, neon_reg_offset(rd
+ 1, 0),
3675 neon_reg_offset(rd
, 0), 8, 8);
3677 tcg_gen_gvec_dup_i32(size
, neon_reg_offset(rd
, 0),
3678 vec_size
, vec_size
, tmp
);
3680 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3683 tcg_temp_free_i32(tmp
);
3684 tcg_temp_free_i32(addr
);
3685 stride
= (1 << size
) * nregs
;
3687 /* Single element. */
3688 int idx
= (insn
>> 4) & 0xf;
3692 reg_idx
= (insn
>> 5) & 7;
3696 reg_idx
= (insn
>> 6) & 3;
3697 stride
= (insn
& (1 << 5)) ? 2 : 1;
3700 reg_idx
= (insn
>> 7) & 1;
3701 stride
= (insn
& (1 << 6)) ? 2 : 1;
3706 nregs
= ((insn
>> 8) & 3) + 1;
3707 /* Catch the UNDEF cases. This is unavoidably a bit messy. */
3710 if (((idx
& (1 << size
)) != 0) ||
3711 (size
== 2 && ((idx
& 3) == 1 || (idx
& 3) == 2))) {
3716 if ((idx
& 1) != 0) {
3721 if (size
== 2 && (idx
& 2) != 0) {
3726 if ((size
== 2) && ((idx
& 3) == 3)) {
3733 if ((rd
+ stride
* (nregs
- 1)) > 31) {
3734 /* Attempts to write off the end of the register file
3735 * are UNPREDICTABLE; we choose to UNDEF because otherwise
3736 * the neon_load_reg() would write off the end of the array.
3740 tmp
= tcg_temp_new_i32();
3741 addr
= tcg_temp_new_i32();
3742 load_reg_var(s
, addr
, rn
);
3743 for (reg
= 0; reg
< nregs
; reg
++) {
3745 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
),
3747 neon_store_element(rd
, reg_idx
, size
, tmp
);
3748 } else { /* Store */
3749 neon_load_element(tmp
, rd
, reg_idx
, size
);
3750 gen_aa32_st_i32(s
, tmp
, addr
, get_mem_index(s
),
3754 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3756 tcg_temp_free_i32(addr
);
3757 tcg_temp_free_i32(tmp
);
3758 stride
= nregs
* (1 << size
);
3764 base
= load_reg(s
, rn
);
3766 tcg_gen_addi_i32(base
, base
, stride
);
3769 index
= load_reg(s
, rm
);
3770 tcg_gen_add_i32(base
, base
, index
);
3771 tcg_temp_free_i32(index
);
3773 store_reg(s
, rn
, base
);
3778 static inline void gen_neon_narrow(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3781 case 0: gen_helper_neon_narrow_u8(dest
, src
); break;
3782 case 1: gen_helper_neon_narrow_u16(dest
, src
); break;
3783 case 2: tcg_gen_extrl_i64_i32(dest
, src
); break;
3788 static inline void gen_neon_narrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3791 case 0: gen_helper_neon_narrow_sat_s8(dest
, cpu_env
, src
); break;
3792 case 1: gen_helper_neon_narrow_sat_s16(dest
, cpu_env
, src
); break;
3793 case 2: gen_helper_neon_narrow_sat_s32(dest
, cpu_env
, src
); break;
3798 static inline void gen_neon_narrow_satu(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3801 case 0: gen_helper_neon_narrow_sat_u8(dest
, cpu_env
, src
); break;
3802 case 1: gen_helper_neon_narrow_sat_u16(dest
, cpu_env
, src
); break;
3803 case 2: gen_helper_neon_narrow_sat_u32(dest
, cpu_env
, src
); break;
3808 static inline void gen_neon_unarrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3811 case 0: gen_helper_neon_unarrow_sat8(dest
, cpu_env
, src
); break;
3812 case 1: gen_helper_neon_unarrow_sat16(dest
, cpu_env
, src
); break;
3813 case 2: gen_helper_neon_unarrow_sat32(dest
, cpu_env
, src
); break;
3818 static inline void gen_neon_shift_narrow(int size
, TCGv_i32 var
, TCGv_i32 shift
,
3824 case 1: gen_helper_neon_rshl_u16(var
, var
, shift
); break;
3825 case 2: gen_helper_neon_rshl_u32(var
, var
, shift
); break;
3830 case 1: gen_helper_neon_rshl_s16(var
, var
, shift
); break;
3831 case 2: gen_helper_neon_rshl_s32(var
, var
, shift
); break;
3838 case 1: gen_helper_neon_shl_u16(var
, var
, shift
); break;
3839 case 2: gen_helper_neon_shl_u32(var
, var
, shift
); break;
3844 case 1: gen_helper_neon_shl_s16(var
, var
, shift
); break;
3845 case 2: gen_helper_neon_shl_s32(var
, var
, shift
); break;
3852 static inline void gen_neon_widen(TCGv_i64 dest
, TCGv_i32 src
, int size
, int u
)
3856 case 0: gen_helper_neon_widen_u8(dest
, src
); break;
3857 case 1: gen_helper_neon_widen_u16(dest
, src
); break;
3858 case 2: tcg_gen_extu_i32_i64(dest
, src
); break;
3863 case 0: gen_helper_neon_widen_s8(dest
, src
); break;
3864 case 1: gen_helper_neon_widen_s16(dest
, src
); break;
3865 case 2: tcg_gen_ext_i32_i64(dest
, src
); break;
3869 tcg_temp_free_i32(src
);
3872 static inline void gen_neon_addl(int size
)
3875 case 0: gen_helper_neon_addl_u16(CPU_V001
); break;
3876 case 1: gen_helper_neon_addl_u32(CPU_V001
); break;
3877 case 2: tcg_gen_add_i64(CPU_V001
); break;
3882 static inline void gen_neon_subl(int size
)
3885 case 0: gen_helper_neon_subl_u16(CPU_V001
); break;
3886 case 1: gen_helper_neon_subl_u32(CPU_V001
); break;
3887 case 2: tcg_gen_sub_i64(CPU_V001
); break;
3892 static inline void gen_neon_negl(TCGv_i64 var
, int size
)
3895 case 0: gen_helper_neon_negl_u16(var
, var
); break;
3896 case 1: gen_helper_neon_negl_u32(var
, var
); break;
3898 tcg_gen_neg_i64(var
, var
);
3904 static inline void gen_neon_addl_saturate(TCGv_i64 op0
, TCGv_i64 op1
, int size
)
3907 case 1: gen_helper_neon_addl_saturate_s32(op0
, cpu_env
, op0
, op1
); break;
3908 case 2: gen_helper_neon_addl_saturate_s64(op0
, cpu_env
, op0
, op1
); break;
3913 static inline void gen_neon_mull(TCGv_i64 dest
, TCGv_i32 a
, TCGv_i32 b
,
3918 switch ((size
<< 1) | u
) {
3919 case 0: gen_helper_neon_mull_s8(dest
, a
, b
); break;
3920 case 1: gen_helper_neon_mull_u8(dest
, a
, b
); break;
3921 case 2: gen_helper_neon_mull_s16(dest
, a
, b
); break;
3922 case 3: gen_helper_neon_mull_u16(dest
, a
, b
); break;
3924 tmp
= gen_muls_i64_i32(a
, b
);
3925 tcg_gen_mov_i64(dest
, tmp
);
3926 tcg_temp_free_i64(tmp
);
3929 tmp
= gen_mulu_i64_i32(a
, b
);
3930 tcg_gen_mov_i64(dest
, tmp
);
3931 tcg_temp_free_i64(tmp
);
3936 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
3937 Don't forget to clean them now. */
3939 tcg_temp_free_i32(a
);
3940 tcg_temp_free_i32(b
);
3944 static void gen_neon_narrow_op(int op
, int u
, int size
,
3945 TCGv_i32 dest
, TCGv_i64 src
)
3949 gen_neon_unarrow_sats(size
, dest
, src
);
3951 gen_neon_narrow(size
, dest
, src
);
3955 gen_neon_narrow_satu(size
, dest
, src
);
3957 gen_neon_narrow_sats(size
, dest
, src
);
3962 /* Symbolic constants for op fields for Neon 3-register same-length.
3963 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
3966 #define NEON_3R_VHADD 0
3967 #define NEON_3R_VQADD 1
3968 #define NEON_3R_VRHADD 2
3969 #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
3970 #define NEON_3R_VHSUB 4
3971 #define NEON_3R_VQSUB 5
3972 #define NEON_3R_VCGT 6
3973 #define NEON_3R_VCGE 7
3974 #define NEON_3R_VSHL 8
3975 #define NEON_3R_VQSHL 9
3976 #define NEON_3R_VRSHL 10
3977 #define NEON_3R_VQRSHL 11
3978 #define NEON_3R_VMAX 12
3979 #define NEON_3R_VMIN 13
3980 #define NEON_3R_VABD 14
3981 #define NEON_3R_VABA 15
3982 #define NEON_3R_VADD_VSUB 16
3983 #define NEON_3R_VTST_VCEQ 17
3984 #define NEON_3R_VML 18 /* VMLA, VMLS */
3985 #define NEON_3R_VMUL 19
3986 #define NEON_3R_VPMAX 20
3987 #define NEON_3R_VPMIN 21
3988 #define NEON_3R_VQDMULH_VQRDMULH 22
3989 #define NEON_3R_VPADD_VQRDMLAH 23
3990 #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */
3991 #define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */
3992 #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
3993 #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
3994 #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
3995 #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
3996 #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
3997 #define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
3999 static const uint8_t neon_3r_sizes
[] = {
4000 [NEON_3R_VHADD
] = 0x7,
4001 [NEON_3R_VQADD
] = 0xf,
4002 [NEON_3R_VRHADD
] = 0x7,
4003 [NEON_3R_LOGIC
] = 0xf, /* size field encodes op type */
4004 [NEON_3R_VHSUB
] = 0x7,
4005 [NEON_3R_VQSUB
] = 0xf,
4006 [NEON_3R_VCGT
] = 0x7,
4007 [NEON_3R_VCGE
] = 0x7,
4008 [NEON_3R_VSHL
] = 0xf,
4009 [NEON_3R_VQSHL
] = 0xf,
4010 [NEON_3R_VRSHL
] = 0xf,
4011 [NEON_3R_VQRSHL
] = 0xf,
4012 [NEON_3R_VMAX
] = 0x7,
4013 [NEON_3R_VMIN
] = 0x7,
4014 [NEON_3R_VABD
] = 0x7,
4015 [NEON_3R_VABA
] = 0x7,
4016 [NEON_3R_VADD_VSUB
] = 0xf,
4017 [NEON_3R_VTST_VCEQ
] = 0x7,
4018 [NEON_3R_VML
] = 0x7,
4019 [NEON_3R_VMUL
] = 0x7,
4020 [NEON_3R_VPMAX
] = 0x7,
4021 [NEON_3R_VPMIN
] = 0x7,
4022 [NEON_3R_VQDMULH_VQRDMULH
] = 0x6,
4023 [NEON_3R_VPADD_VQRDMLAH
] = 0x7,
4024 [NEON_3R_SHA
] = 0xf, /* size field encodes op type */
4025 [NEON_3R_VFM_VQRDMLSH
] = 0x7, /* For VFM, size bit 1 encodes op */
4026 [NEON_3R_FLOAT_ARITH
] = 0x5, /* size bit 1 encodes op */
4027 [NEON_3R_FLOAT_MULTIPLY
] = 0x5, /* size bit 1 encodes op */
4028 [NEON_3R_FLOAT_CMP
] = 0x5, /* size bit 1 encodes op */
4029 [NEON_3R_FLOAT_ACMP
] = 0x5, /* size bit 1 encodes op */
4030 [NEON_3R_FLOAT_MINMAX
] = 0x5, /* size bit 1 encodes op */
4031 [NEON_3R_FLOAT_MISC
] = 0x5, /* size bit 1 encodes op */
4034 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
4035 * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
4038 #define NEON_2RM_VREV64 0
4039 #define NEON_2RM_VREV32 1
4040 #define NEON_2RM_VREV16 2
4041 #define NEON_2RM_VPADDL 4
4042 #define NEON_2RM_VPADDL_U 5
4043 #define NEON_2RM_AESE 6 /* Includes AESD */
4044 #define NEON_2RM_AESMC 7 /* Includes AESIMC */
4045 #define NEON_2RM_VCLS 8
4046 #define NEON_2RM_VCLZ 9
4047 #define NEON_2RM_VCNT 10
4048 #define NEON_2RM_VMVN 11
4049 #define NEON_2RM_VPADAL 12
4050 #define NEON_2RM_VPADAL_U 13
4051 #define NEON_2RM_VQABS 14
4052 #define NEON_2RM_VQNEG 15
4053 #define NEON_2RM_VCGT0 16
4054 #define NEON_2RM_VCGE0 17
4055 #define NEON_2RM_VCEQ0 18
4056 #define NEON_2RM_VCLE0 19
4057 #define NEON_2RM_VCLT0 20
4058 #define NEON_2RM_SHA1H 21
4059 #define NEON_2RM_VABS 22
4060 #define NEON_2RM_VNEG 23
4061 #define NEON_2RM_VCGT0_F 24
4062 #define NEON_2RM_VCGE0_F 25
4063 #define NEON_2RM_VCEQ0_F 26
4064 #define NEON_2RM_VCLE0_F 27
4065 #define NEON_2RM_VCLT0_F 28
4066 #define NEON_2RM_VABS_F 30
4067 #define NEON_2RM_VNEG_F 31
4068 #define NEON_2RM_VSWP 32
4069 #define NEON_2RM_VTRN 33
4070 #define NEON_2RM_VUZP 34
4071 #define NEON_2RM_VZIP 35
4072 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
4073 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
4074 #define NEON_2RM_VSHLL 38
4075 #define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */
4076 #define NEON_2RM_VRINTN 40
4077 #define NEON_2RM_VRINTX 41
4078 #define NEON_2RM_VRINTA 42
4079 #define NEON_2RM_VRINTZ 43
4080 #define NEON_2RM_VCVT_F16_F32 44
4081 #define NEON_2RM_VRINTM 45
4082 #define NEON_2RM_VCVT_F32_F16 46
4083 #define NEON_2RM_VRINTP 47
4084 #define NEON_2RM_VCVTAU 48
4085 #define NEON_2RM_VCVTAS 49
4086 #define NEON_2RM_VCVTNU 50
4087 #define NEON_2RM_VCVTNS 51
4088 #define NEON_2RM_VCVTPU 52
4089 #define NEON_2RM_VCVTPS 53
4090 #define NEON_2RM_VCVTMU 54
4091 #define NEON_2RM_VCVTMS 55
4092 #define NEON_2RM_VRECPE 56
4093 #define NEON_2RM_VRSQRTE 57
4094 #define NEON_2RM_VRECPE_F 58
4095 #define NEON_2RM_VRSQRTE_F 59
4096 #define NEON_2RM_VCVT_FS 60
4097 #define NEON_2RM_VCVT_FU 61
4098 #define NEON_2RM_VCVT_SF 62
4099 #define NEON_2RM_VCVT_UF 63
4101 static bool neon_2rm_is_v8_op(int op
)
4103 /* Return true if this neon 2reg-misc op is ARMv8 and up */
4105 case NEON_2RM_VRINTN
:
4106 case NEON_2RM_VRINTA
:
4107 case NEON_2RM_VRINTM
:
4108 case NEON_2RM_VRINTP
:
4109 case NEON_2RM_VRINTZ
:
4110 case NEON_2RM_VRINTX
:
4111 case NEON_2RM_VCVTAU
:
4112 case NEON_2RM_VCVTAS
:
4113 case NEON_2RM_VCVTNU
:
4114 case NEON_2RM_VCVTNS
:
4115 case NEON_2RM_VCVTPU
:
4116 case NEON_2RM_VCVTPS
:
4117 case NEON_2RM_VCVTMU
:
4118 case NEON_2RM_VCVTMS
:
4125 /* Each entry in this array has bit n set if the insn allows
4126 * size value n (otherwise it will UNDEF). Since unallocated
4127 * op values will have no bits set they always UNDEF.
4129 static const uint8_t neon_2rm_sizes
[] = {
4130 [NEON_2RM_VREV64
] = 0x7,
4131 [NEON_2RM_VREV32
] = 0x3,
4132 [NEON_2RM_VREV16
] = 0x1,
4133 [NEON_2RM_VPADDL
] = 0x7,
4134 [NEON_2RM_VPADDL_U
] = 0x7,
4135 [NEON_2RM_AESE
] = 0x1,
4136 [NEON_2RM_AESMC
] = 0x1,
4137 [NEON_2RM_VCLS
] = 0x7,
4138 [NEON_2RM_VCLZ
] = 0x7,
4139 [NEON_2RM_VCNT
] = 0x1,
4140 [NEON_2RM_VMVN
] = 0x1,
4141 [NEON_2RM_VPADAL
] = 0x7,
4142 [NEON_2RM_VPADAL_U
] = 0x7,
4143 [NEON_2RM_VQABS
] = 0x7,
4144 [NEON_2RM_VQNEG
] = 0x7,
4145 [NEON_2RM_VCGT0
] = 0x7,
4146 [NEON_2RM_VCGE0
] = 0x7,
4147 [NEON_2RM_VCEQ0
] = 0x7,
4148 [NEON_2RM_VCLE0
] = 0x7,
4149 [NEON_2RM_VCLT0
] = 0x7,
4150 [NEON_2RM_SHA1H
] = 0x4,
4151 [NEON_2RM_VABS
] = 0x7,
4152 [NEON_2RM_VNEG
] = 0x7,
4153 [NEON_2RM_VCGT0_F
] = 0x4,
4154 [NEON_2RM_VCGE0_F
] = 0x4,
4155 [NEON_2RM_VCEQ0_F
] = 0x4,
4156 [NEON_2RM_VCLE0_F
] = 0x4,
4157 [NEON_2RM_VCLT0_F
] = 0x4,
4158 [NEON_2RM_VABS_F
] = 0x4,
4159 [NEON_2RM_VNEG_F
] = 0x4,
4160 [NEON_2RM_VSWP
] = 0x1,
4161 [NEON_2RM_VTRN
] = 0x7,
4162 [NEON_2RM_VUZP
] = 0x7,
4163 [NEON_2RM_VZIP
] = 0x7,
4164 [NEON_2RM_VMOVN
] = 0x7,
4165 [NEON_2RM_VQMOVN
] = 0x7,
4166 [NEON_2RM_VSHLL
] = 0x7,
4167 [NEON_2RM_SHA1SU1
] = 0x4,
4168 [NEON_2RM_VRINTN
] = 0x4,
4169 [NEON_2RM_VRINTX
] = 0x4,
4170 [NEON_2RM_VRINTA
] = 0x4,
4171 [NEON_2RM_VRINTZ
] = 0x4,
4172 [NEON_2RM_VCVT_F16_F32
] = 0x2,
4173 [NEON_2RM_VRINTM
] = 0x4,
4174 [NEON_2RM_VCVT_F32_F16
] = 0x2,
4175 [NEON_2RM_VRINTP
] = 0x4,
4176 [NEON_2RM_VCVTAU
] = 0x4,
4177 [NEON_2RM_VCVTAS
] = 0x4,
4178 [NEON_2RM_VCVTNU
] = 0x4,
4179 [NEON_2RM_VCVTNS
] = 0x4,
4180 [NEON_2RM_VCVTPU
] = 0x4,
4181 [NEON_2RM_VCVTPS
] = 0x4,
4182 [NEON_2RM_VCVTMU
] = 0x4,
4183 [NEON_2RM_VCVTMS
] = 0x4,
4184 [NEON_2RM_VRECPE
] = 0x4,
4185 [NEON_2RM_VRSQRTE
] = 0x4,
4186 [NEON_2RM_VRECPE_F
] = 0x4,
4187 [NEON_2RM_VRSQRTE_F
] = 0x4,
4188 [NEON_2RM_VCVT_FS
] = 0x4,
4189 [NEON_2RM_VCVT_FU
] = 0x4,
4190 [NEON_2RM_VCVT_SF
] = 0x4,
4191 [NEON_2RM_VCVT_UF
] = 0x4,
4195 /* Expand v8.1 simd helper. */
4196 static int do_v81_helper(DisasContext
*s
, gen_helper_gvec_3_ptr
*fn
,
4197 int q
, int rd
, int rn
, int rm
)
4199 if (dc_isar_feature(aa32_rdm
, s
)) {
4200 int opr_sz
= (1 + q
) * 8;
4201 tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd
),
4202 vfp_reg_offset(1, rn
),
4203 vfp_reg_offset(1, rm
), cpu_env
,
4204 opr_sz
, opr_sz
, 0, fn
);
4210 static void gen_ssra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4212 tcg_gen_vec_sar8i_i64(a
, a
, shift
);
4213 tcg_gen_vec_add8_i64(d
, d
, a
);
4216 static void gen_ssra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4218 tcg_gen_vec_sar16i_i64(a
, a
, shift
);
4219 tcg_gen_vec_add16_i64(d
, d
, a
);
4222 static void gen_ssra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
4224 tcg_gen_sari_i32(a
, a
, shift
);
4225 tcg_gen_add_i32(d
, d
, a
);
4228 static void gen_ssra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4230 tcg_gen_sari_i64(a
, a
, shift
);
4231 tcg_gen_add_i64(d
, d
, a
);
4234 static void gen_ssra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4236 tcg_gen_sari_vec(vece
, a
, a
, sh
);
4237 tcg_gen_add_vec(vece
, d
, d
, a
);
4240 static const TCGOpcode vecop_list_ssra
[] = {
4241 INDEX_op_sari_vec
, INDEX_op_add_vec
, 0
4244 const GVecGen2i ssra_op
[4] = {
4245 { .fni8
= gen_ssra8_i64
,
4246 .fniv
= gen_ssra_vec
,
4248 .opt_opc
= vecop_list_ssra
,
4250 { .fni8
= gen_ssra16_i64
,
4251 .fniv
= gen_ssra_vec
,
4253 .opt_opc
= vecop_list_ssra
,
4255 { .fni4
= gen_ssra32_i32
,
4256 .fniv
= gen_ssra_vec
,
4258 .opt_opc
= vecop_list_ssra
,
4260 { .fni8
= gen_ssra64_i64
,
4261 .fniv
= gen_ssra_vec
,
4262 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4263 .opt_opc
= vecop_list_ssra
,
4268 static void gen_usra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4270 tcg_gen_vec_shr8i_i64(a
, a
, shift
);
4271 tcg_gen_vec_add8_i64(d
, d
, a
);
4274 static void gen_usra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4276 tcg_gen_vec_shr16i_i64(a
, a
, shift
);
4277 tcg_gen_vec_add16_i64(d
, d
, a
);
4280 static void gen_usra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
4282 tcg_gen_shri_i32(a
, a
, shift
);
4283 tcg_gen_add_i32(d
, d
, a
);
4286 static void gen_usra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4288 tcg_gen_shri_i64(a
, a
, shift
);
4289 tcg_gen_add_i64(d
, d
, a
);
4292 static void gen_usra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4294 tcg_gen_shri_vec(vece
, a
, a
, sh
);
4295 tcg_gen_add_vec(vece
, d
, d
, a
);
4298 static const TCGOpcode vecop_list_usra
[] = {
4299 INDEX_op_shri_vec
, INDEX_op_add_vec
, 0
4302 const GVecGen2i usra_op
[4] = {
4303 { .fni8
= gen_usra8_i64
,
4304 .fniv
= gen_usra_vec
,
4306 .opt_opc
= vecop_list_usra
,
4308 { .fni8
= gen_usra16_i64
,
4309 .fniv
= gen_usra_vec
,
4311 .opt_opc
= vecop_list_usra
,
4313 { .fni4
= gen_usra32_i32
,
4314 .fniv
= gen_usra_vec
,
4316 .opt_opc
= vecop_list_usra
,
4318 { .fni8
= gen_usra64_i64
,
4319 .fniv
= gen_usra_vec
,
4320 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4322 .opt_opc
= vecop_list_usra
,
4326 static void gen_shr8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4328 uint64_t mask
= dup_const(MO_8
, 0xff >> shift
);
4329 TCGv_i64 t
= tcg_temp_new_i64();
4331 tcg_gen_shri_i64(t
, a
, shift
);
4332 tcg_gen_andi_i64(t
, t
, mask
);
4333 tcg_gen_andi_i64(d
, d
, ~mask
);
4334 tcg_gen_or_i64(d
, d
, t
);
4335 tcg_temp_free_i64(t
);
4338 static void gen_shr16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4340 uint64_t mask
= dup_const(MO_16
, 0xffff >> shift
);
4341 TCGv_i64 t
= tcg_temp_new_i64();
4343 tcg_gen_shri_i64(t
, a
, shift
);
4344 tcg_gen_andi_i64(t
, t
, mask
);
4345 tcg_gen_andi_i64(d
, d
, ~mask
);
4346 tcg_gen_or_i64(d
, d
, t
);
4347 tcg_temp_free_i64(t
);
4350 static void gen_shr32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
4352 tcg_gen_shri_i32(a
, a
, shift
);
4353 tcg_gen_deposit_i32(d
, d
, a
, 0, 32 - shift
);
4356 static void gen_shr64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4358 tcg_gen_shri_i64(a
, a
, shift
);
4359 tcg_gen_deposit_i64(d
, d
, a
, 0, 64 - shift
);
4362 static void gen_shr_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4365 tcg_gen_mov_vec(d
, a
);
4367 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4368 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
4370 tcg_gen_dupi_vec(vece
, m
, MAKE_64BIT_MASK((8 << vece
) - sh
, sh
));
4371 tcg_gen_shri_vec(vece
, t
, a
, sh
);
4372 tcg_gen_and_vec(vece
, d
, d
, m
);
4373 tcg_gen_or_vec(vece
, d
, d
, t
);
4375 tcg_temp_free_vec(t
);
4376 tcg_temp_free_vec(m
);
4380 static const TCGOpcode vecop_list_sri
[] = { INDEX_op_shri_vec
, 0 };
4382 const GVecGen2i sri_op
[4] = {
4383 { .fni8
= gen_shr8_ins_i64
,
4384 .fniv
= gen_shr_ins_vec
,
4386 .opt_opc
= vecop_list_sri
,
4388 { .fni8
= gen_shr16_ins_i64
,
4389 .fniv
= gen_shr_ins_vec
,
4391 .opt_opc
= vecop_list_sri
,
4393 { .fni4
= gen_shr32_ins_i32
,
4394 .fniv
= gen_shr_ins_vec
,
4396 .opt_opc
= vecop_list_sri
,
4398 { .fni8
= gen_shr64_ins_i64
,
4399 .fniv
= gen_shr_ins_vec
,
4400 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4402 .opt_opc
= vecop_list_sri
,
4406 static void gen_shl8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4408 uint64_t mask
= dup_const(MO_8
, 0xff << shift
);
4409 TCGv_i64 t
= tcg_temp_new_i64();
4411 tcg_gen_shli_i64(t
, a
, shift
);
4412 tcg_gen_andi_i64(t
, t
, mask
);
4413 tcg_gen_andi_i64(d
, d
, ~mask
);
4414 tcg_gen_or_i64(d
, d
, t
);
4415 tcg_temp_free_i64(t
);
4418 static void gen_shl16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4420 uint64_t mask
= dup_const(MO_16
, 0xffff << shift
);
4421 TCGv_i64 t
= tcg_temp_new_i64();
4423 tcg_gen_shli_i64(t
, a
, shift
);
4424 tcg_gen_andi_i64(t
, t
, mask
);
4425 tcg_gen_andi_i64(d
, d
, ~mask
);
4426 tcg_gen_or_i64(d
, d
, t
);
4427 tcg_temp_free_i64(t
);
4430 static void gen_shl32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
4432 tcg_gen_deposit_i32(d
, d
, a
, shift
, 32 - shift
);
4435 static void gen_shl64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4437 tcg_gen_deposit_i64(d
, d
, a
, shift
, 64 - shift
);
4440 static void gen_shl_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4443 tcg_gen_mov_vec(d
, a
);
4445 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4446 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
4448 tcg_gen_dupi_vec(vece
, m
, MAKE_64BIT_MASK(0, sh
));
4449 tcg_gen_shli_vec(vece
, t
, a
, sh
);
4450 tcg_gen_and_vec(vece
, d
, d
, m
);
4451 tcg_gen_or_vec(vece
, d
, d
, t
);
4453 tcg_temp_free_vec(t
);
4454 tcg_temp_free_vec(m
);
4458 static const TCGOpcode vecop_list_sli
[] = { INDEX_op_shli_vec
, 0 };
4460 const GVecGen2i sli_op
[4] = {
4461 { .fni8
= gen_shl8_ins_i64
,
4462 .fniv
= gen_shl_ins_vec
,
4464 .opt_opc
= vecop_list_sli
,
4466 { .fni8
= gen_shl16_ins_i64
,
4467 .fniv
= gen_shl_ins_vec
,
4469 .opt_opc
= vecop_list_sli
,
4471 { .fni4
= gen_shl32_ins_i32
,
4472 .fniv
= gen_shl_ins_vec
,
4474 .opt_opc
= vecop_list_sli
,
4476 { .fni8
= gen_shl64_ins_i64
,
4477 .fniv
= gen_shl_ins_vec
,
4478 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4480 .opt_opc
= vecop_list_sli
,
4484 static void gen_mla8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4486 gen_helper_neon_mul_u8(a
, a
, b
);
4487 gen_helper_neon_add_u8(d
, d
, a
);
4490 static void gen_mls8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4492 gen_helper_neon_mul_u8(a
, a
, b
);
4493 gen_helper_neon_sub_u8(d
, d
, a
);
4496 static void gen_mla16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4498 gen_helper_neon_mul_u16(a
, a
, b
);
4499 gen_helper_neon_add_u16(d
, d
, a
);
4502 static void gen_mls16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4504 gen_helper_neon_mul_u16(a
, a
, b
);
4505 gen_helper_neon_sub_u16(d
, d
, a
);
4508 static void gen_mla32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4510 tcg_gen_mul_i32(a
, a
, b
);
4511 tcg_gen_add_i32(d
, d
, a
);
4514 static void gen_mls32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4516 tcg_gen_mul_i32(a
, a
, b
);
4517 tcg_gen_sub_i32(d
, d
, a
);
4520 static void gen_mla64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
4522 tcg_gen_mul_i64(a
, a
, b
);
4523 tcg_gen_add_i64(d
, d
, a
);
4526 static void gen_mls64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
4528 tcg_gen_mul_i64(a
, a
, b
);
4529 tcg_gen_sub_i64(d
, d
, a
);
4532 static void gen_mla_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
4534 tcg_gen_mul_vec(vece
, a
, a
, b
);
4535 tcg_gen_add_vec(vece
, d
, d
, a
);
4538 static void gen_mls_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
4540 tcg_gen_mul_vec(vece
, a
, a
, b
);
4541 tcg_gen_sub_vec(vece
, d
, d
, a
);
4544 /* Note that while NEON does not support VMLA and VMLS as 64-bit ops,
4545 * these tables are shared with AArch64 which does support them.
4548 static const TCGOpcode vecop_list_mla
[] = {
4549 INDEX_op_mul_vec
, INDEX_op_add_vec
, 0
4552 static const TCGOpcode vecop_list_mls
[] = {
4553 INDEX_op_mul_vec
, INDEX_op_sub_vec
, 0
4556 const GVecGen3 mla_op
[4] = {
4557 { .fni4
= gen_mla8_i32
,
4558 .fniv
= gen_mla_vec
,
4560 .opt_opc
= vecop_list_mla
,
4562 { .fni4
= gen_mla16_i32
,
4563 .fniv
= gen_mla_vec
,
4565 .opt_opc
= vecop_list_mla
,
4567 { .fni4
= gen_mla32_i32
,
4568 .fniv
= gen_mla_vec
,
4570 .opt_opc
= vecop_list_mla
,
4572 { .fni8
= gen_mla64_i64
,
4573 .fniv
= gen_mla_vec
,
4574 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4576 .opt_opc
= vecop_list_mla
,
4580 const GVecGen3 mls_op
[4] = {
4581 { .fni4
= gen_mls8_i32
,
4582 .fniv
= gen_mls_vec
,
4584 .opt_opc
= vecop_list_mls
,
4586 { .fni4
= gen_mls16_i32
,
4587 .fniv
= gen_mls_vec
,
4589 .opt_opc
= vecop_list_mls
,
4591 { .fni4
= gen_mls32_i32
,
4592 .fniv
= gen_mls_vec
,
4594 .opt_opc
= vecop_list_mls
,
4596 { .fni8
= gen_mls64_i64
,
4597 .fniv
= gen_mls_vec
,
4598 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4600 .opt_opc
= vecop_list_mls
,
4604 /* CMTST : test is "if (X & Y != 0)". */
4605 static void gen_cmtst_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4607 tcg_gen_and_i32(d
, a
, b
);
4608 tcg_gen_setcondi_i32(TCG_COND_NE
, d
, d
, 0);
4609 tcg_gen_neg_i32(d
, d
);
4612 void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
4614 tcg_gen_and_i64(d
, a
, b
);
4615 tcg_gen_setcondi_i64(TCG_COND_NE
, d
, d
, 0);
4616 tcg_gen_neg_i64(d
, d
);
4619 static void gen_cmtst_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
4621 tcg_gen_and_vec(vece
, d
, a
, b
);
4622 tcg_gen_dupi_vec(vece
, a
, 0);
4623 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, d
, d
, a
);
4626 static const TCGOpcode vecop_list_cmtst
[] = { INDEX_op_cmp_vec
, 0 };
4628 const GVecGen3 cmtst_op
[4] = {
4629 { .fni4
= gen_helper_neon_tst_u8
,
4630 .fniv
= gen_cmtst_vec
,
4631 .opt_opc
= vecop_list_cmtst
,
4633 { .fni4
= gen_helper_neon_tst_u16
,
4634 .fniv
= gen_cmtst_vec
,
4635 .opt_opc
= vecop_list_cmtst
,
4637 { .fni4
= gen_cmtst_i32
,
4638 .fniv
= gen_cmtst_vec
,
4639 .opt_opc
= vecop_list_cmtst
,
4641 { .fni8
= gen_cmtst_i64
,
4642 .fniv
= gen_cmtst_vec
,
4643 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4644 .opt_opc
= vecop_list_cmtst
,
4648 static void gen_uqadd_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
4649 TCGv_vec a
, TCGv_vec b
)
4651 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
4652 tcg_gen_add_vec(vece
, x
, a
, b
);
4653 tcg_gen_usadd_vec(vece
, t
, a
, b
);
4654 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
4655 tcg_gen_or_vec(vece
, sat
, sat
, x
);
4656 tcg_temp_free_vec(x
);
4659 static const TCGOpcode vecop_list_uqadd
[] = {
4660 INDEX_op_usadd_vec
, INDEX_op_cmp_vec
, INDEX_op_add_vec
, 0
4663 const GVecGen4 uqadd_op
[4] = {
4664 { .fniv
= gen_uqadd_vec
,
4665 .fno
= gen_helper_gvec_uqadd_b
,
4667 .opt_opc
= vecop_list_uqadd
,
4669 { .fniv
= gen_uqadd_vec
,
4670 .fno
= gen_helper_gvec_uqadd_h
,
4672 .opt_opc
= vecop_list_uqadd
,
4674 { .fniv
= gen_uqadd_vec
,
4675 .fno
= gen_helper_gvec_uqadd_s
,
4677 .opt_opc
= vecop_list_uqadd
,
4679 { .fniv
= gen_uqadd_vec
,
4680 .fno
= gen_helper_gvec_uqadd_d
,
4682 .opt_opc
= vecop_list_uqadd
,
4686 static void gen_sqadd_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
4687 TCGv_vec a
, TCGv_vec b
)
4689 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
4690 tcg_gen_add_vec(vece
, x
, a
, b
);
4691 tcg_gen_ssadd_vec(vece
, t
, a
, b
);
4692 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
4693 tcg_gen_or_vec(vece
, sat
, sat
, x
);
4694 tcg_temp_free_vec(x
);
4697 static const TCGOpcode vecop_list_sqadd
[] = {
4698 INDEX_op_ssadd_vec
, INDEX_op_cmp_vec
, INDEX_op_add_vec
, 0
4701 const GVecGen4 sqadd_op
[4] = {
4702 { .fniv
= gen_sqadd_vec
,
4703 .fno
= gen_helper_gvec_sqadd_b
,
4704 .opt_opc
= vecop_list_sqadd
,
4707 { .fniv
= gen_sqadd_vec
,
4708 .fno
= gen_helper_gvec_sqadd_h
,
4709 .opt_opc
= vecop_list_sqadd
,
4712 { .fniv
= gen_sqadd_vec
,
4713 .fno
= gen_helper_gvec_sqadd_s
,
4714 .opt_opc
= vecop_list_sqadd
,
4717 { .fniv
= gen_sqadd_vec
,
4718 .fno
= gen_helper_gvec_sqadd_d
,
4719 .opt_opc
= vecop_list_sqadd
,
4724 static void gen_uqsub_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
4725 TCGv_vec a
, TCGv_vec b
)
4727 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
4728 tcg_gen_sub_vec(vece
, x
, a
, b
);
4729 tcg_gen_ussub_vec(vece
, t
, a
, b
);
4730 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
4731 tcg_gen_or_vec(vece
, sat
, sat
, x
);
4732 tcg_temp_free_vec(x
);
4735 static const TCGOpcode vecop_list_uqsub
[] = {
4736 INDEX_op_ussub_vec
, INDEX_op_cmp_vec
, INDEX_op_sub_vec
, 0
4739 const GVecGen4 uqsub_op
[4] = {
4740 { .fniv
= gen_uqsub_vec
,
4741 .fno
= gen_helper_gvec_uqsub_b
,
4742 .opt_opc
= vecop_list_uqsub
,
4745 { .fniv
= gen_uqsub_vec
,
4746 .fno
= gen_helper_gvec_uqsub_h
,
4747 .opt_opc
= vecop_list_uqsub
,
4750 { .fniv
= gen_uqsub_vec
,
4751 .fno
= gen_helper_gvec_uqsub_s
,
4752 .opt_opc
= vecop_list_uqsub
,
4755 { .fniv
= gen_uqsub_vec
,
4756 .fno
= gen_helper_gvec_uqsub_d
,
4757 .opt_opc
= vecop_list_uqsub
,
4762 static void gen_sqsub_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
4763 TCGv_vec a
, TCGv_vec b
)
4765 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
4766 tcg_gen_sub_vec(vece
, x
, a
, b
);
4767 tcg_gen_sssub_vec(vece
, t
, a
, b
);
4768 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
4769 tcg_gen_or_vec(vece
, sat
, sat
, x
);
4770 tcg_temp_free_vec(x
);
4773 static const TCGOpcode vecop_list_sqsub
[] = {
4774 INDEX_op_sssub_vec
, INDEX_op_cmp_vec
, INDEX_op_sub_vec
, 0
4777 const GVecGen4 sqsub_op
[4] = {
4778 { .fniv
= gen_sqsub_vec
,
4779 .fno
= gen_helper_gvec_sqsub_b
,
4780 .opt_opc
= vecop_list_sqsub
,
4783 { .fniv
= gen_sqsub_vec
,
4784 .fno
= gen_helper_gvec_sqsub_h
,
4785 .opt_opc
= vecop_list_sqsub
,
4788 { .fniv
= gen_sqsub_vec
,
4789 .fno
= gen_helper_gvec_sqsub_s
,
4790 .opt_opc
= vecop_list_sqsub
,
4793 { .fniv
= gen_sqsub_vec
,
4794 .fno
= gen_helper_gvec_sqsub_d
,
4795 .opt_opc
= vecop_list_sqsub
,
4800 /* Translate a NEON data processing instruction. Return nonzero if the
4801 instruction is invalid.
4802 We process data in a mixture of 32-bit and 64-bit chunks.
4803 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4805 static int disas_neon_data_insn(DisasContext
*s
, uint32_t insn
)
4809 int rd
, rn
, rm
, rd_ofs
, rn_ofs
, rm_ofs
;
4818 TCGv_i32 tmp
, tmp2
, tmp3
, tmp4
, tmp5
;
4819 TCGv_ptr ptr1
, ptr2
, ptr3
;
4822 /* FIXME: this access check should not take precedence over UNDEF
4823 * for invalid encodings; we will generate incorrect syndrome information
4824 * for attempts to execute invalid vfp/neon encodings with FP disabled.
4826 if (s
->fp_excp_el
) {
4827 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
4828 syn_simd_access_trap(1, 0xe, false), s
->fp_excp_el
);
4832 if (!s
->vfp_enabled
)
4834 q
= (insn
& (1 << 6)) != 0;
4835 u
= (insn
>> 24) & 1;
4836 VFP_DREG_D(rd
, insn
);
4837 VFP_DREG_N(rn
, insn
);
4838 VFP_DREG_M(rm
, insn
);
4839 size
= (insn
>> 20) & 3;
4840 vec_size
= q
? 16 : 8;
4841 rd_ofs
= neon_reg_offset(rd
, 0);
4842 rn_ofs
= neon_reg_offset(rn
, 0);
4843 rm_ofs
= neon_reg_offset(rm
, 0);
4845 if ((insn
& (1 << 23)) == 0) {
4846 /* Three register same length. */
4847 op
= ((insn
>> 7) & 0x1e) | ((insn
>> 4) & 1);
4848 /* Catch invalid op and bad size combinations: UNDEF */
4849 if ((neon_3r_sizes
[op
] & (1 << size
)) == 0) {
4852 /* All insns of this form UNDEF for either this condition or the
4853 * superset of cases "Q==1"; we catch the latter later.
4855 if (q
&& ((rd
| rn
| rm
) & 1)) {
4860 /* The SHA-1/SHA-256 3-register instructions require special
4861 * treatment here, as their size field is overloaded as an
4862 * op type selector, and they all consume their input in a
4868 if (!u
) { /* SHA-1 */
4869 if (!dc_isar_feature(aa32_sha1
, s
)) {
4872 ptr1
= vfp_reg_ptr(true, rd
);
4873 ptr2
= vfp_reg_ptr(true, rn
);
4874 ptr3
= vfp_reg_ptr(true, rm
);
4875 tmp4
= tcg_const_i32(size
);
4876 gen_helper_crypto_sha1_3reg(ptr1
, ptr2
, ptr3
, tmp4
);
4877 tcg_temp_free_i32(tmp4
);
4878 } else { /* SHA-256 */
4879 if (!dc_isar_feature(aa32_sha2
, s
) || size
== 3) {
4882 ptr1
= vfp_reg_ptr(true, rd
);
4883 ptr2
= vfp_reg_ptr(true, rn
);
4884 ptr3
= vfp_reg_ptr(true, rm
);
4887 gen_helper_crypto_sha256h(ptr1
, ptr2
, ptr3
);
4890 gen_helper_crypto_sha256h2(ptr1
, ptr2
, ptr3
);
4893 gen_helper_crypto_sha256su1(ptr1
, ptr2
, ptr3
);
4897 tcg_temp_free_ptr(ptr1
);
4898 tcg_temp_free_ptr(ptr2
);
4899 tcg_temp_free_ptr(ptr3
);
4902 case NEON_3R_VPADD_VQRDMLAH
:
4909 return do_v81_helper(s
, gen_helper_gvec_qrdmlah_s16
,
4912 return do_v81_helper(s
, gen_helper_gvec_qrdmlah_s32
,
4917 case NEON_3R_VFM_VQRDMLSH
:
4928 return do_v81_helper(s
, gen_helper_gvec_qrdmlsh_s16
,
4931 return do_v81_helper(s
, gen_helper_gvec_qrdmlsh_s32
,
4936 case NEON_3R_LOGIC
: /* Logic ops. */
4937 switch ((u
<< 2) | size
) {
4939 tcg_gen_gvec_and(0, rd_ofs
, rn_ofs
, rm_ofs
,
4940 vec_size
, vec_size
);
4943 tcg_gen_gvec_andc(0, rd_ofs
, rn_ofs
, rm_ofs
,
4944 vec_size
, vec_size
);
4947 tcg_gen_gvec_or(0, rd_ofs
, rn_ofs
, rm_ofs
,
4948 vec_size
, vec_size
);
4951 tcg_gen_gvec_orc(0, rd_ofs
, rn_ofs
, rm_ofs
,
4952 vec_size
, vec_size
);
4955 tcg_gen_gvec_xor(0, rd_ofs
, rn_ofs
, rm_ofs
,
4956 vec_size
, vec_size
);
4959 tcg_gen_gvec_bitsel(MO_8
, rd_ofs
, rd_ofs
, rn_ofs
, rm_ofs
,
4960 vec_size
, vec_size
);
4963 tcg_gen_gvec_bitsel(MO_8
, rd_ofs
, rm_ofs
, rn_ofs
, rd_ofs
,
4964 vec_size
, vec_size
);
4967 tcg_gen_gvec_bitsel(MO_8
, rd_ofs
, rm_ofs
, rd_ofs
, rn_ofs
,
4968 vec_size
, vec_size
);
4973 case NEON_3R_VADD_VSUB
:
4975 tcg_gen_gvec_sub(size
, rd_ofs
, rn_ofs
, rm_ofs
,
4976 vec_size
, vec_size
);
4978 tcg_gen_gvec_add(size
, rd_ofs
, rn_ofs
, rm_ofs
,
4979 vec_size
, vec_size
);
4984 tcg_gen_gvec_4(rd_ofs
, offsetof(CPUARMState
, vfp
.qc
),
4985 rn_ofs
, rm_ofs
, vec_size
, vec_size
,
4986 (u
? uqadd_op
: sqadd_op
) + size
);
4990 tcg_gen_gvec_4(rd_ofs
, offsetof(CPUARMState
, vfp
.qc
),
4991 rn_ofs
, rm_ofs
, vec_size
, vec_size
,
4992 (u
? uqsub_op
: sqsub_op
) + size
);
4995 case NEON_3R_VMUL
: /* VMUL */
4997 /* Polynomial case allows only P8 and is handled below. */
5002 tcg_gen_gvec_mul(size
, rd_ofs
, rn_ofs
, rm_ofs
,
5003 vec_size
, vec_size
);
5008 case NEON_3R_VML
: /* VMLA, VMLS */
5009 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, vec_size
, vec_size
,
5010 u
? &mls_op
[size
] : &mla_op
[size
]);
5013 case NEON_3R_VTST_VCEQ
:
5015 tcg_gen_gvec_cmp(TCG_COND_EQ
, size
, rd_ofs
, rn_ofs
, rm_ofs
,
5016 vec_size
, vec_size
);
5018 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
,
5019 vec_size
, vec_size
, &cmtst_op
[size
]);
5024 tcg_gen_gvec_cmp(u
? TCG_COND_GTU
: TCG_COND_GT
, size
,
5025 rd_ofs
, rn_ofs
, rm_ofs
, vec_size
, vec_size
);
5029 tcg_gen_gvec_cmp(u
? TCG_COND_GEU
: TCG_COND_GE
, size
,
5030 rd_ofs
, rn_ofs
, rm_ofs
, vec_size
, vec_size
);
5035 tcg_gen_gvec_umax(size
, rd_ofs
, rn_ofs
, rm_ofs
,
5036 vec_size
, vec_size
);
5038 tcg_gen_gvec_smax(size
, rd_ofs
, rn_ofs
, rm_ofs
,
5039 vec_size
, vec_size
);
5044 tcg_gen_gvec_umin(size
, rd_ofs
, rn_ofs
, rm_ofs
,
5045 vec_size
, vec_size
);
5047 tcg_gen_gvec_smin(size
, rd_ofs
, rn_ofs
, rm_ofs
,
5048 vec_size
, vec_size
);
5054 /* 64-bit element instructions. */
5055 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
5056 neon_load_reg64(cpu_V0
, rn
+ pass
);
5057 neon_load_reg64(cpu_V1
, rm
+ pass
);
5061 gen_helper_neon_shl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
5063 gen_helper_neon_shl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
5068 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
5071 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
5077 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
5079 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
5082 case NEON_3R_VQRSHL
:
5084 gen_helper_neon_qrshl_u64(cpu_V0
, cpu_env
,
5087 gen_helper_neon_qrshl_s64(cpu_V0
, cpu_env
,
5094 neon_store_reg64(cpu_V0
, rd
+ pass
);
5103 case NEON_3R_VQRSHL
:
5106 /* Shift instruction operands are reversed. */
5112 case NEON_3R_VPADD_VQRDMLAH
:
5117 case NEON_3R_FLOAT_ARITH
:
5118 pairwise
= (u
&& size
< 2); /* if VPADD (float) */
5120 case NEON_3R_FLOAT_MINMAX
:
5121 pairwise
= u
; /* if VPMIN/VPMAX (float) */
5123 case NEON_3R_FLOAT_CMP
:
5125 /* no encoding for U=0 C=1x */
5129 case NEON_3R_FLOAT_ACMP
:
5134 case NEON_3R_FLOAT_MISC
:
5135 /* VMAXNM/VMINNM in ARMv8 */
5136 if (u
&& !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
5140 case NEON_3R_VFM_VQRDMLSH
:
5141 if (!arm_dc_feature(s
, ARM_FEATURE_VFP4
)) {
5149 if (pairwise
&& q
) {
5150 /* All the pairwise insns UNDEF if Q is set */
5154 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5159 tmp
= neon_load_reg(rn
, 0);
5160 tmp2
= neon_load_reg(rn
, 1);
5162 tmp
= neon_load_reg(rm
, 0);
5163 tmp2
= neon_load_reg(rm
, 1);
5167 tmp
= neon_load_reg(rn
, pass
);
5168 tmp2
= neon_load_reg(rm
, pass
);
5172 GEN_NEON_INTEGER_OP(hadd
);
5174 case NEON_3R_VRHADD
:
5175 GEN_NEON_INTEGER_OP(rhadd
);
5178 GEN_NEON_INTEGER_OP(hsub
);
5181 GEN_NEON_INTEGER_OP(shl
);
5184 GEN_NEON_INTEGER_OP_ENV(qshl
);
5187 GEN_NEON_INTEGER_OP(rshl
);
5189 case NEON_3R_VQRSHL
:
5190 GEN_NEON_INTEGER_OP_ENV(qrshl
);
5193 GEN_NEON_INTEGER_OP(abd
);
5196 GEN_NEON_INTEGER_OP(abd
);
5197 tcg_temp_free_i32(tmp2
);
5198 tmp2
= neon_load_reg(rd
, pass
);
5199 gen_neon_add(size
, tmp
, tmp2
);
5202 /* VMUL.P8; other cases already eliminated. */
5203 gen_helper_neon_mul_p8(tmp
, tmp
, tmp2
);
5206 GEN_NEON_INTEGER_OP(pmax
);
5209 GEN_NEON_INTEGER_OP(pmin
);
5211 case NEON_3R_VQDMULH_VQRDMULH
: /* Multiply high. */
5212 if (!u
) { /* VQDMULH */
5215 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5218 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5222 } else { /* VQRDMULH */
5225 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5228 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5234 case NEON_3R_VPADD_VQRDMLAH
:
5236 case 0: gen_helper_neon_padd_u8(tmp
, tmp
, tmp2
); break;
5237 case 1: gen_helper_neon_padd_u16(tmp
, tmp
, tmp2
); break;
5238 case 2: tcg_gen_add_i32(tmp
, tmp
, tmp2
); break;
5242 case NEON_3R_FLOAT_ARITH
: /* Floating point arithmetic. */
5244 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5245 switch ((u
<< 2) | size
) {
5248 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
5251 gen_helper_vfp_subs(tmp
, tmp
, tmp2
, fpstatus
);
5254 gen_helper_neon_abd_f32(tmp
, tmp
, tmp2
, fpstatus
);
5259 tcg_temp_free_ptr(fpstatus
);
5262 case NEON_3R_FLOAT_MULTIPLY
:
5264 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5265 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
5267 tcg_temp_free_i32(tmp2
);
5268 tmp2
= neon_load_reg(rd
, pass
);
5270 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
5272 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
5275 tcg_temp_free_ptr(fpstatus
);
5278 case NEON_3R_FLOAT_CMP
:
5280 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5282 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
5285 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
5287 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
5290 tcg_temp_free_ptr(fpstatus
);
5293 case NEON_3R_FLOAT_ACMP
:
5295 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5297 gen_helper_neon_acge_f32(tmp
, tmp
, tmp2
, fpstatus
);
5299 gen_helper_neon_acgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
5301 tcg_temp_free_ptr(fpstatus
);
5304 case NEON_3R_FLOAT_MINMAX
:
5306 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5308 gen_helper_vfp_maxs(tmp
, tmp
, tmp2
, fpstatus
);
5310 gen_helper_vfp_mins(tmp
, tmp
, tmp2
, fpstatus
);
5312 tcg_temp_free_ptr(fpstatus
);
5315 case NEON_3R_FLOAT_MISC
:
5318 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5320 gen_helper_vfp_maxnums(tmp
, tmp
, tmp2
, fpstatus
);
5322 gen_helper_vfp_minnums(tmp
, tmp
, tmp2
, fpstatus
);
5324 tcg_temp_free_ptr(fpstatus
);
5327 gen_helper_recps_f32(tmp
, tmp
, tmp2
, cpu_env
);
5329 gen_helper_rsqrts_f32(tmp
, tmp
, tmp2
, cpu_env
);
5333 case NEON_3R_VFM_VQRDMLSH
:
5335 /* VFMA, VFMS: fused multiply-add */
5336 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5337 TCGv_i32 tmp3
= neon_load_reg(rd
, pass
);
5340 gen_helper_vfp_negs(tmp
, tmp
);
5342 gen_helper_vfp_muladds(tmp
, tmp
, tmp2
, tmp3
, fpstatus
);
5343 tcg_temp_free_i32(tmp3
);
5344 tcg_temp_free_ptr(fpstatus
);
5350 tcg_temp_free_i32(tmp2
);
5352 /* Save the result. For elementwise operations we can put it
5353 straight into the destination register. For pairwise operations
5354 we have to be careful to avoid clobbering the source operands. */
5355 if (pairwise
&& rd
== rm
) {
5356 neon_store_scratch(pass
, tmp
);
5358 neon_store_reg(rd
, pass
, tmp
);
5362 if (pairwise
&& rd
== rm
) {
5363 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5364 tmp
= neon_load_scratch(pass
);
5365 neon_store_reg(rd
, pass
, tmp
);
5368 /* End of 3 register same size operations. */
5369 } else if (insn
& (1 << 4)) {
5370 if ((insn
& 0x00380080) != 0) {
5371 /* Two registers and shift. */
5372 op
= (insn
>> 8) & 0xf;
5373 if (insn
& (1 << 7)) {
5381 while ((insn
& (1 << (size
+ 19))) == 0)
5384 shift
= (insn
>> 16) & ((1 << (3 + size
)) - 1);
5386 /* Shift by immediate:
5387 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
5388 if (q
&& ((rd
| rm
) & 1)) {
5391 if (!u
&& (op
== 4 || op
== 6)) {
5394 /* Right shifts are encoded as N - shift, where N is the
5395 element size in bits. */
5397 shift
= shift
- (1 << (size
+ 3));
5402 /* Right shift comes here negative. */
5404 /* Shifts larger than the element size are architecturally
5405 * valid. Unsigned results in all zeros; signed results
5409 tcg_gen_gvec_sari(size
, rd_ofs
, rm_ofs
,
5410 MIN(shift
, (8 << size
) - 1),
5411 vec_size
, vec_size
);
5412 } else if (shift
>= 8 << size
) {
5413 tcg_gen_gvec_dup8i(rd_ofs
, vec_size
, vec_size
, 0);
5415 tcg_gen_gvec_shri(size
, rd_ofs
, rm_ofs
, shift
,
5416 vec_size
, vec_size
);
5421 /* Right shift comes here negative. */
5423 /* Shifts larger than the element size are architecturally
5424 * valid. Unsigned results in all zeros; signed results
5428 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, vec_size
, vec_size
,
5429 MIN(shift
, (8 << size
) - 1),
5431 } else if (shift
>= 8 << size
) {
5434 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, vec_size
, vec_size
,
5435 shift
, &usra_op
[size
]);
5443 /* Right shift comes here negative. */
5445 /* Shift out of range leaves destination unchanged. */
5446 if (shift
< 8 << size
) {
5447 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, vec_size
, vec_size
,
5448 shift
, &sri_op
[size
]);
5452 case 5: /* VSHL, VSLI */
5454 /* Shift out of range leaves destination unchanged. */
5455 if (shift
< 8 << size
) {
5456 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, vec_size
,
5457 vec_size
, shift
, &sli_op
[size
]);
5460 /* Shifts larger than the element size are
5461 * architecturally valid and results in zero.
5463 if (shift
>= 8 << size
) {
5464 tcg_gen_gvec_dup8i(rd_ofs
, vec_size
, vec_size
, 0);
5466 tcg_gen_gvec_shli(size
, rd_ofs
, rm_ofs
, shift
,
5467 vec_size
, vec_size
);
5479 /* To avoid excessive duplication of ops we implement shift
5480 * by immediate using the variable shift operations.
5482 imm
= dup_const(size
, shift
);
5484 for (pass
= 0; pass
< count
; pass
++) {
5486 neon_load_reg64(cpu_V0
, rm
+ pass
);
5487 tcg_gen_movi_i64(cpu_V1
, imm
);
5492 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
5494 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
5496 case 6: /* VQSHLU */
5497 gen_helper_neon_qshlu_s64(cpu_V0
, cpu_env
,
5502 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
5505 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
5510 g_assert_not_reached();
5514 neon_load_reg64(cpu_V1
, rd
+ pass
);
5515 tcg_gen_add_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5517 neon_store_reg64(cpu_V0
, rd
+ pass
);
5518 } else { /* size < 3 */
5519 /* Operands in T0 and T1. */
5520 tmp
= neon_load_reg(rm
, pass
);
5521 tmp2
= tcg_temp_new_i32();
5522 tcg_gen_movi_i32(tmp2
, imm
);
5526 GEN_NEON_INTEGER_OP(rshl
);
5528 case 6: /* VQSHLU */
5531 gen_helper_neon_qshlu_s8(tmp
, cpu_env
,
5535 gen_helper_neon_qshlu_s16(tmp
, cpu_env
,
5539 gen_helper_neon_qshlu_s32(tmp
, cpu_env
,
5547 GEN_NEON_INTEGER_OP_ENV(qshl
);
5550 g_assert_not_reached();
5552 tcg_temp_free_i32(tmp2
);
5556 tmp2
= neon_load_reg(rd
, pass
);
5557 gen_neon_add(size
, tmp
, tmp2
);
5558 tcg_temp_free_i32(tmp2
);
5560 neon_store_reg(rd
, pass
, tmp
);
5563 } else if (op
< 10) {
5564 /* Shift by immediate and narrow:
5565 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
5566 int input_unsigned
= (op
== 8) ? !u
: u
;
5570 shift
= shift
- (1 << (size
+ 3));
5573 tmp64
= tcg_const_i64(shift
);
5574 neon_load_reg64(cpu_V0
, rm
);
5575 neon_load_reg64(cpu_V1
, rm
+ 1);
5576 for (pass
= 0; pass
< 2; pass
++) {
5584 if (input_unsigned
) {
5585 gen_helper_neon_rshl_u64(cpu_V0
, in
, tmp64
);
5587 gen_helper_neon_rshl_s64(cpu_V0
, in
, tmp64
);
5590 if (input_unsigned
) {
5591 gen_helper_neon_shl_u64(cpu_V0
, in
, tmp64
);
5593 gen_helper_neon_shl_s64(cpu_V0
, in
, tmp64
);
5596 tmp
= tcg_temp_new_i32();
5597 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
5598 neon_store_reg(rd
, pass
, tmp
);
5600 tcg_temp_free_i64(tmp64
);
5603 imm
= (uint16_t)shift
;
5607 imm
= (uint32_t)shift
;
5609 tmp2
= tcg_const_i32(imm
);
5610 tmp4
= neon_load_reg(rm
+ 1, 0);
5611 tmp5
= neon_load_reg(rm
+ 1, 1);
5612 for (pass
= 0; pass
< 2; pass
++) {
5614 tmp
= neon_load_reg(rm
, 0);
5618 gen_neon_shift_narrow(size
, tmp
, tmp2
, q
,
5621 tmp3
= neon_load_reg(rm
, 1);
5625 gen_neon_shift_narrow(size
, tmp3
, tmp2
, q
,
5627 tcg_gen_concat_i32_i64(cpu_V0
, tmp
, tmp3
);
5628 tcg_temp_free_i32(tmp
);
5629 tcg_temp_free_i32(tmp3
);
5630 tmp
= tcg_temp_new_i32();
5631 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
5632 neon_store_reg(rd
, pass
, tmp
);
5634 tcg_temp_free_i32(tmp2
);
5636 } else if (op
== 10) {
5638 if (q
|| (rd
& 1)) {
5641 tmp
= neon_load_reg(rm
, 0);
5642 tmp2
= neon_load_reg(rm
, 1);
5643 for (pass
= 0; pass
< 2; pass
++) {
5647 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
5650 /* The shift is less than the width of the source
5651 type, so we can just shift the whole register. */
5652 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, shift
);
5653 /* Widen the result of shift: we need to clear
5654 * the potential overflow bits resulting from
5655 * left bits of the narrow input appearing as
5656 * right bits of left the neighbour narrow
5658 if (size
< 2 || !u
) {
5661 imm
= (0xffu
>> (8 - shift
));
5663 } else if (size
== 1) {
5664 imm
= 0xffff >> (16 - shift
);
5667 imm
= 0xffffffff >> (32 - shift
);
5670 imm64
= imm
| (((uint64_t)imm
) << 32);
5674 tcg_gen_andi_i64(cpu_V0
, cpu_V0
, ~imm64
);
5677 neon_store_reg64(cpu_V0
, rd
+ pass
);
5679 } else if (op
>= 14) {
5680 /* VCVT fixed-point. */
5683 VFPGenFixPointFn
*fn
;
5685 if (!(insn
& (1 << 21)) || (q
&& ((rd
| rm
) & 1))) {
5691 fn
= gen_helper_vfp_ultos
;
5693 fn
= gen_helper_vfp_sltos
;
5697 fn
= gen_helper_vfp_touls_round_to_zero
;
5699 fn
= gen_helper_vfp_tosls_round_to_zero
;
5703 /* We have already masked out the must-be-1 top bit of imm6,
5704 * hence this 32-shift where the ARM ARM has 64-imm6.
5707 fpst
= get_fpstatus_ptr(1);
5708 shiftv
= tcg_const_i32(shift
);
5709 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5710 TCGv_i32 tmpf
= neon_load_reg(rm
, pass
);
5711 fn(tmpf
, tmpf
, shiftv
, fpst
);
5712 neon_store_reg(rd
, pass
, tmpf
);
5714 tcg_temp_free_ptr(fpst
);
5715 tcg_temp_free_i32(shiftv
);
5719 } else { /* (insn & 0x00380080) == 0 */
5720 int invert
, reg_ofs
, vec_size
;
5722 if (q
&& (rd
& 1)) {
5726 op
= (insn
>> 8) & 0xf;
5727 /* One register and immediate. */
5728 imm
= (u
<< 7) | ((insn
>> 12) & 0x70) | (insn
& 0xf);
5729 invert
= (insn
& (1 << 5)) != 0;
5730 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
5731 * We choose to not special-case this and will behave as if a
5732 * valid constant encoding of 0 had been given.
5751 imm
= (imm
<< 8) | (imm
<< 24);
5754 imm
= (imm
<< 8) | 0xff;
5757 imm
= (imm
<< 16) | 0xffff;
5760 imm
|= (imm
<< 8) | (imm
<< 16) | (imm
<< 24);
5769 imm
= ((imm
& 0x80) << 24) | ((imm
& 0x3f) << 19)
5770 | ((imm
& 0x40) ? (0x1f << 25) : (1 << 30));
5777 reg_ofs
= neon_reg_offset(rd
, 0);
5778 vec_size
= q
? 16 : 8;
5780 if (op
& 1 && op
< 12) {
5782 /* The immediate value has already been inverted,
5783 * so BIC becomes AND.
5785 tcg_gen_gvec_andi(MO_32
, reg_ofs
, reg_ofs
, imm
,
5786 vec_size
, vec_size
);
5788 tcg_gen_gvec_ori(MO_32
, reg_ofs
, reg_ofs
, imm
,
5789 vec_size
, vec_size
);
5793 if (op
== 14 && invert
) {
5794 TCGv_i64 t64
= tcg_temp_new_i64();
5796 for (pass
= 0; pass
<= q
; ++pass
) {
5800 for (n
= 0; n
< 8; n
++) {
5801 if (imm
& (1 << (n
+ pass
* 8))) {
5802 val
|= 0xffull
<< (n
* 8);
5805 tcg_gen_movi_i64(t64
, val
);
5806 neon_store_reg64(t64
, rd
+ pass
);
5808 tcg_temp_free_i64(t64
);
5810 tcg_gen_gvec_dup32i(reg_ofs
, vec_size
, vec_size
, imm
);
5814 } else { /* (insn & 0x00800010 == 0x00800000) */
5816 op
= (insn
>> 8) & 0xf;
5817 if ((insn
& (1 << 6)) == 0) {
5818 /* Three registers of different lengths. */
5822 /* undefreq: bit 0 : UNDEF if size == 0
5823 * bit 1 : UNDEF if size == 1
5824 * bit 2 : UNDEF if size == 2
5825 * bit 3 : UNDEF if U == 1
5826 * Note that [2:0] set implies 'always UNDEF'
5829 /* prewiden, src1_wide, src2_wide, undefreq */
5830 static const int neon_3reg_wide
[16][4] = {
5831 {1, 0, 0, 0}, /* VADDL */
5832 {1, 1, 0, 0}, /* VADDW */
5833 {1, 0, 0, 0}, /* VSUBL */
5834 {1, 1, 0, 0}, /* VSUBW */
5835 {0, 1, 1, 0}, /* VADDHN */
5836 {0, 0, 0, 0}, /* VABAL */
5837 {0, 1, 1, 0}, /* VSUBHN */
5838 {0, 0, 0, 0}, /* VABDL */
5839 {0, 0, 0, 0}, /* VMLAL */
5840 {0, 0, 0, 9}, /* VQDMLAL */
5841 {0, 0, 0, 0}, /* VMLSL */
5842 {0, 0, 0, 9}, /* VQDMLSL */
5843 {0, 0, 0, 0}, /* Integer VMULL */
5844 {0, 0, 0, 1}, /* VQDMULL */
5845 {0, 0, 0, 0xa}, /* Polynomial VMULL */
5846 {0, 0, 0, 7}, /* Reserved: always UNDEF */
5849 prewiden
= neon_3reg_wide
[op
][0];
5850 src1_wide
= neon_3reg_wide
[op
][1];
5851 src2_wide
= neon_3reg_wide
[op
][2];
5852 undefreq
= neon_3reg_wide
[op
][3];
5854 if ((undefreq
& (1 << size
)) ||
5855 ((undefreq
& 8) && u
)) {
5858 if ((src1_wide
&& (rn
& 1)) ||
5859 (src2_wide
&& (rm
& 1)) ||
5860 (!src2_wide
&& (rd
& 1))) {
5864 /* Handle VMULL.P64 (Polynomial 64x64 to 128 bit multiply)
5865 * outside the loop below as it only performs a single pass.
5867 if (op
== 14 && size
== 2) {
5868 TCGv_i64 tcg_rn
, tcg_rm
, tcg_rd
;
5870 if (!dc_isar_feature(aa32_pmull
, s
)) {
5873 tcg_rn
= tcg_temp_new_i64();
5874 tcg_rm
= tcg_temp_new_i64();
5875 tcg_rd
= tcg_temp_new_i64();
5876 neon_load_reg64(tcg_rn
, rn
);
5877 neon_load_reg64(tcg_rm
, rm
);
5878 gen_helper_neon_pmull_64_lo(tcg_rd
, tcg_rn
, tcg_rm
);
5879 neon_store_reg64(tcg_rd
, rd
);
5880 gen_helper_neon_pmull_64_hi(tcg_rd
, tcg_rn
, tcg_rm
);
5881 neon_store_reg64(tcg_rd
, rd
+ 1);
5882 tcg_temp_free_i64(tcg_rn
);
5883 tcg_temp_free_i64(tcg_rm
);
5884 tcg_temp_free_i64(tcg_rd
);
5888 /* Avoid overlapping operands. Wide source operands are
5889 always aligned so will never overlap with wide
5890 destinations in problematic ways. */
5891 if (rd
== rm
&& !src2_wide
) {
5892 tmp
= neon_load_reg(rm
, 1);
5893 neon_store_scratch(2, tmp
);
5894 } else if (rd
== rn
&& !src1_wide
) {
5895 tmp
= neon_load_reg(rn
, 1);
5896 neon_store_scratch(2, tmp
);
5899 for (pass
= 0; pass
< 2; pass
++) {
5901 neon_load_reg64(cpu_V0
, rn
+ pass
);
5904 if (pass
== 1 && rd
== rn
) {
5905 tmp
= neon_load_scratch(2);
5907 tmp
= neon_load_reg(rn
, pass
);
5910 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
5914 neon_load_reg64(cpu_V1
, rm
+ pass
);
5917 if (pass
== 1 && rd
== rm
) {
5918 tmp2
= neon_load_scratch(2);
5920 tmp2
= neon_load_reg(rm
, pass
);
5923 gen_neon_widen(cpu_V1
, tmp2
, size
, u
);
5927 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5928 gen_neon_addl(size
);
5930 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5931 gen_neon_subl(size
);
5933 case 5: case 7: /* VABAL, VABDL */
5934 switch ((size
<< 1) | u
) {
5936 gen_helper_neon_abdl_s16(cpu_V0
, tmp
, tmp2
);
5939 gen_helper_neon_abdl_u16(cpu_V0
, tmp
, tmp2
);
5942 gen_helper_neon_abdl_s32(cpu_V0
, tmp
, tmp2
);
5945 gen_helper_neon_abdl_u32(cpu_V0
, tmp
, tmp2
);
5948 gen_helper_neon_abdl_s64(cpu_V0
, tmp
, tmp2
);
5951 gen_helper_neon_abdl_u64(cpu_V0
, tmp
, tmp2
);
5955 tcg_temp_free_i32(tmp2
);
5956 tcg_temp_free_i32(tmp
);
5958 case 8: case 9: case 10: case 11: case 12: case 13:
5959 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5960 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
5962 case 14: /* Polynomial VMULL */
5963 gen_helper_neon_mull_p8(cpu_V0
, tmp
, tmp2
);
5964 tcg_temp_free_i32(tmp2
);
5965 tcg_temp_free_i32(tmp
);
5967 default: /* 15 is RESERVED: caught earlier */
5972 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5973 neon_store_reg64(cpu_V0
, rd
+ pass
);
5974 } else if (op
== 5 || (op
>= 8 && op
<= 11)) {
5976 neon_load_reg64(cpu_V1
, rd
+ pass
);
5978 case 10: /* VMLSL */
5979 gen_neon_negl(cpu_V0
, size
);
5981 case 5: case 8: /* VABAL, VMLAL */
5982 gen_neon_addl(size
);
5984 case 9: case 11: /* VQDMLAL, VQDMLSL */
5985 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5987 gen_neon_negl(cpu_V0
, size
);
5989 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
5994 neon_store_reg64(cpu_V0
, rd
+ pass
);
5995 } else if (op
== 4 || op
== 6) {
5996 /* Narrowing operation. */
5997 tmp
= tcg_temp_new_i32();
6001 gen_helper_neon_narrow_high_u8(tmp
, cpu_V0
);
6004 gen_helper_neon_narrow_high_u16(tmp
, cpu_V0
);
6007 tcg_gen_extrh_i64_i32(tmp
, cpu_V0
);
6014 gen_helper_neon_narrow_round_high_u8(tmp
, cpu_V0
);
6017 gen_helper_neon_narrow_round_high_u16(tmp
, cpu_V0
);
6020 tcg_gen_addi_i64(cpu_V0
, cpu_V0
, 1u << 31);
6021 tcg_gen_extrh_i64_i32(tmp
, cpu_V0
);
6029 neon_store_reg(rd
, 0, tmp3
);
6030 neon_store_reg(rd
, 1, tmp
);
6033 /* Write back the result. */
6034 neon_store_reg64(cpu_V0
, rd
+ pass
);
6038 /* Two registers and a scalar. NB that for ops of this form
6039 * the ARM ARM labels bit 24 as Q, but it is in our variable
6046 case 1: /* Float VMLA scalar */
6047 case 5: /* Floating point VMLS scalar */
6048 case 9: /* Floating point VMUL scalar */
6053 case 0: /* Integer VMLA scalar */
6054 case 4: /* Integer VMLS scalar */
6055 case 8: /* Integer VMUL scalar */
6056 case 12: /* VQDMULH scalar */
6057 case 13: /* VQRDMULH scalar */
6058 if (u
&& ((rd
| rn
) & 1)) {
6061 tmp
= neon_get_scalar(size
, rm
);
6062 neon_store_scratch(0, tmp
);
6063 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
6064 tmp
= neon_load_scratch(0);
6065 tmp2
= neon_load_reg(rn
, pass
);
6068 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
6070 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
6072 } else if (op
== 13) {
6074 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
6076 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
6078 } else if (op
& 1) {
6079 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6080 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
6081 tcg_temp_free_ptr(fpstatus
);
6084 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
6085 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
6086 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
6090 tcg_temp_free_i32(tmp2
);
6093 tmp2
= neon_load_reg(rd
, pass
);
6096 gen_neon_add(size
, tmp
, tmp2
);
6100 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6101 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
6102 tcg_temp_free_ptr(fpstatus
);
6106 gen_neon_rsb(size
, tmp
, tmp2
);
6110 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6111 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
6112 tcg_temp_free_ptr(fpstatus
);
6118 tcg_temp_free_i32(tmp2
);
6120 neon_store_reg(rd
, pass
, tmp
);
6123 case 3: /* VQDMLAL scalar */
6124 case 7: /* VQDMLSL scalar */
6125 case 11: /* VQDMULL scalar */
6130 case 2: /* VMLAL sclar */
6131 case 6: /* VMLSL scalar */
6132 case 10: /* VMULL scalar */
6136 tmp2
= neon_get_scalar(size
, rm
);
6137 /* We need a copy of tmp2 because gen_neon_mull
6138 * deletes it during pass 0. */
6139 tmp4
= tcg_temp_new_i32();
6140 tcg_gen_mov_i32(tmp4
, tmp2
);
6141 tmp3
= neon_load_reg(rn
, 1);
6143 for (pass
= 0; pass
< 2; pass
++) {
6145 tmp
= neon_load_reg(rn
, 0);
6150 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
6152 neon_load_reg64(cpu_V1
, rd
+ pass
);
6156 gen_neon_negl(cpu_V0
, size
);
6159 gen_neon_addl(size
);
6162 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6164 gen_neon_negl(cpu_V0
, size
);
6166 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
6172 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6177 neon_store_reg64(cpu_V0
, rd
+ pass
);
6180 case 14: /* VQRDMLAH scalar */
6181 case 15: /* VQRDMLSH scalar */
6183 NeonGenThreeOpEnvFn
*fn
;
6185 if (!dc_isar_feature(aa32_rdm
, s
)) {
6188 if (u
&& ((rd
| rn
) & 1)) {
6193 fn
= gen_helper_neon_qrdmlah_s16
;
6195 fn
= gen_helper_neon_qrdmlah_s32
;
6199 fn
= gen_helper_neon_qrdmlsh_s16
;
6201 fn
= gen_helper_neon_qrdmlsh_s32
;
6205 tmp2
= neon_get_scalar(size
, rm
);
6206 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
6207 tmp
= neon_load_reg(rn
, pass
);
6208 tmp3
= neon_load_reg(rd
, pass
);
6209 fn(tmp
, cpu_env
, tmp
, tmp2
, tmp3
);
6210 tcg_temp_free_i32(tmp3
);
6211 neon_store_reg(rd
, pass
, tmp
);
6213 tcg_temp_free_i32(tmp2
);
6217 g_assert_not_reached();
6220 } else { /* size == 3 */
6223 imm
= (insn
>> 8) & 0xf;
6228 if (q
&& ((rd
| rn
| rm
) & 1)) {
6233 neon_load_reg64(cpu_V0
, rn
);
6235 neon_load_reg64(cpu_V1
, rn
+ 1);
6237 } else if (imm
== 8) {
6238 neon_load_reg64(cpu_V0
, rn
+ 1);
6240 neon_load_reg64(cpu_V1
, rm
);
6243 tmp64
= tcg_temp_new_i64();
6245 neon_load_reg64(cpu_V0
, rn
);
6246 neon_load_reg64(tmp64
, rn
+ 1);
6248 neon_load_reg64(cpu_V0
, rn
+ 1);
6249 neon_load_reg64(tmp64
, rm
);
6251 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, (imm
& 7) * 8);
6252 tcg_gen_shli_i64(cpu_V1
, tmp64
, 64 - ((imm
& 7) * 8));
6253 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6255 neon_load_reg64(cpu_V1
, rm
);
6257 neon_load_reg64(cpu_V1
, rm
+ 1);
6260 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
6261 tcg_gen_shri_i64(tmp64
, tmp64
, imm
* 8);
6262 tcg_gen_or_i64(cpu_V1
, cpu_V1
, tmp64
);
6263 tcg_temp_free_i64(tmp64
);
6266 neon_load_reg64(cpu_V0
, rn
);
6267 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, imm
* 8);
6268 neon_load_reg64(cpu_V1
, rm
);
6269 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
6270 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6272 neon_store_reg64(cpu_V0
, rd
);
6274 neon_store_reg64(cpu_V1
, rd
+ 1);
6276 } else if ((insn
& (1 << 11)) == 0) {
6277 /* Two register misc. */
6278 op
= ((insn
>> 12) & 0x30) | ((insn
>> 7) & 0xf);
6279 size
= (insn
>> 18) & 3;
6280 /* UNDEF for unknown op values and bad op-size combinations */
6281 if ((neon_2rm_sizes
[op
] & (1 << size
)) == 0) {
6284 if (neon_2rm_is_v8_op(op
) &&
6285 !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
6288 if ((op
!= NEON_2RM_VMOVN
&& op
!= NEON_2RM_VQMOVN
) &&
6289 q
&& ((rm
| rd
) & 1)) {
6293 case NEON_2RM_VREV64
:
6294 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
6295 tmp
= neon_load_reg(rm
, pass
* 2);
6296 tmp2
= neon_load_reg(rm
, pass
* 2 + 1);
6298 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
6299 case 1: gen_swap_half(tmp
); break;
6300 case 2: /* no-op */ break;
6303 neon_store_reg(rd
, pass
* 2 + 1, tmp
);
6305 neon_store_reg(rd
, pass
* 2, tmp2
);
6308 case 0: tcg_gen_bswap32_i32(tmp2
, tmp2
); break;
6309 case 1: gen_swap_half(tmp2
); break;
6312 neon_store_reg(rd
, pass
* 2, tmp2
);
6316 case NEON_2RM_VPADDL
: case NEON_2RM_VPADDL_U
:
6317 case NEON_2RM_VPADAL
: case NEON_2RM_VPADAL_U
:
6318 for (pass
= 0; pass
< q
+ 1; pass
++) {
6319 tmp
= neon_load_reg(rm
, pass
* 2);
6320 gen_neon_widen(cpu_V0
, tmp
, size
, op
& 1);
6321 tmp
= neon_load_reg(rm
, pass
* 2 + 1);
6322 gen_neon_widen(cpu_V1
, tmp
, size
, op
& 1);
6324 case 0: gen_helper_neon_paddl_u16(CPU_V001
); break;
6325 case 1: gen_helper_neon_paddl_u32(CPU_V001
); break;
6326 case 2: tcg_gen_add_i64(CPU_V001
); break;
6329 if (op
>= NEON_2RM_VPADAL
) {
6331 neon_load_reg64(cpu_V1
, rd
+ pass
);
6332 gen_neon_addl(size
);
6334 neon_store_reg64(cpu_V0
, rd
+ pass
);
6340 for (n
= 0; n
< (q
? 4 : 2); n
+= 2) {
6341 tmp
= neon_load_reg(rm
, n
);
6342 tmp2
= neon_load_reg(rd
, n
+ 1);
6343 neon_store_reg(rm
, n
, tmp2
);
6344 neon_store_reg(rd
, n
+ 1, tmp
);
6351 if (gen_neon_unzip(rd
, rm
, size
, q
)) {
6356 if (gen_neon_zip(rd
, rm
, size
, q
)) {
6360 case NEON_2RM_VMOVN
: case NEON_2RM_VQMOVN
:
6361 /* also VQMOVUN; op field and mnemonics don't line up */
6366 for (pass
= 0; pass
< 2; pass
++) {
6367 neon_load_reg64(cpu_V0
, rm
+ pass
);
6368 tmp
= tcg_temp_new_i32();
6369 gen_neon_narrow_op(op
== NEON_2RM_VMOVN
, q
, size
,
6374 neon_store_reg(rd
, 0, tmp2
);
6375 neon_store_reg(rd
, 1, tmp
);
6379 case NEON_2RM_VSHLL
:
6380 if (q
|| (rd
& 1)) {
6383 tmp
= neon_load_reg(rm
, 0);
6384 tmp2
= neon_load_reg(rm
, 1);
6385 for (pass
= 0; pass
< 2; pass
++) {
6388 gen_neon_widen(cpu_V0
, tmp
, size
, 1);
6389 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, 8 << size
);
6390 neon_store_reg64(cpu_V0
, rd
+ pass
);
6393 case NEON_2RM_VCVT_F16_F32
:
6398 if (!dc_isar_feature(aa32_fp16_spconv
, s
) ||
6402 fpst
= get_fpstatus_ptr(true);
6403 ahp
= get_ahp_flag();
6404 tmp
= neon_load_reg(rm
, 0);
6405 gen_helper_vfp_fcvt_f32_to_f16(tmp
, tmp
, fpst
, ahp
);
6406 tmp2
= neon_load_reg(rm
, 1);
6407 gen_helper_vfp_fcvt_f32_to_f16(tmp2
, tmp2
, fpst
, ahp
);
6408 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
6409 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
6410 tcg_temp_free_i32(tmp
);
6411 tmp
= neon_load_reg(rm
, 2);
6412 gen_helper_vfp_fcvt_f32_to_f16(tmp
, tmp
, fpst
, ahp
);
6413 tmp3
= neon_load_reg(rm
, 3);
6414 neon_store_reg(rd
, 0, tmp2
);
6415 gen_helper_vfp_fcvt_f32_to_f16(tmp3
, tmp3
, fpst
, ahp
);
6416 tcg_gen_shli_i32(tmp3
, tmp3
, 16);
6417 tcg_gen_or_i32(tmp3
, tmp3
, tmp
);
6418 neon_store_reg(rd
, 1, tmp3
);
6419 tcg_temp_free_i32(tmp
);
6420 tcg_temp_free_i32(ahp
);
6421 tcg_temp_free_ptr(fpst
);
6424 case NEON_2RM_VCVT_F32_F16
:
6428 if (!dc_isar_feature(aa32_fp16_spconv
, s
) ||
6432 fpst
= get_fpstatus_ptr(true);
6433 ahp
= get_ahp_flag();
6434 tmp3
= tcg_temp_new_i32();
6435 tmp
= neon_load_reg(rm
, 0);
6436 tmp2
= neon_load_reg(rm
, 1);
6437 tcg_gen_ext16u_i32(tmp3
, tmp
);
6438 gen_helper_vfp_fcvt_f16_to_f32(tmp3
, tmp3
, fpst
, ahp
);
6439 neon_store_reg(rd
, 0, tmp3
);
6440 tcg_gen_shri_i32(tmp
, tmp
, 16);
6441 gen_helper_vfp_fcvt_f16_to_f32(tmp
, tmp
, fpst
, ahp
);
6442 neon_store_reg(rd
, 1, tmp
);
6443 tmp3
= tcg_temp_new_i32();
6444 tcg_gen_ext16u_i32(tmp3
, tmp2
);
6445 gen_helper_vfp_fcvt_f16_to_f32(tmp3
, tmp3
, fpst
, ahp
);
6446 neon_store_reg(rd
, 2, tmp3
);
6447 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
6448 gen_helper_vfp_fcvt_f16_to_f32(tmp2
, tmp2
, fpst
, ahp
);
6449 neon_store_reg(rd
, 3, tmp2
);
6450 tcg_temp_free_i32(ahp
);
6451 tcg_temp_free_ptr(fpst
);
6454 case NEON_2RM_AESE
: case NEON_2RM_AESMC
:
6455 if (!dc_isar_feature(aa32_aes
, s
) || ((rm
| rd
) & 1)) {
6458 ptr1
= vfp_reg_ptr(true, rd
);
6459 ptr2
= vfp_reg_ptr(true, rm
);
6461 /* Bit 6 is the lowest opcode bit; it distinguishes between
6462 * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
6464 tmp3
= tcg_const_i32(extract32(insn
, 6, 1));
6466 if (op
== NEON_2RM_AESE
) {
6467 gen_helper_crypto_aese(ptr1
, ptr2
, tmp3
);
6469 gen_helper_crypto_aesmc(ptr1
, ptr2
, tmp3
);
6471 tcg_temp_free_ptr(ptr1
);
6472 tcg_temp_free_ptr(ptr2
);
6473 tcg_temp_free_i32(tmp3
);
6475 case NEON_2RM_SHA1H
:
6476 if (!dc_isar_feature(aa32_sha1
, s
) || ((rm
| rd
) & 1)) {
6479 ptr1
= vfp_reg_ptr(true, rd
);
6480 ptr2
= vfp_reg_ptr(true, rm
);
6482 gen_helper_crypto_sha1h(ptr1
, ptr2
);
6484 tcg_temp_free_ptr(ptr1
);
6485 tcg_temp_free_ptr(ptr2
);
6487 case NEON_2RM_SHA1SU1
:
6488 if ((rm
| rd
) & 1) {
6491 /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
6493 if (!dc_isar_feature(aa32_sha2
, s
)) {
6496 } else if (!dc_isar_feature(aa32_sha1
, s
)) {
6499 ptr1
= vfp_reg_ptr(true, rd
);
6500 ptr2
= vfp_reg_ptr(true, rm
);
6502 gen_helper_crypto_sha256su0(ptr1
, ptr2
);
6504 gen_helper_crypto_sha1su1(ptr1
, ptr2
);
6506 tcg_temp_free_ptr(ptr1
);
6507 tcg_temp_free_ptr(ptr2
);
6511 tcg_gen_gvec_not(0, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
6514 tcg_gen_gvec_neg(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
6517 tcg_gen_gvec_abs(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
6522 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
6523 tmp
= neon_load_reg(rm
, pass
);
6525 case NEON_2RM_VREV32
:
6527 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
6528 case 1: gen_swap_half(tmp
); break;
6532 case NEON_2RM_VREV16
:
6537 case 0: gen_helper_neon_cls_s8(tmp
, tmp
); break;
6538 case 1: gen_helper_neon_cls_s16(tmp
, tmp
); break;
6539 case 2: gen_helper_neon_cls_s32(tmp
, tmp
); break;
6545 case 0: gen_helper_neon_clz_u8(tmp
, tmp
); break;
6546 case 1: gen_helper_neon_clz_u16(tmp
, tmp
); break;
6547 case 2: tcg_gen_clzi_i32(tmp
, tmp
, 32); break;
6552 gen_helper_neon_cnt_u8(tmp
, tmp
);
6554 case NEON_2RM_VQABS
:
6557 gen_helper_neon_qabs_s8(tmp
, cpu_env
, tmp
);
6560 gen_helper_neon_qabs_s16(tmp
, cpu_env
, tmp
);
6563 gen_helper_neon_qabs_s32(tmp
, cpu_env
, tmp
);
6568 case NEON_2RM_VQNEG
:
6571 gen_helper_neon_qneg_s8(tmp
, cpu_env
, tmp
);
6574 gen_helper_neon_qneg_s16(tmp
, cpu_env
, tmp
);
6577 gen_helper_neon_qneg_s32(tmp
, cpu_env
, tmp
);
6582 case NEON_2RM_VCGT0
: case NEON_2RM_VCLE0
:
6583 tmp2
= tcg_const_i32(0);
6585 case 0: gen_helper_neon_cgt_s8(tmp
, tmp
, tmp2
); break;
6586 case 1: gen_helper_neon_cgt_s16(tmp
, tmp
, tmp2
); break;
6587 case 2: gen_helper_neon_cgt_s32(tmp
, tmp
, tmp2
); break;
6590 tcg_temp_free_i32(tmp2
);
6591 if (op
== NEON_2RM_VCLE0
) {
6592 tcg_gen_not_i32(tmp
, tmp
);
6595 case NEON_2RM_VCGE0
: case NEON_2RM_VCLT0
:
6596 tmp2
= tcg_const_i32(0);
6598 case 0: gen_helper_neon_cge_s8(tmp
, tmp
, tmp2
); break;
6599 case 1: gen_helper_neon_cge_s16(tmp
, tmp
, tmp2
); break;
6600 case 2: gen_helper_neon_cge_s32(tmp
, tmp
, tmp2
); break;
6603 tcg_temp_free_i32(tmp2
);
6604 if (op
== NEON_2RM_VCLT0
) {
6605 tcg_gen_not_i32(tmp
, tmp
);
6608 case NEON_2RM_VCEQ0
:
6609 tmp2
= tcg_const_i32(0);
6611 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
6612 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
6613 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
6616 tcg_temp_free_i32(tmp2
);
6618 case NEON_2RM_VCGT0_F
:
6620 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6621 tmp2
= tcg_const_i32(0);
6622 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
6623 tcg_temp_free_i32(tmp2
);
6624 tcg_temp_free_ptr(fpstatus
);
6627 case NEON_2RM_VCGE0_F
:
6629 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6630 tmp2
= tcg_const_i32(0);
6631 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
6632 tcg_temp_free_i32(tmp2
);
6633 tcg_temp_free_ptr(fpstatus
);
6636 case NEON_2RM_VCEQ0_F
:
6638 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6639 tmp2
= tcg_const_i32(0);
6640 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
6641 tcg_temp_free_i32(tmp2
);
6642 tcg_temp_free_ptr(fpstatus
);
6645 case NEON_2RM_VCLE0_F
:
6647 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6648 tmp2
= tcg_const_i32(0);
6649 gen_helper_neon_cge_f32(tmp
, tmp2
, tmp
, fpstatus
);
6650 tcg_temp_free_i32(tmp2
);
6651 tcg_temp_free_ptr(fpstatus
);
6654 case NEON_2RM_VCLT0_F
:
6656 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6657 tmp2
= tcg_const_i32(0);
6658 gen_helper_neon_cgt_f32(tmp
, tmp2
, tmp
, fpstatus
);
6659 tcg_temp_free_i32(tmp2
);
6660 tcg_temp_free_ptr(fpstatus
);
6663 case NEON_2RM_VABS_F
:
6664 gen_helper_vfp_abss(tmp
, tmp
);
6666 case NEON_2RM_VNEG_F
:
6667 gen_helper_vfp_negs(tmp
, tmp
);
6670 tmp2
= neon_load_reg(rd
, pass
);
6671 neon_store_reg(rm
, pass
, tmp2
);
6674 tmp2
= neon_load_reg(rd
, pass
);
6676 case 0: gen_neon_trn_u8(tmp
, tmp2
); break;
6677 case 1: gen_neon_trn_u16(tmp
, tmp2
); break;
6680 neon_store_reg(rm
, pass
, tmp2
);
6682 case NEON_2RM_VRINTN
:
6683 case NEON_2RM_VRINTA
:
6684 case NEON_2RM_VRINTM
:
6685 case NEON_2RM_VRINTP
:
6686 case NEON_2RM_VRINTZ
:
6689 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6692 if (op
== NEON_2RM_VRINTZ
) {
6693 rmode
= FPROUNDING_ZERO
;
6695 rmode
= fp_decode_rm
[((op
& 0x6) >> 1) ^ 1];
6698 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6699 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6701 gen_helper_rints(tmp
, tmp
, fpstatus
);
6702 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6704 tcg_temp_free_ptr(fpstatus
);
6705 tcg_temp_free_i32(tcg_rmode
);
6708 case NEON_2RM_VRINTX
:
6710 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6711 gen_helper_rints_exact(tmp
, tmp
, fpstatus
);
6712 tcg_temp_free_ptr(fpstatus
);
6715 case NEON_2RM_VCVTAU
:
6716 case NEON_2RM_VCVTAS
:
6717 case NEON_2RM_VCVTNU
:
6718 case NEON_2RM_VCVTNS
:
6719 case NEON_2RM_VCVTPU
:
6720 case NEON_2RM_VCVTPS
:
6721 case NEON_2RM_VCVTMU
:
6722 case NEON_2RM_VCVTMS
:
6724 bool is_signed
= !extract32(insn
, 7, 1);
6725 TCGv_ptr fpst
= get_fpstatus_ptr(1);
6726 TCGv_i32 tcg_rmode
, tcg_shift
;
6727 int rmode
= fp_decode_rm
[extract32(insn
, 8, 2)];
6729 tcg_shift
= tcg_const_i32(0);
6730 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6731 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6735 gen_helper_vfp_tosls(tmp
, tmp
,
6738 gen_helper_vfp_touls(tmp
, tmp
,
6742 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6744 tcg_temp_free_i32(tcg_rmode
);
6745 tcg_temp_free_i32(tcg_shift
);
6746 tcg_temp_free_ptr(fpst
);
6749 case NEON_2RM_VRECPE
:
6751 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6752 gen_helper_recpe_u32(tmp
, tmp
, fpstatus
);
6753 tcg_temp_free_ptr(fpstatus
);
6756 case NEON_2RM_VRSQRTE
:
6758 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6759 gen_helper_rsqrte_u32(tmp
, tmp
, fpstatus
);
6760 tcg_temp_free_ptr(fpstatus
);
6763 case NEON_2RM_VRECPE_F
:
6765 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6766 gen_helper_recpe_f32(tmp
, tmp
, fpstatus
);
6767 tcg_temp_free_ptr(fpstatus
);
6770 case NEON_2RM_VRSQRTE_F
:
6772 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6773 gen_helper_rsqrte_f32(tmp
, tmp
, fpstatus
);
6774 tcg_temp_free_ptr(fpstatus
);
6777 case NEON_2RM_VCVT_FS
: /* VCVT.F32.S32 */
6779 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6780 gen_helper_vfp_sitos(tmp
, tmp
, fpstatus
);
6781 tcg_temp_free_ptr(fpstatus
);
6784 case NEON_2RM_VCVT_FU
: /* VCVT.F32.U32 */
6786 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6787 gen_helper_vfp_uitos(tmp
, tmp
, fpstatus
);
6788 tcg_temp_free_ptr(fpstatus
);
6791 case NEON_2RM_VCVT_SF
: /* VCVT.S32.F32 */
6793 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6794 gen_helper_vfp_tosizs(tmp
, tmp
, fpstatus
);
6795 tcg_temp_free_ptr(fpstatus
);
6798 case NEON_2RM_VCVT_UF
: /* VCVT.U32.F32 */
6800 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6801 gen_helper_vfp_touizs(tmp
, tmp
, fpstatus
);
6802 tcg_temp_free_ptr(fpstatus
);
6806 /* Reserved op values were caught by the
6807 * neon_2rm_sizes[] check earlier.
6811 neon_store_reg(rd
, pass
, tmp
);
6815 } else if ((insn
& (1 << 10)) == 0) {
6817 int n
= ((insn
>> 8) & 3) + 1;
6818 if ((rn
+ n
) > 32) {
6819 /* This is UNPREDICTABLE; we choose to UNDEF to avoid the
6820 * helper function running off the end of the register file.
6825 if (insn
& (1 << 6)) {
6826 tmp
= neon_load_reg(rd
, 0);
6828 tmp
= tcg_temp_new_i32();
6829 tcg_gen_movi_i32(tmp
, 0);
6831 tmp2
= neon_load_reg(rm
, 0);
6832 ptr1
= vfp_reg_ptr(true, rn
);
6833 tmp5
= tcg_const_i32(n
);
6834 gen_helper_neon_tbl(tmp2
, tmp2
, tmp
, ptr1
, tmp5
);
6835 tcg_temp_free_i32(tmp
);
6836 if (insn
& (1 << 6)) {
6837 tmp
= neon_load_reg(rd
, 1);
6839 tmp
= tcg_temp_new_i32();
6840 tcg_gen_movi_i32(tmp
, 0);
6842 tmp3
= neon_load_reg(rm
, 1);
6843 gen_helper_neon_tbl(tmp3
, tmp3
, tmp
, ptr1
, tmp5
);
6844 tcg_temp_free_i32(tmp5
);
6845 tcg_temp_free_ptr(ptr1
);
6846 neon_store_reg(rd
, 0, tmp2
);
6847 neon_store_reg(rd
, 1, tmp3
);
6848 tcg_temp_free_i32(tmp
);
6849 } else if ((insn
& 0x380) == 0) {
6854 if ((insn
& (7 << 16)) == 0 || (q
&& (rd
& 1))) {
6857 if (insn
& (1 << 16)) {
6859 element
= (insn
>> 17) & 7;
6860 } else if (insn
& (1 << 17)) {
6862 element
= (insn
>> 18) & 3;
6865 element
= (insn
>> 19) & 1;
6867 tcg_gen_gvec_dup_mem(size
, neon_reg_offset(rd
, 0),
6868 neon_element_offset(rm
, element
, size
),
6869 q
? 16 : 8, q
? 16 : 8);
6878 /* Advanced SIMD three registers of the same length extension.
6879 * 31 25 23 22 20 16 12 11 10 9 8 3 0
6880 * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
6881 * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
6882 * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
6884 static int disas_neon_insn_3same_ext(DisasContext
*s
, uint32_t insn
)
6886 gen_helper_gvec_3
*fn_gvec
= NULL
;
6887 gen_helper_gvec_3_ptr
*fn_gvec_ptr
= NULL
;
6888 int rd
, rn
, rm
, opr_sz
;
6891 bool is_long
= false, q
= extract32(insn
, 6, 1);
6892 bool ptr_is_env
= false;
6894 if ((insn
& 0xfe200f10) == 0xfc200800) {
6895 /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
6896 int size
= extract32(insn
, 20, 1);
6897 data
= extract32(insn
, 23, 2); /* rot */
6898 if (!dc_isar_feature(aa32_vcma
, s
)
6899 || (!size
&& !dc_isar_feature(aa32_fp16_arith
, s
))) {
6902 fn_gvec_ptr
= size
? gen_helper_gvec_fcmlas
: gen_helper_gvec_fcmlah
;
6903 } else if ((insn
& 0xfea00f10) == 0xfc800800) {
6904 /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
6905 int size
= extract32(insn
, 20, 1);
6906 data
= extract32(insn
, 24, 1); /* rot */
6907 if (!dc_isar_feature(aa32_vcma
, s
)
6908 || (!size
&& !dc_isar_feature(aa32_fp16_arith
, s
))) {
6911 fn_gvec_ptr
= size
? gen_helper_gvec_fcadds
: gen_helper_gvec_fcaddh
;
6912 } else if ((insn
& 0xfeb00f00) == 0xfc200d00) {
6913 /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
6914 bool u
= extract32(insn
, 4, 1);
6915 if (!dc_isar_feature(aa32_dp
, s
)) {
6918 fn_gvec
= u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
;
6919 } else if ((insn
& 0xff300f10) == 0xfc200810) {
6920 /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
6921 int is_s
= extract32(insn
, 23, 1);
6922 if (!dc_isar_feature(aa32_fhm
, s
)) {
6926 data
= is_s
; /* is_2 == 0 */
6927 fn_gvec_ptr
= gen_helper_gvec_fmlal_a32
;
6933 VFP_DREG_D(rd
, insn
);
6937 if (q
|| !is_long
) {
6938 VFP_DREG_N(rn
, insn
);
6939 VFP_DREG_M(rm
, insn
);
6940 if ((rn
| rm
) & q
& !is_long
) {
6943 off_rn
= vfp_reg_offset(1, rn
);
6944 off_rm
= vfp_reg_offset(1, rm
);
6946 rn
= VFP_SREG_N(insn
);
6947 rm
= VFP_SREG_M(insn
);
6948 off_rn
= vfp_reg_offset(0, rn
);
6949 off_rm
= vfp_reg_offset(0, rm
);
6952 if (s
->fp_excp_el
) {
6953 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
6954 syn_simd_access_trap(1, 0xe, false), s
->fp_excp_el
);
6957 if (!s
->vfp_enabled
) {
6961 opr_sz
= (1 + q
) * 8;
6967 ptr
= get_fpstatus_ptr(1);
6969 tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd
), off_rn
, off_rm
, ptr
,
6970 opr_sz
, opr_sz
, data
, fn_gvec_ptr
);
6972 tcg_temp_free_ptr(ptr
);
6975 tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd
), off_rn
, off_rm
,
6976 opr_sz
, opr_sz
, data
, fn_gvec
);
6981 /* Advanced SIMD two registers and a scalar extension.
6982 * 31 24 23 22 20 16 12 11 10 9 8 3 0
6983 * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
6984 * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
6985 * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
6989 static int disas_neon_insn_2reg_scalar_ext(DisasContext
*s
, uint32_t insn
)
6991 gen_helper_gvec_3
*fn_gvec
= NULL
;
6992 gen_helper_gvec_3_ptr
*fn_gvec_ptr
= NULL
;
6993 int rd
, rn
, rm
, opr_sz
, data
;
6995 bool is_long
= false, q
= extract32(insn
, 6, 1);
6996 bool ptr_is_env
= false;
6998 if ((insn
& 0xff000f10) == 0xfe000800) {
6999 /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
7000 int rot
= extract32(insn
, 20, 2);
7001 int size
= extract32(insn
, 23, 1);
7004 if (!dc_isar_feature(aa32_vcma
, s
)) {
7008 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
7011 /* For fp16, rm is just Vm, and index is M. */
7012 rm
= extract32(insn
, 0, 4);
7013 index
= extract32(insn
, 5, 1);
7015 /* For fp32, rm is the usual M:Vm, and index is 0. */
7016 VFP_DREG_M(rm
, insn
);
7019 data
= (index
<< 2) | rot
;
7020 fn_gvec_ptr
= (size
? gen_helper_gvec_fcmlas_idx
7021 : gen_helper_gvec_fcmlah_idx
);
7022 } else if ((insn
& 0xffb00f00) == 0xfe200d00) {
7023 /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
7024 int u
= extract32(insn
, 4, 1);
7026 if (!dc_isar_feature(aa32_dp
, s
)) {
7029 fn_gvec
= u
? gen_helper_gvec_udot_idx_b
: gen_helper_gvec_sdot_idx_b
;
7030 /* rm is just Vm, and index is M. */
7031 data
= extract32(insn
, 5, 1); /* index */
7032 rm
= extract32(insn
, 0, 4);
7033 } else if ((insn
& 0xffa00f10) == 0xfe000810) {
7034 /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
7035 int is_s
= extract32(insn
, 20, 1);
7036 int vm20
= extract32(insn
, 0, 3);
7037 int vm3
= extract32(insn
, 3, 1);
7038 int m
= extract32(insn
, 5, 1);
7041 if (!dc_isar_feature(aa32_fhm
, s
)) {
7046 index
= m
* 2 + vm3
;
7052 data
= (index
<< 2) | is_s
; /* is_2 == 0 */
7053 fn_gvec_ptr
= gen_helper_gvec_fmlal_idx_a32
;
7059 VFP_DREG_D(rd
, insn
);
7063 if (q
|| !is_long
) {
7064 VFP_DREG_N(rn
, insn
);
7065 if (rn
& q
& !is_long
) {
7068 off_rn
= vfp_reg_offset(1, rn
);
7069 off_rm
= vfp_reg_offset(1, rm
);
7071 rn
= VFP_SREG_N(insn
);
7072 off_rn
= vfp_reg_offset(0, rn
);
7073 off_rm
= vfp_reg_offset(0, rm
);
7075 if (s
->fp_excp_el
) {
7076 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
7077 syn_simd_access_trap(1, 0xe, false), s
->fp_excp_el
);
7080 if (!s
->vfp_enabled
) {
7084 opr_sz
= (1 + q
) * 8;
7090 ptr
= get_fpstatus_ptr(1);
7092 tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd
), off_rn
, off_rm
, ptr
,
7093 opr_sz
, opr_sz
, data
, fn_gvec_ptr
);
7095 tcg_temp_free_ptr(ptr
);
7098 tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd
), off_rn
, off_rm
,
7099 opr_sz
, opr_sz
, data
, fn_gvec
);
7104 static int disas_coproc_insn(DisasContext
*s
, uint32_t insn
)
7106 int cpnum
, is64
, crn
, crm
, opc1
, opc2
, isread
, rt
, rt2
;
7107 const ARMCPRegInfo
*ri
;
7109 cpnum
= (insn
>> 8) & 0xf;
7111 /* First check for coprocessor space used for XScale/iwMMXt insns */
7112 if (arm_dc_feature(s
, ARM_FEATURE_XSCALE
) && (cpnum
< 2)) {
7113 if (extract32(s
->c15_cpar
, cpnum
, 1) == 0) {
7116 if (arm_dc_feature(s
, ARM_FEATURE_IWMMXT
)) {
7117 return disas_iwmmxt_insn(s
, insn
);
7118 } else if (arm_dc_feature(s
, ARM_FEATURE_XSCALE
)) {
7119 return disas_dsp_insn(s
, insn
);
7124 /* Otherwise treat as a generic register access */
7125 is64
= (insn
& (1 << 25)) == 0;
7126 if (!is64
&& ((insn
& (1 << 4)) == 0)) {
7134 opc1
= (insn
>> 4) & 0xf;
7136 rt2
= (insn
>> 16) & 0xf;
7138 crn
= (insn
>> 16) & 0xf;
7139 opc1
= (insn
>> 21) & 7;
7140 opc2
= (insn
>> 5) & 7;
7143 isread
= (insn
>> 20) & 1;
7144 rt
= (insn
>> 12) & 0xf;
7146 ri
= get_arm_cp_reginfo(s
->cp_regs
,
7147 ENCODE_CP_REG(cpnum
, is64
, s
->ns
, crn
, crm
, opc1
, opc2
));
7149 /* Check access permissions */
7150 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
7155 (arm_dc_feature(s
, ARM_FEATURE_XSCALE
) && cpnum
< 14)) {
7156 /* Emit code to perform further access permissions checks at
7157 * runtime; this may result in an exception.
7158 * Note that on XScale all cp0..c13 registers do an access check
7159 * call in order to handle c15_cpar.
7162 TCGv_i32 tcg_syn
, tcg_isread
;
7165 /* Note that since we are an implementation which takes an
7166 * exception on a trapped conditional instruction only if the
7167 * instruction passes its condition code check, we can take
7168 * advantage of the clause in the ARM ARM that allows us to set
7169 * the COND field in the instruction to 0xE in all cases.
7170 * We could fish the actual condition out of the insn (ARM)
7171 * or the condexec bits (Thumb) but it isn't necessary.
7176 syndrome
= syn_cp14_rrt_trap(1, 0xe, opc1
, crm
, rt
, rt2
,
7179 syndrome
= syn_cp14_rt_trap(1, 0xe, opc1
, opc2
, crn
, crm
,
7185 syndrome
= syn_cp15_rrt_trap(1, 0xe, opc1
, crm
, rt
, rt2
,
7188 syndrome
= syn_cp15_rt_trap(1, 0xe, opc1
, opc2
, crn
, crm
,
7193 /* ARMv8 defines that only coprocessors 14 and 15 exist,
7194 * so this can only happen if this is an ARMv7 or earlier CPU,
7195 * in which case the syndrome information won't actually be
7198 assert(!arm_dc_feature(s
, ARM_FEATURE_V8
));
7199 syndrome
= syn_uncategorized();
7203 gen_set_condexec(s
);
7204 gen_set_pc_im(s
, s
->pc_curr
);
7205 tmpptr
= tcg_const_ptr(ri
);
7206 tcg_syn
= tcg_const_i32(syndrome
);
7207 tcg_isread
= tcg_const_i32(isread
);
7208 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
,
7210 tcg_temp_free_ptr(tmpptr
);
7211 tcg_temp_free_i32(tcg_syn
);
7212 tcg_temp_free_i32(tcg_isread
);
7213 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
7215 * The readfn or writefn might raise an exception;
7216 * synchronize the CPU state in case it does.
7218 gen_set_condexec(s
);
7219 gen_set_pc_im(s
, s
->pc_curr
);
7222 /* Handle special cases first */
7223 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
7230 gen_set_pc_im(s
, s
->base
.pc_next
);
7231 s
->base
.is_jmp
= DISAS_WFI
;
7237 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
7246 if (ri
->type
& ARM_CP_CONST
) {
7247 tmp64
= tcg_const_i64(ri
->resetvalue
);
7248 } else if (ri
->readfn
) {
7250 tmp64
= tcg_temp_new_i64();
7251 tmpptr
= tcg_const_ptr(ri
);
7252 gen_helper_get_cp_reg64(tmp64
, cpu_env
, tmpptr
);
7253 tcg_temp_free_ptr(tmpptr
);
7255 tmp64
= tcg_temp_new_i64();
7256 tcg_gen_ld_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
7258 tmp
= tcg_temp_new_i32();
7259 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
7260 store_reg(s
, rt
, tmp
);
7261 tmp
= tcg_temp_new_i32();
7262 tcg_gen_extrh_i64_i32(tmp
, tmp64
);
7263 tcg_temp_free_i64(tmp64
);
7264 store_reg(s
, rt2
, tmp
);
7267 if (ri
->type
& ARM_CP_CONST
) {
7268 tmp
= tcg_const_i32(ri
->resetvalue
);
7269 } else if (ri
->readfn
) {
7271 tmp
= tcg_temp_new_i32();
7272 tmpptr
= tcg_const_ptr(ri
);
7273 gen_helper_get_cp_reg(tmp
, cpu_env
, tmpptr
);
7274 tcg_temp_free_ptr(tmpptr
);
7276 tmp
= load_cpu_offset(ri
->fieldoffset
);
7279 /* Destination register of r15 for 32 bit loads sets
7280 * the condition codes from the high 4 bits of the value
7283 tcg_temp_free_i32(tmp
);
7285 store_reg(s
, rt
, tmp
);
7290 if (ri
->type
& ARM_CP_CONST
) {
7291 /* If not forbidden by access permissions, treat as WI */
7296 TCGv_i32 tmplo
, tmphi
;
7297 TCGv_i64 tmp64
= tcg_temp_new_i64();
7298 tmplo
= load_reg(s
, rt
);
7299 tmphi
= load_reg(s
, rt2
);
7300 tcg_gen_concat_i32_i64(tmp64
, tmplo
, tmphi
);
7301 tcg_temp_free_i32(tmplo
);
7302 tcg_temp_free_i32(tmphi
);
7304 TCGv_ptr tmpptr
= tcg_const_ptr(ri
);
7305 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tmp64
);
7306 tcg_temp_free_ptr(tmpptr
);
7308 tcg_gen_st_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
7310 tcg_temp_free_i64(tmp64
);
7315 tmp
= load_reg(s
, rt
);
7316 tmpptr
= tcg_const_ptr(ri
);
7317 gen_helper_set_cp_reg(cpu_env
, tmpptr
, tmp
);
7318 tcg_temp_free_ptr(tmpptr
);
7319 tcg_temp_free_i32(tmp
);
7321 TCGv_i32 tmp
= load_reg(s
, rt
);
7322 store_cpu_offset(tmp
, ri
->fieldoffset
);
7327 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
7328 /* I/O operations must end the TB here (whether read or write) */
7330 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
7331 /* We default to ending the TB on a coprocessor register write,
7332 * but allow this to be suppressed by the register definition
7333 * (usually only necessary to work around guest bugs).
7341 /* Unknown register; this might be a guest error or a QEMU
7342 * unimplemented feature.
7345 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
7346 "64 bit system register cp:%d opc1: %d crm:%d "
7348 isread
? "read" : "write", cpnum
, opc1
, crm
,
7349 s
->ns
? "non-secure" : "secure");
7351 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
7352 "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d "
7354 isread
? "read" : "write", cpnum
, opc1
, crn
, crm
, opc2
,
7355 s
->ns
? "non-secure" : "secure");
7362 /* Store a 64-bit value to a register pair. Clobbers val. */
7363 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
7366 tmp
= tcg_temp_new_i32();
7367 tcg_gen_extrl_i64_i32(tmp
, val
);
7368 store_reg(s
, rlow
, tmp
);
7369 tmp
= tcg_temp_new_i32();
7370 tcg_gen_extrh_i64_i32(tmp
, val
);
7371 store_reg(s
, rhigh
, tmp
);
7374 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
7375 static void gen_addq_lo(DisasContext
*s
, TCGv_i64 val
, int rlow
)
7380 /* Load value and extend to 64 bits. */
7381 tmp
= tcg_temp_new_i64();
7382 tmp2
= load_reg(s
, rlow
);
7383 tcg_gen_extu_i32_i64(tmp
, tmp2
);
7384 tcg_temp_free_i32(tmp2
);
7385 tcg_gen_add_i64(val
, val
, tmp
);
7386 tcg_temp_free_i64(tmp
);
7389 /* load and add a 64-bit value from a register pair. */
7390 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
7396 /* Load 64-bit value rd:rn. */
7397 tmpl
= load_reg(s
, rlow
);
7398 tmph
= load_reg(s
, rhigh
);
7399 tmp
= tcg_temp_new_i64();
7400 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
7401 tcg_temp_free_i32(tmpl
);
7402 tcg_temp_free_i32(tmph
);
7403 tcg_gen_add_i64(val
, val
, tmp
);
7404 tcg_temp_free_i64(tmp
);
7407 /* Set N and Z flags from hi|lo. */
7408 static void gen_logicq_cc(TCGv_i32 lo
, TCGv_i32 hi
)
7410 tcg_gen_mov_i32(cpu_NF
, hi
);
7411 tcg_gen_or_i32(cpu_ZF
, lo
, hi
);
7414 /* Load/Store exclusive instructions are implemented by remembering
7415 the value/address loaded, and seeing if these are the same
7416 when the store is performed. This should be sufficient to implement
7417 the architecturally mandated semantics, and avoids having to monitor
7418 regular stores. The compare vs the remembered value is done during
7419 the cmpxchg operation, but we must compare the addresses manually. */
7420 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
7421 TCGv_i32 addr
, int size
)
7423 TCGv_i32 tmp
= tcg_temp_new_i32();
7424 MemOp opc
= size
| MO_ALIGN
| s
->be_data
;
7429 TCGv_i32 tmp2
= tcg_temp_new_i32();
7430 TCGv_i64 t64
= tcg_temp_new_i64();
7432 /* For AArch32, architecturally the 32-bit word at the lowest
7433 * address is always Rt and the one at addr+4 is Rt2, even if
7434 * the CPU is big-endian. That means we don't want to do a
7435 * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if
7436 * for an architecturally 64-bit access, but instead do a
7437 * 64-bit access using MO_BE if appropriate and then split
7439 * This only makes a difference for BE32 user-mode, where
7440 * frob64() must not flip the two halves of the 64-bit data
7441 * but this code must treat BE32 user-mode like BE32 system.
7443 TCGv taddr
= gen_aa32_addr(s
, addr
, opc
);
7445 tcg_gen_qemu_ld_i64(t64
, taddr
, get_mem_index(s
), opc
);
7446 tcg_temp_free(taddr
);
7447 tcg_gen_mov_i64(cpu_exclusive_val
, t64
);
7448 if (s
->be_data
== MO_BE
) {
7449 tcg_gen_extr_i64_i32(tmp2
, tmp
, t64
);
7451 tcg_gen_extr_i64_i32(tmp
, tmp2
, t64
);
7453 tcg_temp_free_i64(t64
);
7455 store_reg(s
, rt2
, tmp2
);
7457 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
), opc
);
7458 tcg_gen_extu_i32_i64(cpu_exclusive_val
, tmp
);
7461 store_reg(s
, rt
, tmp
);
7462 tcg_gen_extu_i32_i64(cpu_exclusive_addr
, addr
);
7465 static void gen_clrex(DisasContext
*s
)
7467 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
7470 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
7471 TCGv_i32 addr
, int size
)
7473 TCGv_i32 t0
, t1
, t2
;
7476 TCGLabel
*done_label
;
7477 TCGLabel
*fail_label
;
7478 MemOp opc
= size
| MO_ALIGN
| s
->be_data
;
7480 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
7486 fail_label
= gen_new_label();
7487 done_label
= gen_new_label();
7488 extaddr
= tcg_temp_new_i64();
7489 tcg_gen_extu_i32_i64(extaddr
, addr
);
7490 tcg_gen_brcond_i64(TCG_COND_NE
, extaddr
, cpu_exclusive_addr
, fail_label
);
7491 tcg_temp_free_i64(extaddr
);
7493 taddr
= gen_aa32_addr(s
, addr
, opc
);
7494 t0
= tcg_temp_new_i32();
7495 t1
= load_reg(s
, rt
);
7497 TCGv_i64 o64
= tcg_temp_new_i64();
7498 TCGv_i64 n64
= tcg_temp_new_i64();
7500 t2
= load_reg(s
, rt2
);
7501 /* For AArch32, architecturally the 32-bit word at the lowest
7502 * address is always Rt and the one at addr+4 is Rt2, even if
7503 * the CPU is big-endian. Since we're going to treat this as a
7504 * single 64-bit BE store, we need to put the two halves in the
7505 * opposite order for BE to LE, so that they end up in the right
7507 * We don't want gen_aa32_frob64() because that does the wrong
7508 * thing for BE32 usermode.
7510 if (s
->be_data
== MO_BE
) {
7511 tcg_gen_concat_i32_i64(n64
, t2
, t1
);
7513 tcg_gen_concat_i32_i64(n64
, t1
, t2
);
7515 tcg_temp_free_i32(t2
);
7517 tcg_gen_atomic_cmpxchg_i64(o64
, taddr
, cpu_exclusive_val
, n64
,
7518 get_mem_index(s
), opc
);
7519 tcg_temp_free_i64(n64
);
7521 tcg_gen_setcond_i64(TCG_COND_NE
, o64
, o64
, cpu_exclusive_val
);
7522 tcg_gen_extrl_i64_i32(t0
, o64
);
7524 tcg_temp_free_i64(o64
);
7526 t2
= tcg_temp_new_i32();
7527 tcg_gen_extrl_i64_i32(t2
, cpu_exclusive_val
);
7528 tcg_gen_atomic_cmpxchg_i32(t0
, taddr
, t2
, t1
, get_mem_index(s
), opc
);
7529 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t2
);
7530 tcg_temp_free_i32(t2
);
7532 tcg_temp_free_i32(t1
);
7533 tcg_temp_free(taddr
);
7534 tcg_gen_mov_i32(cpu_R
[rd
], t0
);
7535 tcg_temp_free_i32(t0
);
7536 tcg_gen_br(done_label
);
7538 gen_set_label(fail_label
);
7539 tcg_gen_movi_i32(cpu_R
[rd
], 1);
7540 gen_set_label(done_label
);
7541 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
7547 * @mode: mode field from insn (which stack to store to)
7548 * @amode: addressing mode (DA/IA/DB/IB), encoded as per P,U bits in ARM insn
7549 * @writeback: true if writeback bit set
7551 * Generate code for the SRS (Store Return State) insn.
7553 static void gen_srs(DisasContext
*s
,
7554 uint32_t mode
, uint32_t amode
, bool writeback
)
7561 * - trapped to EL3 if EL3 is AArch64 and we are at Secure EL1
7562 * and specified mode is monitor mode
7563 * - UNDEFINED in Hyp mode
7564 * - UNPREDICTABLE in User or System mode
7565 * - UNPREDICTABLE if the specified mode is:
7566 * -- not implemented
7567 * -- not a valid mode number
7568 * -- a mode that's at a higher exception level
7569 * -- Monitor, if we are Non-secure
7570 * For the UNPREDICTABLE cases we choose to UNDEF.
7572 if (s
->current_el
== 1 && !s
->ns
&& mode
== ARM_CPU_MODE_MON
) {
7573 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(), 3);
7577 if (s
->current_el
== 0 || s
->current_el
== 2) {
7582 case ARM_CPU_MODE_USR
:
7583 case ARM_CPU_MODE_FIQ
:
7584 case ARM_CPU_MODE_IRQ
:
7585 case ARM_CPU_MODE_SVC
:
7586 case ARM_CPU_MODE_ABT
:
7587 case ARM_CPU_MODE_UND
:
7588 case ARM_CPU_MODE_SYS
:
7590 case ARM_CPU_MODE_HYP
:
7591 if (s
->current_el
== 1 || !arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
7595 case ARM_CPU_MODE_MON
:
7596 /* No need to check specifically for "are we non-secure" because
7597 * we've already made EL0 UNDEF and handled the trap for S-EL1;
7598 * so if this isn't EL3 then we must be non-secure.
7600 if (s
->current_el
!= 3) {
7609 unallocated_encoding(s
);
7613 addr
= tcg_temp_new_i32();
7614 tmp
= tcg_const_i32(mode
);
7615 /* get_r13_banked() will raise an exception if called from System mode */
7616 gen_set_condexec(s
);
7617 gen_set_pc_im(s
, s
->pc_curr
);
7618 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
7619 tcg_temp_free_i32(tmp
);
7636 tcg_gen_addi_i32(addr
, addr
, offset
);
7637 tmp
= load_reg(s
, 14);
7638 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
7639 tcg_temp_free_i32(tmp
);
7640 tmp
= load_cpu_field(spsr
);
7641 tcg_gen_addi_i32(addr
, addr
, 4);
7642 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
7643 tcg_temp_free_i32(tmp
);
7661 tcg_gen_addi_i32(addr
, addr
, offset
);
7662 tmp
= tcg_const_i32(mode
);
7663 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
7664 tcg_temp_free_i32(tmp
);
7666 tcg_temp_free_i32(addr
);
7667 s
->base
.is_jmp
= DISAS_UPDATE
;
7670 /* Generate a label used for skipping this instruction */
7671 static void arm_gen_condlabel(DisasContext
*s
)
7674 s
->condlabel
= gen_new_label();
7679 /* Skip this instruction if the ARM condition is false */
7680 static void arm_skip_unless(DisasContext
*s
, uint32_t cond
)
7682 arm_gen_condlabel(s
);
7683 arm_gen_test_cc(cond
^ 1, s
->condlabel
);
7686 static void disas_arm_insn(DisasContext
*s
, unsigned int insn
)
7688 unsigned int cond
, val
, op1
, i
, shift
, rm
, rs
, rn
, rd
, sh
;
7695 /* M variants do not implement ARM mode; this must raise the INVSTATE
7696 * UsageFault exception.
7698 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
7699 gen_exception_insn(s
, s
->pc_curr
, EXCP_INVSTATE
, syn_uncategorized(),
7700 default_exception_el(s
));
7705 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
7706 * choose to UNDEF. In ARMv5 and above the space is used
7707 * for miscellaneous unconditional instructions.
7711 /* Unconditional instructions. */
7712 if (((insn
>> 25) & 7) == 1) {
7713 /* NEON Data processing. */
7714 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
7718 if (disas_neon_data_insn(s
, insn
)) {
7723 if ((insn
& 0x0f100000) == 0x04000000) {
7724 /* NEON load/store. */
7725 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
7729 if (disas_neon_ls_insn(s
, insn
)) {
7734 if ((insn
& 0x0f000e10) == 0x0e000a00) {
7736 if (disas_vfp_insn(s
, insn
)) {
7741 if (((insn
& 0x0f30f000) == 0x0510f000) ||
7742 ((insn
& 0x0f30f010) == 0x0710f000)) {
7743 if ((insn
& (1 << 22)) == 0) {
7745 if (!arm_dc_feature(s
, ARM_FEATURE_V7MP
)) {
7749 /* Otherwise PLD; v5TE+ */
7753 if (((insn
& 0x0f70f000) == 0x0450f000) ||
7754 ((insn
& 0x0f70f010) == 0x0650f000)) {
7756 return; /* PLI; V7 */
7758 if (((insn
& 0x0f700000) == 0x04100000) ||
7759 ((insn
& 0x0f700010) == 0x06100000)) {
7760 if (!arm_dc_feature(s
, ARM_FEATURE_V7MP
)) {
7763 return; /* v7MP: Unallocated memory hint: must NOP */
7766 if ((insn
& 0x0ffffdff) == 0x01010000) {
7769 if (((insn
>> 9) & 1) != !!(s
->be_data
== MO_BE
)) {
7770 gen_helper_setend(cpu_env
);
7771 s
->base
.is_jmp
= DISAS_UPDATE
;
7774 } else if ((insn
& 0x0fffff00) == 0x057ff000) {
7775 switch ((insn
>> 4) & 0xf) {
7783 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
7786 /* We need to break the TB after this insn to execute
7787 * self-modifying code correctly and also to take
7788 * any pending interrupts immediately.
7790 gen_goto_tb(s
, 0, s
->base
.pc_next
);
7793 if ((insn
& 0xf) || !dc_isar_feature(aa32_sb
, s
)) {
7797 * TODO: There is no speculation barrier opcode
7798 * for TCG; MB and end the TB instead.
7800 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
7801 gen_goto_tb(s
, 0, s
->base
.pc_next
);
7806 } else if ((insn
& 0x0e5fffe0) == 0x084d0500) {
7809 gen_srs(s
, (insn
& 0x1f), (insn
>> 23) & 3, insn
& (1 << 21));
7811 } else if ((insn
& 0x0e50ffe0) == 0x08100a00) {
7817 rn
= (insn
>> 16) & 0xf;
7818 addr
= load_reg(s
, rn
);
7819 i
= (insn
>> 23) & 3;
7821 case 0: offset
= -4; break; /* DA */
7822 case 1: offset
= 0; break; /* IA */
7823 case 2: offset
= -8; break; /* DB */
7824 case 3: offset
= 4; break; /* IB */
7828 tcg_gen_addi_i32(addr
, addr
, offset
);
7829 /* Load PC into tmp and CPSR into tmp2. */
7830 tmp
= tcg_temp_new_i32();
7831 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
7832 tcg_gen_addi_i32(addr
, addr
, 4);
7833 tmp2
= tcg_temp_new_i32();
7834 gen_aa32_ld32u(s
, tmp2
, addr
, get_mem_index(s
));
7835 if (insn
& (1 << 21)) {
7836 /* Base writeback. */
7838 case 0: offset
= -8; break;
7839 case 1: offset
= 4; break;
7840 case 2: offset
= -4; break;
7841 case 3: offset
= 0; break;
7845 tcg_gen_addi_i32(addr
, addr
, offset
);
7846 store_reg(s
, rn
, addr
);
7848 tcg_temp_free_i32(addr
);
7850 gen_rfe(s
, tmp
, tmp2
);
7852 } else if ((insn
& 0x0e000000) == 0x0a000000) {
7853 /* branch link and change to thumb (blx <offset>) */
7856 tmp
= tcg_temp_new_i32();
7857 tcg_gen_movi_i32(tmp
, s
->base
.pc_next
);
7858 store_reg(s
, 14, tmp
);
7859 /* Sign-extend the 24-bit offset */
7860 offset
= (((int32_t)insn
) << 8) >> 8;
7862 /* offset * 4 + bit24 * 2 + (thumb bit) */
7863 val
+= (offset
<< 2) | ((insn
>> 23) & 2) | 1;
7864 /* protected by ARCH(5); above, near the start of uncond block */
7867 } else if ((insn
& 0x0e000f00) == 0x0c000100) {
7868 if (arm_dc_feature(s
, ARM_FEATURE_IWMMXT
)) {
7869 /* iWMMXt register transfer. */
7870 if (extract32(s
->c15_cpar
, 1, 1)) {
7871 if (!disas_iwmmxt_insn(s
, insn
)) {
7876 } else if ((insn
& 0x0e000a00) == 0x0c000800
7877 && arm_dc_feature(s
, ARM_FEATURE_V8
)) {
7878 if (disas_neon_insn_3same_ext(s
, insn
)) {
7882 } else if ((insn
& 0x0f000a00) == 0x0e000800
7883 && arm_dc_feature(s
, ARM_FEATURE_V8
)) {
7884 if (disas_neon_insn_2reg_scalar_ext(s
, insn
)) {
7888 } else if ((insn
& 0x0fe00000) == 0x0c400000) {
7889 /* Coprocessor double register transfer. */
7891 } else if ((insn
& 0x0f000010) == 0x0e000010) {
7892 /* Additional coprocessor register transfer. */
7893 } else if ((insn
& 0x0ff10020) == 0x01000000) {
7896 /* cps (privileged) */
7900 if (insn
& (1 << 19)) {
7901 if (insn
& (1 << 8))
7903 if (insn
& (1 << 7))
7905 if (insn
& (1 << 6))
7907 if (insn
& (1 << 18))
7910 if (insn
& (1 << 17)) {
7912 val
|= (insn
& 0x1f);
7915 gen_set_psr_im(s
, mask
, 0, val
);
7922 /* if not always execute, we generate a conditional jump to
7924 arm_skip_unless(s
, cond
);
7926 if ((insn
& 0x0f900000) == 0x03000000) {
7927 if ((insn
& (1 << 21)) == 0) {
7929 rd
= (insn
>> 12) & 0xf;
7930 val
= ((insn
>> 4) & 0xf000) | (insn
& 0xfff);
7931 if ((insn
& (1 << 22)) == 0) {
7933 tmp
= tcg_temp_new_i32();
7934 tcg_gen_movi_i32(tmp
, val
);
7937 tmp
= load_reg(s
, rd
);
7938 tcg_gen_ext16u_i32(tmp
, tmp
);
7939 tcg_gen_ori_i32(tmp
, tmp
, val
<< 16);
7941 store_reg(s
, rd
, tmp
);
7943 if (((insn
>> 12) & 0xf) != 0xf)
7945 if (((insn
>> 16) & 0xf) == 0) {
7946 gen_nop_hint(s
, insn
& 0xff);
7948 /* CPSR = immediate */
7950 shift
= ((insn
>> 8) & 0xf) * 2;
7951 val
= ror32(val
, shift
);
7952 i
= ((insn
& (1 << 22)) != 0);
7953 if (gen_set_psr_im(s
, msr_mask(s
, (insn
>> 16) & 0xf, i
),
7959 } else if ((insn
& 0x0f900000) == 0x01000000
7960 && (insn
& 0x00000090) != 0x00000090) {
7961 /* miscellaneous instructions */
7962 op1
= (insn
>> 21) & 3;
7963 sh
= (insn
>> 4) & 0xf;
7966 case 0x0: /* MSR, MRS */
7967 if (insn
& (1 << 9)) {
7968 /* MSR (banked) and MRS (banked) */
7969 int sysm
= extract32(insn
, 16, 4) |
7970 (extract32(insn
, 8, 1) << 4);
7971 int r
= extract32(insn
, 22, 1);
7975 gen_msr_banked(s
, r
, sysm
, rm
);
7978 int rd
= extract32(insn
, 12, 4);
7980 gen_mrs_banked(s
, r
, sysm
, rd
);
7985 /* MSR, MRS (for PSRs) */
7988 tmp
= load_reg(s
, rm
);
7989 i
= ((op1
& 2) != 0);
7990 if (gen_set_psr(s
, msr_mask(s
, (insn
>> 16) & 0xf, i
), i
, tmp
))
7994 rd
= (insn
>> 12) & 0xf;
7998 tmp
= load_cpu_field(spsr
);
8000 tmp
= tcg_temp_new_i32();
8001 gen_helper_cpsr_read(tmp
, cpu_env
);
8003 store_reg(s
, rd
, tmp
);
8008 /* branch/exchange thumb (bx). */
8010 tmp
= load_reg(s
, rm
);
8012 } else if (op1
== 3) {
8015 rd
= (insn
>> 12) & 0xf;
8016 tmp
= load_reg(s
, rm
);
8017 tcg_gen_clzi_i32(tmp
, tmp
, 32);
8018 store_reg(s
, rd
, tmp
);
8026 /* Trivial implementation equivalent to bx. */
8027 tmp
= load_reg(s
, rm
);
8038 /* branch link/exchange thumb (blx) */
8039 tmp
= load_reg(s
, rm
);
8040 tmp2
= tcg_temp_new_i32();
8041 tcg_gen_movi_i32(tmp2
, s
->base
.pc_next
);
8042 store_reg(s
, 14, tmp2
);
8048 uint32_t c
= extract32(insn
, 8, 4);
8050 /* Check this CPU supports ARMv8 CRC instructions.
8051 * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED.
8052 * Bits 8, 10 and 11 should be zero.
8054 if (!dc_isar_feature(aa32_crc32
, s
) || op1
== 0x3 || (c
& 0xd) != 0) {
8058 rn
= extract32(insn
, 16, 4);
8059 rd
= extract32(insn
, 12, 4);
8061 tmp
= load_reg(s
, rn
);
8062 tmp2
= load_reg(s
, rm
);
8064 tcg_gen_andi_i32(tmp2
, tmp2
, 0xff);
8065 } else if (op1
== 1) {
8066 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff);
8068 tmp3
= tcg_const_i32(1 << op1
);
8070 gen_helper_crc32c(tmp
, tmp
, tmp2
, tmp3
);
8072 gen_helper_crc32(tmp
, tmp
, tmp2
, tmp3
);
8074 tcg_temp_free_i32(tmp2
);
8075 tcg_temp_free_i32(tmp3
);
8076 store_reg(s
, rd
, tmp
);
8079 case 0x5: /* saturating add/subtract */
8081 rd
= (insn
>> 12) & 0xf;
8082 rn
= (insn
>> 16) & 0xf;
8083 tmp
= load_reg(s
, rm
);
8084 tmp2
= load_reg(s
, rn
);
8086 gen_helper_add_saturate(tmp2
, cpu_env
, tmp2
, tmp2
);
8088 gen_helper_sub_saturate(tmp
, cpu_env
, tmp
, tmp2
);
8090 gen_helper_add_saturate(tmp
, cpu_env
, tmp
, tmp2
);
8091 tcg_temp_free_i32(tmp2
);
8092 store_reg(s
, rd
, tmp
);
8094 case 0x6: /* ERET */
8098 if (!arm_dc_feature(s
, ARM_FEATURE_V7VE
)) {
8101 if ((insn
& 0x000fff0f) != 0x0000000e) {
8102 /* UNPREDICTABLE; we choose to UNDEF */
8106 if (s
->current_el
== 2) {
8107 tmp
= load_cpu_field(elr_el
[2]);
8109 tmp
= load_reg(s
, 14);
8111 gen_exception_return(s
, tmp
);
8115 int imm16
= extract32(insn
, 0, 4) | (extract32(insn
, 8, 12) << 4);
8124 gen_exception_bkpt_insn(s
, syn_aa32_bkpt(imm16
, false));
8127 /* Hypervisor call (v7) */
8135 /* Secure monitor call (v6+) */
8143 g_assert_not_reached();
8147 case 0x8: /* signed multiply */
8152 rs
= (insn
>> 8) & 0xf;
8153 rn
= (insn
>> 12) & 0xf;
8154 rd
= (insn
>> 16) & 0xf;
8156 /* (32 * 16) >> 16 */
8157 tmp
= load_reg(s
, rm
);
8158 tmp2
= load_reg(s
, rs
);
8160 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
8163 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
8164 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
8165 tmp
= tcg_temp_new_i32();
8166 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
8167 tcg_temp_free_i64(tmp64
);
8168 if ((sh
& 2) == 0) {
8169 tmp2
= load_reg(s
, rn
);
8170 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
8171 tcg_temp_free_i32(tmp2
);
8173 store_reg(s
, rd
, tmp
);
8176 tmp
= load_reg(s
, rm
);
8177 tmp2
= load_reg(s
, rs
);
8178 gen_mulxy(tmp
, tmp2
, sh
& 2, sh
& 4);
8179 tcg_temp_free_i32(tmp2
);
8181 tmp64
= tcg_temp_new_i64();
8182 tcg_gen_ext_i32_i64(tmp64
, tmp
);
8183 tcg_temp_free_i32(tmp
);
8184 gen_addq(s
, tmp64
, rn
, rd
);
8185 gen_storeq_reg(s
, rn
, rd
, tmp64
);
8186 tcg_temp_free_i64(tmp64
);
8189 tmp2
= load_reg(s
, rn
);
8190 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
8191 tcg_temp_free_i32(tmp2
);
8193 store_reg(s
, rd
, tmp
);
8200 } else if (((insn
& 0x0e000000) == 0 &&
8201 (insn
& 0x00000090) != 0x90) ||
8202 ((insn
& 0x0e000000) == (1 << 25))) {
8203 int set_cc
, logic_cc
, shiftop
;
8205 op1
= (insn
>> 21) & 0xf;
8206 set_cc
= (insn
>> 20) & 1;
8207 logic_cc
= table_logic_cc
[op1
] & set_cc
;
8209 /* data processing instruction */
8210 if (insn
& (1 << 25)) {
8211 /* immediate operand */
8213 shift
= ((insn
>> 8) & 0xf) * 2;
8214 val
= ror32(val
, shift
);
8215 tmp2
= tcg_temp_new_i32();
8216 tcg_gen_movi_i32(tmp2
, val
);
8217 if (logic_cc
&& shift
) {
8218 gen_set_CF_bit31(tmp2
);
8223 tmp2
= load_reg(s
, rm
);
8224 shiftop
= (insn
>> 5) & 3;
8225 if (!(insn
& (1 << 4))) {
8226 shift
= (insn
>> 7) & 0x1f;
8227 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
8229 rs
= (insn
>> 8) & 0xf;
8230 tmp
= load_reg(s
, rs
);
8231 gen_arm_shift_reg(tmp2
, shiftop
, tmp
, logic_cc
);
8234 if (op1
!= 0x0f && op1
!= 0x0d) {
8235 rn
= (insn
>> 16) & 0xf;
8236 tmp
= load_reg(s
, rn
);
8240 rd
= (insn
>> 12) & 0xf;
8243 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
8247 store_reg_bx(s
, rd
, tmp
);
8250 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
8254 store_reg_bx(s
, rd
, tmp
);
8257 if (set_cc
&& rd
== 15) {
8258 /* SUBS r15, ... is used for exception return. */
8262 gen_sub_CC(tmp
, tmp
, tmp2
);
8263 gen_exception_return(s
, tmp
);
8266 gen_sub_CC(tmp
, tmp
, tmp2
);
8268 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8270 store_reg_bx(s
, rd
, tmp
);
8275 gen_sub_CC(tmp
, tmp2
, tmp
);
8277 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
8279 store_reg_bx(s
, rd
, tmp
);
8283 gen_add_CC(tmp
, tmp
, tmp2
);
8285 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8287 store_reg_bx(s
, rd
, tmp
);
8291 gen_adc_CC(tmp
, tmp
, tmp2
);
8293 gen_add_carry(tmp
, tmp
, tmp2
);
8295 store_reg_bx(s
, rd
, tmp
);
8299 gen_sbc_CC(tmp
, tmp
, tmp2
);
8301 gen_sub_carry(tmp
, tmp
, tmp2
);
8303 store_reg_bx(s
, rd
, tmp
);
8307 gen_sbc_CC(tmp
, tmp2
, tmp
);
8309 gen_sub_carry(tmp
, tmp2
, tmp
);
8311 store_reg_bx(s
, rd
, tmp
);
8315 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
8318 tcg_temp_free_i32(tmp
);
8322 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
8325 tcg_temp_free_i32(tmp
);
8329 gen_sub_CC(tmp
, tmp
, tmp2
);
8331 tcg_temp_free_i32(tmp
);
8335 gen_add_CC(tmp
, tmp
, tmp2
);
8337 tcg_temp_free_i32(tmp
);
8340 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
8344 store_reg_bx(s
, rd
, tmp
);
8347 if (logic_cc
&& rd
== 15) {
8348 /* MOVS r15, ... is used for exception return. */
8352 gen_exception_return(s
, tmp2
);
8357 store_reg_bx(s
, rd
, tmp2
);
8361 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
8365 store_reg_bx(s
, rd
, tmp
);
8369 tcg_gen_not_i32(tmp2
, tmp2
);
8373 store_reg_bx(s
, rd
, tmp2
);
8376 if (op1
!= 0x0f && op1
!= 0x0d) {
8377 tcg_temp_free_i32(tmp2
);
8380 /* other instructions */
8381 op1
= (insn
>> 24) & 0xf;
8385 /* multiplies, extra load/stores */
8386 sh
= (insn
>> 5) & 3;
8389 rd
= (insn
>> 16) & 0xf;
8390 rn
= (insn
>> 12) & 0xf;
8391 rs
= (insn
>> 8) & 0xf;
8393 op1
= (insn
>> 20) & 0xf;
8395 case 0: case 1: case 2: case 3: case 6:
8397 tmp
= load_reg(s
, rs
);
8398 tmp2
= load_reg(s
, rm
);
8399 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
8400 tcg_temp_free_i32(tmp2
);
8401 if (insn
& (1 << 22)) {
8402 /* Subtract (mls) */
8404 tmp2
= load_reg(s
, rn
);
8405 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
8406 tcg_temp_free_i32(tmp2
);
8407 } else if (insn
& (1 << 21)) {
8409 tmp2
= load_reg(s
, rn
);
8410 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8411 tcg_temp_free_i32(tmp2
);
8413 if (insn
& (1 << 20))
8415 store_reg(s
, rd
, tmp
);
8418 /* 64 bit mul double accumulate (UMAAL) */
8420 tmp
= load_reg(s
, rs
);
8421 tmp2
= load_reg(s
, rm
);
8422 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
8423 gen_addq_lo(s
, tmp64
, rn
);
8424 gen_addq_lo(s
, tmp64
, rd
);
8425 gen_storeq_reg(s
, rn
, rd
, tmp64
);
8426 tcg_temp_free_i64(tmp64
);
8428 case 8: case 9: case 10: case 11:
8429 case 12: case 13: case 14: case 15:
8430 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
8431 tmp
= load_reg(s
, rs
);
8432 tmp2
= load_reg(s
, rm
);
8433 if (insn
& (1 << 22)) {
8434 tcg_gen_muls2_i32(tmp
, tmp2
, tmp
, tmp2
);
8436 tcg_gen_mulu2_i32(tmp
, tmp2
, tmp
, tmp2
);
8438 if (insn
& (1 << 21)) { /* mult accumulate */
8439 TCGv_i32 al
= load_reg(s
, rn
);
8440 TCGv_i32 ah
= load_reg(s
, rd
);
8441 tcg_gen_add2_i32(tmp
, tmp2
, tmp
, tmp2
, al
, ah
);
8442 tcg_temp_free_i32(al
);
8443 tcg_temp_free_i32(ah
);
8445 if (insn
& (1 << 20)) {
8446 gen_logicq_cc(tmp
, tmp2
);
8448 store_reg(s
, rn
, tmp
);
8449 store_reg(s
, rd
, tmp2
);
8455 rn
= (insn
>> 16) & 0xf;
8456 rd
= (insn
>> 12) & 0xf;
8457 if (insn
& (1 << 23)) {
8458 /* load/store exclusive */
8459 bool is_ld
= extract32(insn
, 20, 1);
8460 bool is_lasr
= !extract32(insn
, 8, 1);
8461 int op2
= (insn
>> 8) & 3;
8462 op1
= (insn
>> 21) & 0x3;
8465 case 0: /* lda/stl */
8471 case 1: /* reserved */
8473 case 2: /* ldaex/stlex */
8476 case 3: /* ldrex/strex */
8485 addr
= tcg_temp_local_new_i32();
8486 load_reg_var(s
, addr
, rn
);
8488 if (is_lasr
&& !is_ld
) {
8489 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
8494 tmp
= tcg_temp_new_i32();
8497 gen_aa32_ld32u_iss(s
, tmp
, addr
,
8502 gen_aa32_ld8u_iss(s
, tmp
, addr
,
8507 gen_aa32_ld16u_iss(s
, tmp
, addr
,
8514 store_reg(s
, rd
, tmp
);
8517 tmp
= load_reg(s
, rm
);
8520 gen_aa32_st32_iss(s
, tmp
, addr
,
8525 gen_aa32_st8_iss(s
, tmp
, addr
,
8530 gen_aa32_st16_iss(s
, tmp
, addr
,
8537 tcg_temp_free_i32(tmp
);
8542 gen_load_exclusive(s
, rd
, 15, addr
, 2);
8544 case 1: /* ldrexd */
8545 gen_load_exclusive(s
, rd
, rd
+ 1, addr
, 3);
8547 case 2: /* ldrexb */
8548 gen_load_exclusive(s
, rd
, 15, addr
, 0);
8550 case 3: /* ldrexh */
8551 gen_load_exclusive(s
, rd
, 15, addr
, 1);
8560 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 2);
8562 case 1: /* strexd */
8563 gen_store_exclusive(s
, rd
, rm
, rm
+ 1, addr
, 3);
8565 case 2: /* strexb */
8566 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 0);
8568 case 3: /* strexh */
8569 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 1);
8575 tcg_temp_free_i32(addr
);
8577 if (is_lasr
&& is_ld
) {
8578 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
8580 } else if ((insn
& 0x00300f00) == 0) {
8581 /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
8586 MemOp opc
= s
->be_data
;
8590 if (insn
& (1 << 22)) {
8593 opc
|= MO_UL
| MO_ALIGN
;
8596 addr
= load_reg(s
, rn
);
8597 taddr
= gen_aa32_addr(s
, addr
, opc
);
8598 tcg_temp_free_i32(addr
);
8600 tmp
= load_reg(s
, rm
);
8601 tcg_gen_atomic_xchg_i32(tmp
, taddr
, tmp
,
8602 get_mem_index(s
), opc
);
8603 tcg_temp_free(taddr
);
8604 store_reg(s
, rd
, tmp
);
8611 bool load
= insn
& (1 << 20);
8612 bool wbit
= insn
& (1 << 21);
8613 bool pbit
= insn
& (1 << 24);
8614 bool doubleword
= false;
8617 /* Misc load/store */
8618 rn
= (insn
>> 16) & 0xf;
8619 rd
= (insn
>> 12) & 0xf;
8621 /* ISS not valid if writeback */
8622 issinfo
= (pbit
& !wbit
) ? rd
: ISSInvalid
;
8624 if (!load
&& (sh
& 2)) {
8628 /* UNPREDICTABLE; we choose to UNDEF */
8631 load
= (sh
& 1) == 0;
8635 addr
= load_reg(s
, rn
);
8637 gen_add_datah_offset(s
, insn
, 0, addr
);
8644 tmp
= load_reg(s
, rd
);
8645 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
8646 tcg_temp_free_i32(tmp
);
8647 tcg_gen_addi_i32(addr
, addr
, 4);
8648 tmp
= load_reg(s
, rd
+ 1);
8649 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
8650 tcg_temp_free_i32(tmp
);
8653 tmp
= tcg_temp_new_i32();
8654 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
8655 store_reg(s
, rd
, tmp
);
8656 tcg_gen_addi_i32(addr
, addr
, 4);
8657 tmp
= tcg_temp_new_i32();
8658 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
8661 address_offset
= -4;
8664 tmp
= tcg_temp_new_i32();
8667 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
),
8671 gen_aa32_ld8s_iss(s
, tmp
, addr
, get_mem_index(s
),
8676 gen_aa32_ld16s_iss(s
, tmp
, addr
, get_mem_index(s
),
8682 tmp
= load_reg(s
, rd
);
8683 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
), issinfo
);
8684 tcg_temp_free_i32(tmp
);
8686 /* Perform base writeback before the loaded value to
8687 ensure correct behavior with overlapping index registers.
8688 ldrd with base writeback is undefined if the
8689 destination and index registers overlap. */
8691 gen_add_datah_offset(s
, insn
, address_offset
, addr
);
8692 store_reg(s
, rn
, addr
);
8695 tcg_gen_addi_i32(addr
, addr
, address_offset
);
8696 store_reg(s
, rn
, addr
);
8698 tcg_temp_free_i32(addr
);
8701 /* Complete the load. */
8702 store_reg(s
, rd
, tmp
);
8711 if (insn
& (1 << 4)) {
8713 /* Armv6 Media instructions. */
8715 rn
= (insn
>> 16) & 0xf;
8716 rd
= (insn
>> 12) & 0xf;
8717 rs
= (insn
>> 8) & 0xf;
8718 switch ((insn
>> 23) & 3) {
8719 case 0: /* Parallel add/subtract. */
8720 op1
= (insn
>> 20) & 7;
8721 tmp
= load_reg(s
, rn
);
8722 tmp2
= load_reg(s
, rm
);
8723 sh
= (insn
>> 5) & 7;
8724 if ((op1
& 3) == 0 || sh
== 5 || sh
== 6)
8726 gen_arm_parallel_addsub(op1
, sh
, tmp
, tmp2
);
8727 tcg_temp_free_i32(tmp2
);
8728 store_reg(s
, rd
, tmp
);
8731 if ((insn
& 0x00700020) == 0) {
8732 /* Halfword pack. */
8733 tmp
= load_reg(s
, rn
);
8734 tmp2
= load_reg(s
, rm
);
8735 shift
= (insn
>> 7) & 0x1f;
8736 if (insn
& (1 << 6)) {
8741 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
8742 tcg_gen_deposit_i32(tmp
, tmp
, tmp2
, 0, 16);
8745 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
8746 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, 0, 16);
8748 tcg_temp_free_i32(tmp2
);
8749 store_reg(s
, rd
, tmp
);
8750 } else if ((insn
& 0x00200020) == 0x00200000) {
8752 tmp
= load_reg(s
, rm
);
8753 shift
= (insn
>> 7) & 0x1f;
8754 if (insn
& (1 << 6)) {
8757 tcg_gen_sari_i32(tmp
, tmp
, shift
);
8759 tcg_gen_shli_i32(tmp
, tmp
, shift
);
8761 sh
= (insn
>> 16) & 0x1f;
8762 tmp2
= tcg_const_i32(sh
);
8763 if (insn
& (1 << 22))
8764 gen_helper_usat(tmp
, cpu_env
, tmp
, tmp2
);
8766 gen_helper_ssat(tmp
, cpu_env
, tmp
, tmp2
);
8767 tcg_temp_free_i32(tmp2
);
8768 store_reg(s
, rd
, tmp
);
8769 } else if ((insn
& 0x00300fe0) == 0x00200f20) {
8771 tmp
= load_reg(s
, rm
);
8772 sh
= (insn
>> 16) & 0x1f;
8773 tmp2
= tcg_const_i32(sh
);
8774 if (insn
& (1 << 22))
8775 gen_helper_usat16(tmp
, cpu_env
, tmp
, tmp2
);
8777 gen_helper_ssat16(tmp
, cpu_env
, tmp
, tmp2
);
8778 tcg_temp_free_i32(tmp2
);
8779 store_reg(s
, rd
, tmp
);
8780 } else if ((insn
& 0x00700fe0) == 0x00000fa0) {
8782 tmp
= load_reg(s
, rn
);
8783 tmp2
= load_reg(s
, rm
);
8784 tmp3
= tcg_temp_new_i32();
8785 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUARMState
, GE
));
8786 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
8787 tcg_temp_free_i32(tmp3
);
8788 tcg_temp_free_i32(tmp2
);
8789 store_reg(s
, rd
, tmp
);
8790 } else if ((insn
& 0x000003e0) == 0x00000060) {
8791 tmp
= load_reg(s
, rm
);
8792 shift
= (insn
>> 10) & 3;
8793 /* ??? In many cases it's not necessary to do a
8794 rotate, a shift is sufficient. */
8795 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
8796 op1
= (insn
>> 20) & 7;
8798 case 0: gen_sxtb16(tmp
); break;
8799 case 2: gen_sxtb(tmp
); break;
8800 case 3: gen_sxth(tmp
); break;
8801 case 4: gen_uxtb16(tmp
); break;
8802 case 6: gen_uxtb(tmp
); break;
8803 case 7: gen_uxth(tmp
); break;
8804 default: goto illegal_op
;
8807 tmp2
= load_reg(s
, rn
);
8808 if ((op1
& 3) == 0) {
8809 gen_add16(tmp
, tmp2
);
8811 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8812 tcg_temp_free_i32(tmp2
);
8815 store_reg(s
, rd
, tmp
);
8816 } else if ((insn
& 0x003f0f60) == 0x003f0f20) {
8818 tmp
= load_reg(s
, rm
);
8819 if (insn
& (1 << 22)) {
8820 if (insn
& (1 << 7)) {
8824 gen_helper_rbit(tmp
, tmp
);
8827 if (insn
& (1 << 7))
8830 tcg_gen_bswap32_i32(tmp
, tmp
);
8832 store_reg(s
, rd
, tmp
);
8837 case 2: /* Multiplies (Type 3). */
8838 switch ((insn
>> 20) & 0x7) {
8840 if (((insn
>> 6) ^ (insn
>> 7)) & 1) {
8841 /* op2 not 00x or 11x : UNDEF */
8844 /* Signed multiply most significant [accumulate].
8845 (SMMUL, SMMLA, SMMLS) */
8846 tmp
= load_reg(s
, rm
);
8847 tmp2
= load_reg(s
, rs
);
8848 tcg_gen_muls2_i32(tmp2
, tmp
, tmp
, tmp2
);
8851 tmp3
= load_reg(s
, rd
);
8852 if (insn
& (1 << 6)) {
8854 * For SMMLS, we need a 64-bit subtract.
8855 * Borrow caused by a non-zero multiplicand
8856 * lowpart, and the correct result lowpart
8859 TCGv_i32 zero
= tcg_const_i32(0);
8860 tcg_gen_sub2_i32(tmp2
, tmp
, zero
, tmp3
,
8862 tcg_temp_free_i32(zero
);
8864 tcg_gen_add_i32(tmp
, tmp
, tmp3
);
8866 tcg_temp_free_i32(tmp3
);
8868 if (insn
& (1 << 5)) {
8870 * Adding 0x80000000 to the 64-bit quantity
8871 * means that we have carry in to the high
8872 * word when the low word has the high bit set.
8874 tcg_gen_shri_i32(tmp2
, tmp2
, 31);
8875 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8877 tcg_temp_free_i32(tmp2
);
8878 store_reg(s
, rn
, tmp
);
8882 /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */
8883 if (insn
& (1 << 7)) {
8886 tmp
= load_reg(s
, rm
);
8887 tmp2
= load_reg(s
, rs
);
8888 if (insn
& (1 << 5))
8889 gen_swap_half(tmp2
);
8890 gen_smul_dual(tmp
, tmp2
);
8891 if (insn
& (1 << 22)) {
8892 /* smlald, smlsld */
8895 tmp64
= tcg_temp_new_i64();
8896 tmp64_2
= tcg_temp_new_i64();
8897 tcg_gen_ext_i32_i64(tmp64
, tmp
);
8898 tcg_gen_ext_i32_i64(tmp64_2
, tmp2
);
8899 tcg_temp_free_i32(tmp
);
8900 tcg_temp_free_i32(tmp2
);
8901 if (insn
& (1 << 6)) {
8902 tcg_gen_sub_i64(tmp64
, tmp64
, tmp64_2
);
8904 tcg_gen_add_i64(tmp64
, tmp64
, tmp64_2
);
8906 tcg_temp_free_i64(tmp64_2
);
8907 gen_addq(s
, tmp64
, rd
, rn
);
8908 gen_storeq_reg(s
, rd
, rn
, tmp64
);
8909 tcg_temp_free_i64(tmp64
);
8911 /* smuad, smusd, smlad, smlsd */
8912 if (insn
& (1 << 6)) {
8913 /* This subtraction cannot overflow. */
8914 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8916 /* This addition cannot overflow 32 bits;
8917 * however it may overflow considered as a
8918 * signed operation, in which case we must set
8921 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
8923 tcg_temp_free_i32(tmp2
);
8926 tmp2
= load_reg(s
, rd
);
8927 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
8928 tcg_temp_free_i32(tmp2
);
8930 store_reg(s
, rn
, tmp
);
8936 if (!dc_isar_feature(arm_div
, s
)) {
8939 if (((insn
>> 5) & 7) || (rd
!= 15)) {
8942 tmp
= load_reg(s
, rm
);
8943 tmp2
= load_reg(s
, rs
);
8944 if (insn
& (1 << 21)) {
8945 gen_helper_udiv(tmp
, tmp
, tmp2
);
8947 gen_helper_sdiv(tmp
, tmp
, tmp2
);
8949 tcg_temp_free_i32(tmp2
);
8950 store_reg(s
, rn
, tmp
);
8957 op1
= ((insn
>> 17) & 0x38) | ((insn
>> 5) & 7);
8959 case 0: /* Unsigned sum of absolute differences. */
8961 tmp
= load_reg(s
, rm
);
8962 tmp2
= load_reg(s
, rs
);
8963 gen_helper_usad8(tmp
, tmp
, tmp2
);
8964 tcg_temp_free_i32(tmp2
);
8966 tmp2
= load_reg(s
, rd
);
8967 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8968 tcg_temp_free_i32(tmp2
);
8970 store_reg(s
, rn
, tmp
);
8972 case 0x20: case 0x24: case 0x28: case 0x2c:
8973 /* Bitfield insert/clear. */
8975 shift
= (insn
>> 7) & 0x1f;
8976 i
= (insn
>> 16) & 0x1f;
8978 /* UNPREDICTABLE; we choose to UNDEF */
8983 tmp
= tcg_temp_new_i32();
8984 tcg_gen_movi_i32(tmp
, 0);
8986 tmp
= load_reg(s
, rm
);
8989 tmp2
= load_reg(s
, rd
);
8990 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, shift
, i
);
8991 tcg_temp_free_i32(tmp2
);
8993 store_reg(s
, rd
, tmp
);
8995 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
8996 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
8998 tmp
= load_reg(s
, rm
);
8999 shift
= (insn
>> 7) & 0x1f;
9000 i
= ((insn
>> 16) & 0x1f) + 1;
9005 tcg_gen_extract_i32(tmp
, tmp
, shift
, i
);
9007 tcg_gen_sextract_i32(tmp
, tmp
, shift
, i
);
9010 store_reg(s
, rd
, tmp
);
9020 /* Check for undefined extension instructions
9021 * per the ARM Bible IE:
9022 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
9024 sh
= (0xf << 20) | (0xf << 4);
9025 if (op1
== 0x7 && ((insn
& sh
) == sh
))
9029 /* load/store byte/word */
9030 rn
= (insn
>> 16) & 0xf;
9031 rd
= (insn
>> 12) & 0xf;
9032 tmp2
= load_reg(s
, rn
);
9033 if ((insn
& 0x01200000) == 0x00200000) {
9035 i
= get_a32_user_mem_index(s
);
9037 i
= get_mem_index(s
);
9039 if (insn
& (1 << 24))
9040 gen_add_data_offset(s
, insn
, tmp2
);
9041 if (insn
& (1 << 20)) {
9043 tmp
= tcg_temp_new_i32();
9044 if (insn
& (1 << 22)) {
9045 gen_aa32_ld8u_iss(s
, tmp
, tmp2
, i
, rd
);
9047 gen_aa32_ld32u_iss(s
, tmp
, tmp2
, i
, rd
);
9051 tmp
= load_reg(s
, rd
);
9052 if (insn
& (1 << 22)) {
9053 gen_aa32_st8_iss(s
, tmp
, tmp2
, i
, rd
);
9055 gen_aa32_st32_iss(s
, tmp
, tmp2
, i
, rd
);
9057 tcg_temp_free_i32(tmp
);
9059 if (!(insn
& (1 << 24))) {
9060 gen_add_data_offset(s
, insn
, tmp2
);
9061 store_reg(s
, rn
, tmp2
);
9062 } else if (insn
& (1 << 21)) {
9063 store_reg(s
, rn
, tmp2
);
9065 tcg_temp_free_i32(tmp2
);
9067 if (insn
& (1 << 20)) {
9068 /* Complete the load. */
9069 store_reg_from_load(s
, rd
, tmp
);
9075 int j
, n
, loaded_base
;
9076 bool exc_return
= false;
9077 bool is_load
= extract32(insn
, 20, 1);
9079 TCGv_i32 loaded_var
;
9080 /* load/store multiple words */
9081 /* XXX: store correct base if write back */
9082 if (insn
& (1 << 22)) {
9083 /* LDM (user), LDM (exception return) and STM (user) */
9085 goto illegal_op
; /* only usable in supervisor mode */
9087 if (is_load
&& extract32(insn
, 15, 1)) {
9093 rn
= (insn
>> 16) & 0xf;
9094 addr
= load_reg(s
, rn
);
9096 /* compute total size */
9100 for (i
= 0; i
< 16; i
++) {
9101 if (insn
& (1 << i
))
9104 /* XXX: test invalid n == 0 case ? */
9105 if (insn
& (1 << 23)) {
9106 if (insn
& (1 << 24)) {
9108 tcg_gen_addi_i32(addr
, addr
, 4);
9110 /* post increment */
9113 if (insn
& (1 << 24)) {
9115 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
9117 /* post decrement */
9119 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
9123 for (i
= 0; i
< 16; i
++) {
9124 if (insn
& (1 << i
)) {
9127 tmp
= tcg_temp_new_i32();
9128 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9130 tmp2
= tcg_const_i32(i
);
9131 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
9132 tcg_temp_free_i32(tmp2
);
9133 tcg_temp_free_i32(tmp
);
9134 } else if (i
== rn
) {
9137 } else if (i
== 15 && exc_return
) {
9138 store_pc_exc_ret(s
, tmp
);
9140 store_reg_from_load(s
, i
, tmp
);
9145 tmp
= tcg_temp_new_i32();
9146 tcg_gen_movi_i32(tmp
, read_pc(s
));
9148 tmp
= tcg_temp_new_i32();
9149 tmp2
= tcg_const_i32(i
);
9150 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
9151 tcg_temp_free_i32(tmp2
);
9153 tmp
= load_reg(s
, i
);
9155 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
9156 tcg_temp_free_i32(tmp
);
9159 /* no need to add after the last transfer */
9161 tcg_gen_addi_i32(addr
, addr
, 4);
9164 if (insn
& (1 << 21)) {
9166 if (insn
& (1 << 23)) {
9167 if (insn
& (1 << 24)) {
9170 /* post increment */
9171 tcg_gen_addi_i32(addr
, addr
, 4);
9174 if (insn
& (1 << 24)) {
9177 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
9179 /* post decrement */
9180 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
9183 store_reg(s
, rn
, addr
);
9185 tcg_temp_free_i32(addr
);
9188 store_reg(s
, rn
, loaded_var
);
9191 /* Restore CPSR from SPSR. */
9192 tmp
= load_cpu_field(spsr
);
9193 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
9196 gen_helper_cpsr_write_eret(cpu_env
, tmp
);
9197 tcg_temp_free_i32(tmp
);
9198 /* Must exit loop to check un-masked IRQs */
9199 s
->base
.is_jmp
= DISAS_EXIT
;
9208 /* branch (and link) */
9209 if (insn
& (1 << 24)) {
9210 tmp
= tcg_temp_new_i32();
9211 tcg_gen_movi_i32(tmp
, s
->base
.pc_next
);
9212 store_reg(s
, 14, tmp
);
9214 offset
= sextract32(insn
<< 2, 0, 26);
9215 gen_jmp(s
, read_pc(s
) + offset
);
9221 if (((insn
>> 8) & 0xe) == 10) {
9223 if (disas_vfp_insn(s
, insn
)) {
9226 } else if (disas_coproc_insn(s
, insn
)) {
9233 gen_set_pc_im(s
, s
->base
.pc_next
);
9234 s
->svc_imm
= extract32(insn
, 0, 24);
9235 s
->base
.is_jmp
= DISAS_SWI
;
9239 unallocated_encoding(s
);
9245 static bool thumb_insn_is_16bit(DisasContext
*s
, uint32_t pc
, uint32_t insn
)
9248 * Return true if this is a 16 bit instruction. We must be precise
9249 * about this (matching the decode).
9251 if ((insn
>> 11) < 0x1d) {
9252 /* Definitely a 16-bit instruction */
9256 /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
9257 * first half of a 32-bit Thumb insn. Thumb-1 cores might
9258 * end up actually treating this as two 16-bit insns, though,
9259 * if it's half of a bl/blx pair that might span a page boundary.
9261 if (arm_dc_feature(s
, ARM_FEATURE_THUMB2
) ||
9262 arm_dc_feature(s
, ARM_FEATURE_M
)) {
9263 /* Thumb2 cores (including all M profile ones) always treat
9264 * 32-bit insns as 32-bit.
9269 if ((insn
>> 11) == 0x1e && pc
- s
->page_start
< TARGET_PAGE_SIZE
- 3) {
9270 /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
9271 * is not on the next page; we merge this into a 32-bit
9276 /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF);
9277 * 0b1111_1xxx_xxxx_xxxx : BL suffix;
9278 * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page
9279 * -- handle as single 16 bit insn
9284 /* Return true if this is a Thumb-2 logical op. */
9286 thumb2_logic_op(int op
)
9291 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
9292 then set condition code flags based on the result of the operation.
9293 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
9294 to the high bit of T1.
9295 Returns zero if the opcode is valid. */
9298 gen_thumb2_data_op(DisasContext
*s
, int op
, int conds
, uint32_t shifter_out
,
9299 TCGv_i32 t0
, TCGv_i32 t1
)
9306 tcg_gen_and_i32(t0
, t0
, t1
);
9310 tcg_gen_andc_i32(t0
, t0
, t1
);
9314 tcg_gen_or_i32(t0
, t0
, t1
);
9318 tcg_gen_orc_i32(t0
, t0
, t1
);
9322 tcg_gen_xor_i32(t0
, t0
, t1
);
9327 gen_add_CC(t0
, t0
, t1
);
9329 tcg_gen_add_i32(t0
, t0
, t1
);
9333 gen_adc_CC(t0
, t0
, t1
);
9339 gen_sbc_CC(t0
, t0
, t1
);
9341 gen_sub_carry(t0
, t0
, t1
);
9346 gen_sub_CC(t0
, t0
, t1
);
9348 tcg_gen_sub_i32(t0
, t0
, t1
);
9352 gen_sub_CC(t0
, t1
, t0
);
9354 tcg_gen_sub_i32(t0
, t1
, t0
);
9356 default: /* 5, 6, 7, 9, 12, 15. */
9362 gen_set_CF_bit31(t1
);
9367 /* Translate a 32-bit thumb instruction. */
9368 static void disas_thumb2_insn(DisasContext
*s
, uint32_t insn
)
9370 uint32_t imm
, shift
, offset
;
9371 uint32_t rd
, rn
, rm
, rs
;
9383 * ARMv6-M supports a limited subset of Thumb2 instructions.
9384 * Other Thumb1 architectures allow only 32-bit
9385 * combined BL/BLX prefix and suffix.
9387 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
9388 !arm_dc_feature(s
, ARM_FEATURE_V7
)) {
9391 static const uint32_t armv6m_insn
[] = {0xf3808000 /* msr */,
9392 0xf3b08040 /* dsb */,
9393 0xf3b08050 /* dmb */,
9394 0xf3b08060 /* isb */,
9395 0xf3e08000 /* mrs */,
9396 0xf000d000 /* bl */};
9397 static const uint32_t armv6m_mask
[] = {0xffe0d000,
9404 for (i
= 0; i
< ARRAY_SIZE(armv6m_insn
); i
++) {
9405 if ((insn
& armv6m_mask
[i
]) == armv6m_insn
[i
]) {
9413 } else if ((insn
& 0xf800e800) != 0xf000e800) {
9417 rn
= (insn
>> 16) & 0xf;
9418 rs
= (insn
>> 12) & 0xf;
9419 rd
= (insn
>> 8) & 0xf;
9421 switch ((insn
>> 25) & 0xf) {
9422 case 0: case 1: case 2: case 3:
9423 /* 16-bit instructions. Should never happen. */
9426 if (insn
& (1 << 22)) {
9427 /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx
9428 * - load/store doubleword, load/store exclusive, ldacq/strel,
9431 if (insn
== 0xe97fe97f && arm_dc_feature(s
, ARM_FEATURE_M
) &&
9432 arm_dc_feature(s
, ARM_FEATURE_V8
)) {
9433 /* 0b1110_1001_0111_1111_1110_1001_0111_111
9435 * The bulk of the behaviour for this instruction is implemented
9436 * in v7m_handle_execute_nsc(), which deals with the insn when
9437 * it is executed by a CPU in non-secure state from memory
9438 * which is Secure & NonSecure-Callable.
9439 * Here we only need to handle the remaining cases:
9440 * * in NS memory (including the "security extension not
9441 * implemented" case) : NOP
9442 * * in S memory but CPU already secure (clear IT bits)
9443 * We know that the attribute for the memory this insn is
9444 * in must match the current CPU state, because otherwise
9445 * get_phys_addr_pmsav8 would have generated an exception.
9447 if (s
->v8m_secure
) {
9448 /* Like the IT insn, we don't need to generate any code */
9449 s
->condexec_cond
= 0;
9450 s
->condexec_mask
= 0;
9452 } else if (insn
& 0x01200000) {
9453 /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
9454 * - load/store dual (post-indexed)
9455 * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx
9456 * - load/store dual (literal and immediate)
9457 * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
9458 * - load/store dual (pre-indexed)
9460 bool wback
= extract32(insn
, 21, 1);
9462 if (rn
== 15 && (insn
& (1 << 21))) {
9467 addr
= add_reg_for_lit(s
, rn
, 0);
9468 offset
= (insn
& 0xff) * 4;
9469 if ((insn
& (1 << 23)) == 0) {
9473 if (s
->v8m_stackcheck
&& rn
== 13 && wback
) {
9475 * Here 'addr' is the current SP; if offset is +ve we're
9476 * moving SP up, else down. It is UNKNOWN whether the limit
9477 * check triggers when SP starts below the limit and ends
9478 * up above it; check whichever of the current and final
9479 * SP is lower, so QEMU will trigger in that situation.
9481 if ((int32_t)offset
< 0) {
9482 TCGv_i32 newsp
= tcg_temp_new_i32();
9484 tcg_gen_addi_i32(newsp
, addr
, offset
);
9485 gen_helper_v8m_stackcheck(cpu_env
, newsp
);
9486 tcg_temp_free_i32(newsp
);
9488 gen_helper_v8m_stackcheck(cpu_env
, addr
);
9492 if (insn
& (1 << 24)) {
9493 tcg_gen_addi_i32(addr
, addr
, offset
);
9496 if (insn
& (1 << 20)) {
9498 tmp
= tcg_temp_new_i32();
9499 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9500 store_reg(s
, rs
, tmp
);
9501 tcg_gen_addi_i32(addr
, addr
, 4);
9502 tmp
= tcg_temp_new_i32();
9503 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9504 store_reg(s
, rd
, tmp
);
9507 tmp
= load_reg(s
, rs
);
9508 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
9509 tcg_temp_free_i32(tmp
);
9510 tcg_gen_addi_i32(addr
, addr
, 4);
9511 tmp
= load_reg(s
, rd
);
9512 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
9513 tcg_temp_free_i32(tmp
);
9516 /* Base writeback. */
9517 tcg_gen_addi_i32(addr
, addr
, offset
- 4);
9518 store_reg(s
, rn
, addr
);
9520 tcg_temp_free_i32(addr
);
9522 } else if ((insn
& (1 << 23)) == 0) {
9523 /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx
9524 * - load/store exclusive word
9528 if (!(insn
& (1 << 20)) &&
9529 arm_dc_feature(s
, ARM_FEATURE_M
) &&
9530 arm_dc_feature(s
, ARM_FEATURE_V8
)) {
9531 /* 0b1110_1000_0100_xxxx_1111_xxxx_xxxx_xxxx
9534 bool alt
= insn
& (1 << 7);
9535 TCGv_i32 addr
, op
, ttresp
;
9537 if ((insn
& 0x3f) || rd
== 13 || rd
== 15 || rn
== 15) {
9538 /* we UNDEF for these UNPREDICTABLE cases */
9542 if (alt
&& !s
->v8m_secure
) {
9546 addr
= load_reg(s
, rn
);
9547 op
= tcg_const_i32(extract32(insn
, 6, 2));
9548 ttresp
= tcg_temp_new_i32();
9549 gen_helper_v7m_tt(ttresp
, cpu_env
, addr
, op
);
9550 tcg_temp_free_i32(addr
);
9551 tcg_temp_free_i32(op
);
9552 store_reg(s
, rd
, ttresp
);
9557 addr
= tcg_temp_local_new_i32();
9558 load_reg_var(s
, addr
, rn
);
9559 tcg_gen_addi_i32(addr
, addr
, (insn
& 0xff) << 2);
9560 if (insn
& (1 << 20)) {
9561 gen_load_exclusive(s
, rs
, 15, addr
, 2);
9563 gen_store_exclusive(s
, rd
, rs
, 15, addr
, 2);
9565 tcg_temp_free_i32(addr
);
9566 } else if ((insn
& (7 << 5)) == 0) {
9568 addr
= load_reg(s
, rn
);
9569 tmp
= load_reg(s
, rm
);
9570 tcg_gen_add_i32(addr
, addr
, tmp
);
9571 if (insn
& (1 << 4)) {
9573 tcg_gen_add_i32(addr
, addr
, tmp
);
9574 tcg_temp_free_i32(tmp
);
9575 tmp
= tcg_temp_new_i32();
9576 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
9578 tcg_temp_free_i32(tmp
);
9579 tmp
= tcg_temp_new_i32();
9580 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
9582 tcg_temp_free_i32(addr
);
9583 tcg_gen_shli_i32(tmp
, tmp
, 1);
9584 tcg_gen_addi_i32(tmp
, tmp
, read_pc(s
));
9585 store_reg(s
, 15, tmp
);
9587 bool is_lasr
= false;
9588 bool is_ld
= extract32(insn
, 20, 1);
9589 int op2
= (insn
>> 6) & 0x3;
9590 op
= (insn
>> 4) & 0x3;
9595 /* Load/store exclusive byte/halfword/doubleword */
9602 /* Load-acquire/store-release */
9608 /* Load-acquire/store-release exclusive */
9614 if (is_lasr
&& !is_ld
) {
9615 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
9618 addr
= tcg_temp_local_new_i32();
9619 load_reg_var(s
, addr
, rn
);
9622 tmp
= tcg_temp_new_i32();
9625 gen_aa32_ld8u_iss(s
, tmp
, addr
, get_mem_index(s
),
9629 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
),
9633 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
),
9639 store_reg(s
, rs
, tmp
);
9641 tmp
= load_reg(s
, rs
);
9644 gen_aa32_st8_iss(s
, tmp
, addr
, get_mem_index(s
),
9648 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
),
9652 gen_aa32_st32_iss(s
, tmp
, addr
, get_mem_index(s
),
9658 tcg_temp_free_i32(tmp
);
9661 gen_load_exclusive(s
, rs
, rd
, addr
, op
);
9663 gen_store_exclusive(s
, rm
, rs
, rd
, addr
, op
);
9665 tcg_temp_free_i32(addr
);
9667 if (is_lasr
&& is_ld
) {
9668 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
9672 /* Load/store multiple, RFE, SRS. */
9673 if (((insn
>> 23) & 1) == ((insn
>> 24) & 1)) {
9674 /* RFE, SRS: not available in user mode or on M profile */
9675 if (IS_USER(s
) || arm_dc_feature(s
, ARM_FEATURE_M
)) {
9678 if (insn
& (1 << 20)) {
9680 addr
= load_reg(s
, rn
);
9681 if ((insn
& (1 << 24)) == 0)
9682 tcg_gen_addi_i32(addr
, addr
, -8);
9683 /* Load PC into tmp and CPSR into tmp2. */
9684 tmp
= tcg_temp_new_i32();
9685 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9686 tcg_gen_addi_i32(addr
, addr
, 4);
9687 tmp2
= tcg_temp_new_i32();
9688 gen_aa32_ld32u(s
, tmp2
, addr
, get_mem_index(s
));
9689 if (insn
& (1 << 21)) {
9690 /* Base writeback. */
9691 if (insn
& (1 << 24)) {
9692 tcg_gen_addi_i32(addr
, addr
, 4);
9694 tcg_gen_addi_i32(addr
, addr
, -4);
9696 store_reg(s
, rn
, addr
);
9698 tcg_temp_free_i32(addr
);
9700 gen_rfe(s
, tmp
, tmp2
);
9703 gen_srs(s
, (insn
& 0x1f), (insn
& (1 << 24)) ? 1 : 2,
9707 int i
, loaded_base
= 0;
9708 TCGv_i32 loaded_var
;
9709 bool wback
= extract32(insn
, 21, 1);
9710 /* Load/store multiple. */
9711 addr
= load_reg(s
, rn
);
9713 for (i
= 0; i
< 16; i
++) {
9714 if (insn
& (1 << i
))
9718 if (insn
& (1 << 24)) {
9719 tcg_gen_addi_i32(addr
, addr
, -offset
);
9722 if (s
->v8m_stackcheck
&& rn
== 13 && wback
) {
9724 * If the writeback is incrementing SP rather than
9725 * decrementing it, and the initial SP is below the
9726 * stack limit but the final written-back SP would
9727 * be above, then then we must not perform any memory
9728 * accesses, but it is IMPDEF whether we generate
9729 * an exception. We choose to do so in this case.
9730 * At this point 'addr' is the lowest address, so
9731 * either the original SP (if incrementing) or our
9732 * final SP (if decrementing), so that's what we check.
9734 gen_helper_v8m_stackcheck(cpu_env
, addr
);
9738 for (i
= 0; i
< 16; i
++) {
9739 if ((insn
& (1 << i
)) == 0)
9741 if (insn
& (1 << 20)) {
9743 tmp
= tcg_temp_new_i32();
9744 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9746 gen_bx_excret(s
, tmp
);
9747 } else if (i
== rn
) {
9751 store_reg(s
, i
, tmp
);
9755 tmp
= load_reg(s
, i
);
9756 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
9757 tcg_temp_free_i32(tmp
);
9759 tcg_gen_addi_i32(addr
, addr
, 4);
9762 store_reg(s
, rn
, loaded_var
);
9765 /* Base register writeback. */
9766 if (insn
& (1 << 24)) {
9767 tcg_gen_addi_i32(addr
, addr
, -offset
);
9769 /* Fault if writeback register is in register list. */
9770 if (insn
& (1 << rn
))
9772 store_reg(s
, rn
, addr
);
9774 tcg_temp_free_i32(addr
);
9781 op
= (insn
>> 21) & 0xf;
9783 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9786 /* Halfword pack. */
9787 tmp
= load_reg(s
, rn
);
9788 tmp2
= load_reg(s
, rm
);
9789 shift
= ((insn
>> 10) & 0x1c) | ((insn
>> 6) & 0x3);
9790 if (insn
& (1 << 5)) {
9795 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
9796 tcg_gen_deposit_i32(tmp
, tmp
, tmp2
, 0, 16);
9799 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
9800 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, 0, 16);
9802 tcg_temp_free_i32(tmp2
);
9803 store_reg(s
, rd
, tmp
);
9805 /* Data processing register constant shift. */
9807 tmp
= tcg_temp_new_i32();
9808 tcg_gen_movi_i32(tmp
, 0);
9810 tmp
= load_reg(s
, rn
);
9812 tmp2
= load_reg(s
, rm
);
9814 shiftop
= (insn
>> 4) & 3;
9815 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
9816 conds
= (insn
& (1 << 20)) != 0;
9817 logic_cc
= (conds
&& thumb2_logic_op(op
));
9818 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
9819 if (gen_thumb2_data_op(s
, op
, conds
, 0, tmp
, tmp2
))
9821 tcg_temp_free_i32(tmp2
);
9823 ((op
== 2 && rn
== 15) ||
9824 (op
== 8 && rn
== 13) ||
9825 (op
== 13 && rn
== 13))) {
9826 /* MOV SP, ... or ADD SP, SP, ... or SUB SP, SP, ... */
9827 store_sp_checked(s
, tmp
);
9828 } else if (rd
!= 15) {
9829 store_reg(s
, rd
, tmp
);
9831 tcg_temp_free_i32(tmp
);
9835 case 13: /* Misc data processing. */
9836 op
= ((insn
>> 22) & 6) | ((insn
>> 7) & 1);
9837 if (op
< 4 && (insn
& 0xf000) != 0xf000)
9840 case 0: /* Register controlled shift. */
9841 tmp
= load_reg(s
, rn
);
9842 tmp2
= load_reg(s
, rm
);
9843 if ((insn
& 0x70) != 0)
9846 * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx:
9847 * - MOV, MOVS (register-shifted register), flagsetting
9849 op
= (insn
>> 21) & 3;
9850 logic_cc
= (insn
& (1 << 20)) != 0;
9851 gen_arm_shift_reg(tmp
, op
, tmp2
, logic_cc
);
9854 store_reg(s
, rd
, tmp
);
9856 case 1: /* Sign/zero extend. */
9857 op
= (insn
>> 20) & 7;
9859 case 0: /* SXTAH, SXTH */
9860 case 1: /* UXTAH, UXTH */
9861 case 4: /* SXTAB, SXTB */
9862 case 5: /* UXTAB, UXTB */
9864 case 2: /* SXTAB16, SXTB16 */
9865 case 3: /* UXTAB16, UXTB16 */
9866 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9874 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9878 tmp
= load_reg(s
, rm
);
9879 shift
= (insn
>> 4) & 3;
9880 /* ??? In many cases it's not necessary to do a
9881 rotate, a shift is sufficient. */
9882 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
9883 op
= (insn
>> 20) & 7;
9885 case 0: gen_sxth(tmp
); break;
9886 case 1: gen_uxth(tmp
); break;
9887 case 2: gen_sxtb16(tmp
); break;
9888 case 3: gen_uxtb16(tmp
); break;
9889 case 4: gen_sxtb(tmp
); break;
9890 case 5: gen_uxtb(tmp
); break;
9892 g_assert_not_reached();
9895 tmp2
= load_reg(s
, rn
);
9896 if ((op
>> 1) == 1) {
9897 gen_add16(tmp
, tmp2
);
9899 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9900 tcg_temp_free_i32(tmp2
);
9903 store_reg(s
, rd
, tmp
);
9905 case 2: /* SIMD add/subtract. */
9906 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9909 op
= (insn
>> 20) & 7;
9910 shift
= (insn
>> 4) & 7;
9911 if ((op
& 3) == 3 || (shift
& 3) == 3)
9913 tmp
= load_reg(s
, rn
);
9914 tmp2
= load_reg(s
, rm
);
9915 gen_thumb2_parallel_addsub(op
, shift
, tmp
, tmp2
);
9916 tcg_temp_free_i32(tmp2
);
9917 store_reg(s
, rd
, tmp
);
9919 case 3: /* Other data processing. */
9920 op
= ((insn
>> 17) & 0x38) | ((insn
>> 4) & 7);
9922 /* Saturating add/subtract. */
9923 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9926 tmp
= load_reg(s
, rn
);
9927 tmp2
= load_reg(s
, rm
);
9929 gen_helper_add_saturate(tmp
, cpu_env
, tmp
, tmp
);
9931 gen_helper_sub_saturate(tmp
, cpu_env
, tmp2
, tmp
);
9933 gen_helper_add_saturate(tmp
, cpu_env
, tmp
, tmp2
);
9934 tcg_temp_free_i32(tmp2
);
9937 case 0x0a: /* rbit */
9938 case 0x08: /* rev */
9939 case 0x09: /* rev16 */
9940 case 0x0b: /* revsh */
9941 case 0x18: /* clz */
9943 case 0x10: /* sel */
9944 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9948 case 0x20: /* crc32/crc32c */
9954 if (!dc_isar_feature(aa32_crc32
, s
)) {
9961 tmp
= load_reg(s
, rn
);
9963 case 0x0a: /* rbit */
9964 gen_helper_rbit(tmp
, tmp
);
9966 case 0x08: /* rev */
9967 tcg_gen_bswap32_i32(tmp
, tmp
);
9969 case 0x09: /* rev16 */
9972 case 0x0b: /* revsh */
9975 case 0x10: /* sel */
9976 tmp2
= load_reg(s
, rm
);
9977 tmp3
= tcg_temp_new_i32();
9978 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUARMState
, GE
));
9979 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
9980 tcg_temp_free_i32(tmp3
);
9981 tcg_temp_free_i32(tmp2
);
9983 case 0x18: /* clz */
9984 tcg_gen_clzi_i32(tmp
, tmp
, 32);
9994 uint32_t sz
= op
& 0x3;
9995 uint32_t c
= op
& 0x8;
9997 tmp2
= load_reg(s
, rm
);
9999 tcg_gen_andi_i32(tmp2
, tmp2
, 0xff);
10000 } else if (sz
== 1) {
10001 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff);
10003 tmp3
= tcg_const_i32(1 << sz
);
10005 gen_helper_crc32c(tmp
, tmp
, tmp2
, tmp3
);
10007 gen_helper_crc32(tmp
, tmp
, tmp2
, tmp3
);
10009 tcg_temp_free_i32(tmp2
);
10010 tcg_temp_free_i32(tmp3
);
10014 g_assert_not_reached();
10017 store_reg(s
, rd
, tmp
);
10019 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
10020 switch ((insn
>> 20) & 7) {
10021 case 0: /* 32 x 32 -> 32 */
10022 case 7: /* Unsigned sum of absolute differences. */
10024 case 1: /* 16 x 16 -> 32 */
10025 case 2: /* Dual multiply add. */
10026 case 3: /* 32 * 16 -> 32msb */
10027 case 4: /* Dual multiply subtract. */
10028 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
10029 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10034 op
= (insn
>> 4) & 0xf;
10035 tmp
= load_reg(s
, rn
);
10036 tmp2
= load_reg(s
, rm
);
10037 switch ((insn
>> 20) & 7) {
10038 case 0: /* 32 x 32 -> 32 */
10039 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
10040 tcg_temp_free_i32(tmp2
);
10042 tmp2
= load_reg(s
, rs
);
10044 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
10046 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10047 tcg_temp_free_i32(tmp2
);
10050 case 1: /* 16 x 16 -> 32 */
10051 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
10052 tcg_temp_free_i32(tmp2
);
10054 tmp2
= load_reg(s
, rs
);
10055 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
10056 tcg_temp_free_i32(tmp2
);
10059 case 2: /* Dual multiply add. */
10060 case 4: /* Dual multiply subtract. */
10062 gen_swap_half(tmp2
);
10063 gen_smul_dual(tmp
, tmp2
);
10064 if (insn
& (1 << 22)) {
10065 /* This subtraction cannot overflow. */
10066 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
10068 /* This addition cannot overflow 32 bits;
10069 * however it may overflow considered as a signed
10070 * operation, in which case we must set the Q flag.
10072 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
10074 tcg_temp_free_i32(tmp2
);
10077 tmp2
= load_reg(s
, rs
);
10078 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
10079 tcg_temp_free_i32(tmp2
);
10082 case 3: /* 32 * 16 -> 32msb */
10084 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
10087 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
10088 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
10089 tmp
= tcg_temp_new_i32();
10090 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
10091 tcg_temp_free_i64(tmp64
);
10094 tmp2
= load_reg(s
, rs
);
10095 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
10096 tcg_temp_free_i32(tmp2
);
10099 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
10100 tcg_gen_muls2_i32(tmp2
, tmp
, tmp
, tmp2
);
10102 tmp3
= load_reg(s
, rs
);
10103 if (insn
& (1 << 20)) {
10104 tcg_gen_add_i32(tmp
, tmp
, tmp3
);
10107 * For SMMLS, we need a 64-bit subtract.
10108 * Borrow caused by a non-zero multiplicand lowpart,
10109 * and the correct result lowpart for rounding.
10111 TCGv_i32 zero
= tcg_const_i32(0);
10112 tcg_gen_sub2_i32(tmp2
, tmp
, zero
, tmp3
, tmp2
, tmp
);
10113 tcg_temp_free_i32(zero
);
10115 tcg_temp_free_i32(tmp3
);
10117 if (insn
& (1 << 4)) {
10119 * Adding 0x80000000 to the 64-bit quantity
10120 * means that we have carry in to the high
10121 * word when the low word has the high bit set.
10123 tcg_gen_shri_i32(tmp2
, tmp2
, 31);
10124 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10126 tcg_temp_free_i32(tmp2
);
10128 case 7: /* Unsigned sum of absolute differences. */
10129 gen_helper_usad8(tmp
, tmp
, tmp2
);
10130 tcg_temp_free_i32(tmp2
);
10132 tmp2
= load_reg(s
, rs
);
10133 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10134 tcg_temp_free_i32(tmp2
);
10138 store_reg(s
, rd
, tmp
);
10140 case 6: case 7: /* 64-bit multiply, Divide. */
10141 op
= ((insn
>> 4) & 0xf) | ((insn
>> 16) & 0x70);
10142 tmp
= load_reg(s
, rn
);
10143 tmp2
= load_reg(s
, rm
);
10144 if ((op
& 0x50) == 0x10) {
10146 if (!dc_isar_feature(thumb_div
, s
)) {
10150 gen_helper_udiv(tmp
, tmp
, tmp2
);
10152 gen_helper_sdiv(tmp
, tmp
, tmp2
);
10153 tcg_temp_free_i32(tmp2
);
10154 store_reg(s
, rd
, tmp
);
10155 } else if ((op
& 0xe) == 0xc) {
10156 /* Dual multiply accumulate long. */
10157 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10158 tcg_temp_free_i32(tmp
);
10159 tcg_temp_free_i32(tmp2
);
10163 gen_swap_half(tmp2
);
10164 gen_smul_dual(tmp
, tmp2
);
10166 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
10168 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10170 tcg_temp_free_i32(tmp2
);
10172 tmp64
= tcg_temp_new_i64();
10173 tcg_gen_ext_i32_i64(tmp64
, tmp
);
10174 tcg_temp_free_i32(tmp
);
10175 gen_addq(s
, tmp64
, rs
, rd
);
10176 gen_storeq_reg(s
, rs
, rd
, tmp64
);
10177 tcg_temp_free_i64(tmp64
);
10180 /* Unsigned 64-bit multiply */
10181 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
10185 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10186 tcg_temp_free_i32(tmp2
);
10187 tcg_temp_free_i32(tmp
);
10190 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
10191 tcg_temp_free_i32(tmp2
);
10192 tmp64
= tcg_temp_new_i64();
10193 tcg_gen_ext_i32_i64(tmp64
, tmp
);
10194 tcg_temp_free_i32(tmp
);
10196 /* Signed 64-bit multiply */
10197 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
10202 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10203 tcg_temp_free_i64(tmp64
);
10206 gen_addq_lo(s
, tmp64
, rs
);
10207 gen_addq_lo(s
, tmp64
, rd
);
10208 } else if (op
& 0x40) {
10209 /* 64-bit accumulate. */
10210 gen_addq(s
, tmp64
, rs
, rd
);
10212 gen_storeq_reg(s
, rs
, rd
, tmp64
);
10213 tcg_temp_free_i64(tmp64
);
10218 case 6: case 7: case 14: case 15:
10220 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10221 /* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */
10222 if (extract32(insn
, 24, 2) == 3) {
10223 goto illegal_op
; /* op0 = 0b11 : unallocated */
10227 * Decode VLLDM and VLSTM first: these are nonstandard because:
10228 * * if there is no FPU then these insns must NOP in
10229 * Secure state and UNDEF in Nonsecure state
10230 * * if there is an FPU then these insns do not have
10231 * the usual behaviour that disas_vfp_insn() provides of
10232 * being controlled by CPACR/NSACR enable bits or the
10233 * lazy-stacking logic.
10235 if (arm_dc_feature(s
, ARM_FEATURE_V8
) &&
10236 (insn
& 0xffa00f00) == 0xec200a00) {
10237 /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx
10239 * We choose to UNDEF if the RAZ bits are non-zero.
10241 if (!s
->v8m_secure
|| (insn
& 0x0040f0ff)) {
10245 if (arm_dc_feature(s
, ARM_FEATURE_VFP
)) {
10246 TCGv_i32 fptr
= load_reg(s
, rn
);
10248 if (extract32(insn
, 20, 1)) {
10249 gen_helper_v7m_vlldm(cpu_env
, fptr
);
10251 gen_helper_v7m_vlstm(cpu_env
, fptr
);
10253 tcg_temp_free_i32(fptr
);
10255 /* End the TB, because we have updated FP control bits */
10256 s
->base
.is_jmp
= DISAS_UPDATE
;
10260 if (arm_dc_feature(s
, ARM_FEATURE_VFP
) &&
10261 ((insn
>> 8) & 0xe) == 10) {
10262 /* FP, and the CPU supports it */
10263 if (disas_vfp_insn(s
, insn
)) {
10269 /* All other insns: NOCP */
10270 gen_exception_insn(s
, s
->pc_curr
, EXCP_NOCP
, syn_uncategorized(),
10271 default_exception_el(s
));
10274 if ((insn
& 0xfe000a00) == 0xfc000800
10275 && arm_dc_feature(s
, ARM_FEATURE_V8
)) {
10276 /* The Thumb2 and ARM encodings are identical. */
10277 if (disas_neon_insn_3same_ext(s
, insn
)) {
10280 } else if ((insn
& 0xff000a00) == 0xfe000800
10281 && arm_dc_feature(s
, ARM_FEATURE_V8
)) {
10282 /* The Thumb2 and ARM encodings are identical. */
10283 if (disas_neon_insn_2reg_scalar_ext(s
, insn
)) {
10286 } else if (((insn
>> 24) & 3) == 3) {
10287 /* Translate into the equivalent ARM encoding. */
10288 insn
= (insn
& 0xe2ffffff) | ((insn
& (1 << 28)) >> 4) | (1 << 28);
10289 if (disas_neon_data_insn(s
, insn
)) {
10292 } else if (((insn
>> 8) & 0xe) == 10) {
10293 if (disas_vfp_insn(s
, insn
)) {
10297 if (insn
& (1 << 28))
10299 if (disas_coproc_insn(s
, insn
)) {
10304 case 8: case 9: case 10: case 11:
10305 if (insn
& (1 << 15)) {
10306 /* Branches, misc control. */
10307 if (insn
& 0x5000) {
10308 /* Unconditional branch. */
10309 /* signextend(hw1[10:0]) -> offset[:12]. */
10310 offset
= ((int32_t)insn
<< 5) >> 9 & ~(int32_t)0xfff;
10311 /* hw1[10:0] -> offset[11:1]. */
10312 offset
|= (insn
& 0x7ff) << 1;
10313 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
10314 offset[24:22] already have the same value because of the
10315 sign extension above. */
10316 offset
^= ((~insn
) & (1 << 13)) << 10;
10317 offset
^= ((~insn
) & (1 << 11)) << 11;
10319 if (insn
& (1 << 14)) {
10320 /* Branch and link. */
10321 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| 1);
10324 offset
+= read_pc(s
);
10325 if (insn
& (1 << 12)) {
10327 gen_jmp(s
, offset
);
10330 offset
&= ~(uint32_t)2;
10331 /* thumb2 bx, no need to check */
10332 gen_bx_im(s
, offset
);
10334 } else if (((insn
>> 23) & 7) == 7) {
10336 if (insn
& (1 << 13))
10339 if (insn
& (1 << 26)) {
10340 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10343 if (!(insn
& (1 << 20))) {
10344 /* Hypervisor call (v7) */
10345 int imm16
= extract32(insn
, 16, 4) << 12
10346 | extract32(insn
, 0, 12);
10353 /* Secure monitor call (v6+) */
10361 op
= (insn
>> 20) & 7;
10363 case 0: /* msr cpsr. */
10364 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10365 tmp
= load_reg(s
, rn
);
10366 /* the constant is the mask and SYSm fields */
10367 addr
= tcg_const_i32(insn
& 0xfff);
10368 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
10369 tcg_temp_free_i32(addr
);
10370 tcg_temp_free_i32(tmp
);
10375 case 1: /* msr spsr. */
10376 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10380 if (extract32(insn
, 5, 1)) {
10382 int sysm
= extract32(insn
, 8, 4) |
10383 (extract32(insn
, 4, 1) << 4);
10386 gen_msr_banked(s
, r
, sysm
, rm
);
10390 /* MSR (for PSRs) */
10391 tmp
= load_reg(s
, rn
);
10393 msr_mask(s
, (insn
>> 8) & 0xf, op
== 1),
10397 case 2: /* cps, nop-hint. */
10398 if (((insn
>> 8) & 7) == 0) {
10399 gen_nop_hint(s
, insn
& 0xff);
10401 /* Implemented as NOP in user mode. */
10406 if (insn
& (1 << 10)) {
10407 if (insn
& (1 << 7))
10409 if (insn
& (1 << 6))
10411 if (insn
& (1 << 5))
10413 if (insn
& (1 << 9))
10414 imm
= CPSR_A
| CPSR_I
| CPSR_F
;
10416 if (insn
& (1 << 8)) {
10418 imm
|= (insn
& 0x1f);
10421 gen_set_psr_im(s
, offset
, 0, imm
);
10424 case 3: /* Special control operations. */
10425 if (!arm_dc_feature(s
, ARM_FEATURE_V7
) &&
10426 !arm_dc_feature(s
, ARM_FEATURE_M
)) {
10429 op
= (insn
>> 4) & 0xf;
10431 case 2: /* clrex */
10436 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
10439 /* We need to break the TB after this insn
10440 * to execute self-modifying code correctly
10441 * and also to take any pending interrupts
10444 gen_goto_tb(s
, 0, s
->base
.pc_next
);
10447 if ((insn
& 0xf) || !dc_isar_feature(aa32_sb
, s
)) {
10451 * TODO: There is no speculation barrier opcode
10452 * for TCG; MB and end the TB instead.
10454 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
10455 gen_goto_tb(s
, 0, s
->base
.pc_next
);
10462 /* Trivial implementation equivalent to bx.
10463 * This instruction doesn't exist at all for M-profile.
10465 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10468 tmp
= load_reg(s
, rn
);
10471 case 5: /* Exception return. */
10475 if (rn
!= 14 || rd
!= 15) {
10478 if (s
->current_el
== 2) {
10479 /* ERET from Hyp uses ELR_Hyp, not LR */
10483 tmp
= load_cpu_field(elr_el
[2]);
10485 tmp
= load_reg(s
, rn
);
10486 tcg_gen_subi_i32(tmp
, tmp
, insn
& 0xff);
10488 gen_exception_return(s
, tmp
);
10491 if (extract32(insn
, 5, 1) &&
10492 !arm_dc_feature(s
, ARM_FEATURE_M
)) {
10494 int sysm
= extract32(insn
, 16, 4) |
10495 (extract32(insn
, 4, 1) << 4);
10497 gen_mrs_banked(s
, 0, sysm
, rd
);
10501 if (extract32(insn
, 16, 4) != 0xf) {
10504 if (!arm_dc_feature(s
, ARM_FEATURE_M
) &&
10505 extract32(insn
, 0, 8) != 0) {
10510 tmp
= tcg_temp_new_i32();
10511 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10512 addr
= tcg_const_i32(insn
& 0xff);
10513 gen_helper_v7m_mrs(tmp
, cpu_env
, addr
);
10514 tcg_temp_free_i32(addr
);
10516 gen_helper_cpsr_read(tmp
, cpu_env
);
10518 store_reg(s
, rd
, tmp
);
10521 if (extract32(insn
, 5, 1) &&
10522 !arm_dc_feature(s
, ARM_FEATURE_M
)) {
10524 int sysm
= extract32(insn
, 16, 4) |
10525 (extract32(insn
, 4, 1) << 4);
10527 gen_mrs_banked(s
, 1, sysm
, rd
);
10532 /* Not accessible in user mode. */
10533 if (IS_USER(s
) || arm_dc_feature(s
, ARM_FEATURE_M
)) {
10537 if (extract32(insn
, 16, 4) != 0xf ||
10538 extract32(insn
, 0, 8) != 0) {
10542 tmp
= load_cpu_field(spsr
);
10543 store_reg(s
, rd
, tmp
);
10548 /* Conditional branch. */
10549 op
= (insn
>> 22) & 0xf;
10550 /* Generate a conditional jump to next instruction. */
10551 arm_skip_unless(s
, op
);
10553 /* offset[11:1] = insn[10:0] */
10554 offset
= (insn
& 0x7ff) << 1;
10555 /* offset[17:12] = insn[21:16]. */
10556 offset
|= (insn
& 0x003f0000) >> 4;
10557 /* offset[31:20] = insn[26]. */
10558 offset
|= ((int32_t)((insn
<< 5) & 0x80000000)) >> 11;
10559 /* offset[18] = insn[13]. */
10560 offset
|= (insn
& (1 << 13)) << 5;
10561 /* offset[19] = insn[11]. */
10562 offset
|= (insn
& (1 << 11)) << 8;
10564 /* jump to the offset */
10565 gen_jmp(s
, read_pc(s
) + offset
);
10569 * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx
10570 * - Data-processing (modified immediate, plain binary immediate)
10572 if (insn
& (1 << 25)) {
10574 * 0b1111_0x1x_xxxx_0xxx_xxxx_xxxx
10575 * - Data-processing (plain binary immediate)
10577 if (insn
& (1 << 24)) {
10578 if (insn
& (1 << 20))
10580 /* Bitfield/Saturate. */
10581 op
= (insn
>> 21) & 7;
10583 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
10585 tmp
= tcg_temp_new_i32();
10586 tcg_gen_movi_i32(tmp
, 0);
10588 tmp
= load_reg(s
, rn
);
10591 case 2: /* Signed bitfield extract. */
10593 if (shift
+ imm
> 32)
10596 tcg_gen_sextract_i32(tmp
, tmp
, shift
, imm
);
10599 case 6: /* Unsigned bitfield extract. */
10601 if (shift
+ imm
> 32)
10604 tcg_gen_extract_i32(tmp
, tmp
, shift
, imm
);
10607 case 3: /* Bitfield insert/clear. */
10610 imm
= imm
+ 1 - shift
;
10612 tmp2
= load_reg(s
, rd
);
10613 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, shift
, imm
);
10614 tcg_temp_free_i32(tmp2
);
10619 default: /* Saturate. */
10621 tcg_gen_sari_i32(tmp
, tmp
, shift
);
10623 tcg_gen_shli_i32(tmp
, tmp
, shift
);
10625 tmp2
= tcg_const_i32(imm
);
10628 if ((op
& 1) && shift
== 0) {
10629 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10630 tcg_temp_free_i32(tmp
);
10631 tcg_temp_free_i32(tmp2
);
10634 gen_helper_usat16(tmp
, cpu_env
, tmp
, tmp2
);
10636 gen_helper_usat(tmp
, cpu_env
, tmp
, tmp2
);
10640 if ((op
& 1) && shift
== 0) {
10641 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
10642 tcg_temp_free_i32(tmp
);
10643 tcg_temp_free_i32(tmp2
);
10646 gen_helper_ssat16(tmp
, cpu_env
, tmp
, tmp2
);
10648 gen_helper_ssat(tmp
, cpu_env
, tmp
, tmp2
);
10651 tcg_temp_free_i32(tmp2
);
10654 store_reg(s
, rd
, tmp
);
10656 imm
= ((insn
& 0x04000000) >> 15)
10657 | ((insn
& 0x7000) >> 4) | (insn
& 0xff);
10658 if (insn
& (1 << 22)) {
10659 /* 16-bit immediate. */
10660 imm
|= (insn
>> 4) & 0xf000;
10661 if (insn
& (1 << 23)) {
10663 tmp
= load_reg(s
, rd
);
10664 tcg_gen_ext16u_i32(tmp
, tmp
);
10665 tcg_gen_ori_i32(tmp
, tmp
, imm
<< 16);
10668 tmp
= tcg_temp_new_i32();
10669 tcg_gen_movi_i32(tmp
, imm
);
10671 store_reg(s
, rd
, tmp
);
10673 /* Add/sub 12-bit immediate. */
10674 if (insn
& (1 << 23)) {
10677 tmp
= add_reg_for_lit(s
, rn
, imm
);
10678 if (rn
== 13 && rd
== 13) {
10679 /* ADD SP, SP, imm or SUB SP, SP, imm */
10680 store_sp_checked(s
, tmp
);
10682 store_reg(s
, rd
, tmp
);
10688 * 0b1111_0x0x_xxxx_0xxx_xxxx_xxxx
10689 * - Data-processing (modified immediate)
10691 int shifter_out
= 0;
10692 /* modified 12-bit immediate. */
10693 shift
= ((insn
& 0x04000000) >> 23) | ((insn
& 0x7000) >> 12);
10694 imm
= (insn
& 0xff);
10697 /* Nothing to do. */
10699 case 1: /* 00XY00XY */
10702 case 2: /* XY00XY00 */
10706 case 3: /* XYXYXYXY */
10710 default: /* Rotated constant. */
10711 shift
= (shift
<< 1) | (imm
>> 7);
10713 imm
= imm
<< (32 - shift
);
10717 tmp2
= tcg_temp_new_i32();
10718 tcg_gen_movi_i32(tmp2
, imm
);
10719 rn
= (insn
>> 16) & 0xf;
10721 tmp
= tcg_temp_new_i32();
10722 tcg_gen_movi_i32(tmp
, 0);
10724 tmp
= load_reg(s
, rn
);
10726 op
= (insn
>> 21) & 0xf;
10727 if (gen_thumb2_data_op(s
, op
, (insn
& (1 << 20)) != 0,
10728 shifter_out
, tmp
, tmp2
))
10730 tcg_temp_free_i32(tmp2
);
10731 rd
= (insn
>> 8) & 0xf;
10732 if (rd
== 13 && rn
== 13
10733 && (op
== 8 || op
== 13)) {
10734 /* ADD(S) SP, SP, imm or SUB(S) SP, SP, imm */
10735 store_sp_checked(s
, tmp
);
10736 } else if (rd
!= 15) {
10737 store_reg(s
, rd
, tmp
);
10739 tcg_temp_free_i32(tmp
);
10744 case 12: /* Load/store single data item. */
10751 if ((insn
& 0x01100000) == 0x01000000) {
10752 if (disas_neon_ls_insn(s
, insn
)) {
10757 op
= ((insn
>> 21) & 3) | ((insn
>> 22) & 4);
10759 if (!(insn
& (1 << 20))) {
10763 /* Byte or halfword load space with dest == r15 : memory hints.
10764 * Catch them early so we don't emit pointless addressing code.
10765 * This space is a mix of:
10766 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
10767 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
10769 * unallocated hints, which must be treated as NOPs
10770 * UNPREDICTABLE space, which we NOP or UNDEF depending on
10771 * which is easiest for the decoding logic
10772 * Some space which must UNDEF
10774 int op1
= (insn
>> 23) & 3;
10775 int op2
= (insn
>> 6) & 0x3f;
10780 /* UNPREDICTABLE, unallocated hint or
10781 * PLD/PLDW/PLI (literal)
10786 return; /* PLD/PLDW/PLI or unallocated hint */
10788 if ((op2
== 0) || ((op2
& 0x3c) == 0x30)) {
10789 return; /* PLD/PLDW/PLI or unallocated hint */
10791 /* UNDEF space, or an UNPREDICTABLE */
10795 memidx
= get_mem_index(s
);
10796 imm
= insn
& 0xfff;
10797 if (insn
& (1 << 23)) {
10798 /* PC relative or Positive offset. */
10799 addr
= add_reg_for_lit(s
, rn
, imm
);
10800 } else if (rn
== 15) {
10801 /* PC relative with negative offset. */
10802 addr
= add_reg_for_lit(s
, rn
, -imm
);
10804 addr
= load_reg(s
, rn
);
10806 switch ((insn
>> 8) & 0xf) {
10807 case 0x0: /* Shifted Register. */
10808 shift
= (insn
>> 4) & 0xf;
10810 tcg_temp_free_i32(addr
);
10813 tmp
= load_reg(s
, rm
);
10814 tcg_gen_shli_i32(tmp
, tmp
, shift
);
10815 tcg_gen_add_i32(addr
, addr
, tmp
);
10816 tcg_temp_free_i32(tmp
);
10818 case 0xc: /* Negative offset. */
10819 tcg_gen_addi_i32(addr
, addr
, -imm
);
10821 case 0xe: /* User privilege. */
10822 tcg_gen_addi_i32(addr
, addr
, imm
);
10823 memidx
= get_a32_user_mem_index(s
);
10825 case 0x9: /* Post-decrement. */
10827 /* Fall through. */
10828 case 0xb: /* Post-increment. */
10832 case 0xd: /* Pre-decrement. */
10834 /* Fall through. */
10835 case 0xf: /* Pre-increment. */
10839 tcg_temp_free_i32(addr
);
10844 issinfo
= writeback
? ISSInvalid
: rs
;
10846 if (s
->v8m_stackcheck
&& rn
== 13 && writeback
) {
10848 * Stackcheck. Here we know 'addr' is the current SP;
10849 * if imm is +ve we're moving SP up, else down. It is
10850 * UNKNOWN whether the limit check triggers when SP starts
10851 * below the limit and ends up above it; we chose to do so.
10853 if ((int32_t)imm
< 0) {
10854 TCGv_i32 newsp
= tcg_temp_new_i32();
10856 tcg_gen_addi_i32(newsp
, addr
, imm
);
10857 gen_helper_v8m_stackcheck(cpu_env
, newsp
);
10858 tcg_temp_free_i32(newsp
);
10860 gen_helper_v8m_stackcheck(cpu_env
, addr
);
10864 if (writeback
&& !postinc
) {
10865 tcg_gen_addi_i32(addr
, addr
, imm
);
10868 if (insn
& (1 << 20)) {
10870 tmp
= tcg_temp_new_i32();
10873 gen_aa32_ld8u_iss(s
, tmp
, addr
, memidx
, issinfo
);
10876 gen_aa32_ld8s_iss(s
, tmp
, addr
, memidx
, issinfo
);
10879 gen_aa32_ld16u_iss(s
, tmp
, addr
, memidx
, issinfo
);
10882 gen_aa32_ld16s_iss(s
, tmp
, addr
, memidx
, issinfo
);
10885 gen_aa32_ld32u_iss(s
, tmp
, addr
, memidx
, issinfo
);
10888 tcg_temp_free_i32(tmp
);
10889 tcg_temp_free_i32(addr
);
10893 gen_bx_excret(s
, tmp
);
10895 store_reg(s
, rs
, tmp
);
10899 tmp
= load_reg(s
, rs
);
10902 gen_aa32_st8_iss(s
, tmp
, addr
, memidx
, issinfo
);
10905 gen_aa32_st16_iss(s
, tmp
, addr
, memidx
, issinfo
);
10908 gen_aa32_st32_iss(s
, tmp
, addr
, memidx
, issinfo
);
10911 tcg_temp_free_i32(tmp
);
10912 tcg_temp_free_i32(addr
);
10915 tcg_temp_free_i32(tmp
);
10918 tcg_gen_addi_i32(addr
, addr
, imm
);
10920 store_reg(s
, rn
, addr
);
10922 tcg_temp_free_i32(addr
);
10931 unallocated_encoding(s
);
10934 static void disas_thumb_insn(DisasContext
*s
, uint32_t insn
)
10936 uint32_t val
, op
, rm
, rn
, rd
, shift
, cond
;
10943 switch (insn
>> 12) {
10947 op
= (insn
>> 11) & 3;
10950 * 0b0001_1xxx_xxxx_xxxx
10951 * - Add, subtract (three low registers)
10952 * - Add, subtract (two low registers and immediate)
10954 rn
= (insn
>> 3) & 7;
10955 tmp
= load_reg(s
, rn
);
10956 if (insn
& (1 << 10)) {
10958 tmp2
= tcg_temp_new_i32();
10959 tcg_gen_movi_i32(tmp2
, (insn
>> 6) & 7);
10962 rm
= (insn
>> 6) & 7;
10963 tmp2
= load_reg(s
, rm
);
10965 if (insn
& (1 << 9)) {
10966 if (s
->condexec_mask
)
10967 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
10969 gen_sub_CC(tmp
, tmp
, tmp2
);
10971 if (s
->condexec_mask
)
10972 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10974 gen_add_CC(tmp
, tmp
, tmp2
);
10976 tcg_temp_free_i32(tmp2
);
10977 store_reg(s
, rd
, tmp
);
10979 /* shift immediate */
10980 rm
= (insn
>> 3) & 7;
10981 shift
= (insn
>> 6) & 0x1f;
10982 tmp
= load_reg(s
, rm
);
10983 gen_arm_shift_im(tmp
, op
, shift
, s
->condexec_mask
== 0);
10984 if (!s
->condexec_mask
)
10986 store_reg(s
, rd
, tmp
);
10991 * 0b001x_xxxx_xxxx_xxxx
10992 * - Add, subtract, compare, move (one low register and immediate)
10994 op
= (insn
>> 11) & 3;
10995 rd
= (insn
>> 8) & 0x7;
10996 if (op
== 0) { /* mov */
10997 tmp
= tcg_temp_new_i32();
10998 tcg_gen_movi_i32(tmp
, insn
& 0xff);
10999 if (!s
->condexec_mask
)
11001 store_reg(s
, rd
, tmp
);
11003 tmp
= load_reg(s
, rd
);
11004 tmp2
= tcg_temp_new_i32();
11005 tcg_gen_movi_i32(tmp2
, insn
& 0xff);
11008 gen_sub_CC(tmp
, tmp
, tmp2
);
11009 tcg_temp_free_i32(tmp
);
11010 tcg_temp_free_i32(tmp2
);
11013 if (s
->condexec_mask
)
11014 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
11016 gen_add_CC(tmp
, tmp
, tmp2
);
11017 tcg_temp_free_i32(tmp2
);
11018 store_reg(s
, rd
, tmp
);
11021 if (s
->condexec_mask
)
11022 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
11024 gen_sub_CC(tmp
, tmp
, tmp2
);
11025 tcg_temp_free_i32(tmp2
);
11026 store_reg(s
, rd
, tmp
);
11032 if (insn
& (1 << 11)) {
11033 rd
= (insn
>> 8) & 7;
11034 /* load pc-relative. Bit 1 of PC is ignored. */
11035 addr
= add_reg_for_lit(s
, 15, (insn
& 0xff) * 4);
11036 tmp
= tcg_temp_new_i32();
11037 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
),
11039 tcg_temp_free_i32(addr
);
11040 store_reg(s
, rd
, tmp
);
11043 if (insn
& (1 << 10)) {
11044 /* 0b0100_01xx_xxxx_xxxx
11045 * - data processing extended, branch and exchange
11047 rd
= (insn
& 7) | ((insn
>> 4) & 8);
11048 rm
= (insn
>> 3) & 0xf;
11049 op
= (insn
>> 8) & 3;
11052 tmp
= load_reg(s
, rd
);
11053 tmp2
= load_reg(s
, rm
);
11054 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
11055 tcg_temp_free_i32(tmp2
);
11057 /* ADD SP, SP, reg */
11058 store_sp_checked(s
, tmp
);
11060 store_reg(s
, rd
, tmp
);
11064 tmp
= load_reg(s
, rd
);
11065 tmp2
= load_reg(s
, rm
);
11066 gen_sub_CC(tmp
, tmp
, tmp2
);
11067 tcg_temp_free_i32(tmp2
);
11068 tcg_temp_free_i32(tmp
);
11070 case 2: /* mov/cpy */
11071 tmp
= load_reg(s
, rm
);
11074 store_sp_checked(s
, tmp
);
11076 store_reg(s
, rd
, tmp
);
11081 /* 0b0100_0111_xxxx_xxxx
11082 * - branch [and link] exchange thumb register
11084 bool link
= insn
& (1 << 7);
11093 /* BXNS/BLXNS: only exists for v8M with the
11094 * security extensions, and always UNDEF if NonSecure.
11095 * We don't implement these in the user-only mode
11096 * either (in theory you can use them from Secure User
11097 * mode but they are too tied in to system emulation.)
11099 if (!s
->v8m_secure
|| IS_USER_ONLY
) {
11110 tmp
= load_reg(s
, rm
);
11112 val
= (uint32_t)s
->base
.pc_next
| 1;
11113 tmp2
= tcg_temp_new_i32();
11114 tcg_gen_movi_i32(tmp2
, val
);
11115 store_reg(s
, 14, tmp2
);
11118 /* Only BX works as exception-return, not BLX */
11119 gen_bx_excret(s
, tmp
);
11128 * 0b0100_00xx_xxxx_xxxx
11129 * - Data-processing (two low registers)
11132 rm
= (insn
>> 3) & 7;
11133 op
= (insn
>> 6) & 0xf;
11134 if (op
== 2 || op
== 3 || op
== 4 || op
== 7) {
11135 /* the shift/rotate ops want the operands backwards */
11144 if (op
== 9) { /* neg */
11145 tmp
= tcg_temp_new_i32();
11146 tcg_gen_movi_i32(tmp
, 0);
11147 } else if (op
!= 0xf) { /* mvn doesn't read its first operand */
11148 tmp
= load_reg(s
, rd
);
11153 tmp2
= load_reg(s
, rm
);
11155 case 0x0: /* and */
11156 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
11157 if (!s
->condexec_mask
)
11160 case 0x1: /* eor */
11161 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
11162 if (!s
->condexec_mask
)
11165 case 0x2: /* lsl */
11166 if (s
->condexec_mask
) {
11167 gen_shl(tmp2
, tmp2
, tmp
);
11169 gen_helper_shl_cc(tmp2
, cpu_env
, tmp2
, tmp
);
11170 gen_logic_CC(tmp2
);
11173 case 0x3: /* lsr */
11174 if (s
->condexec_mask
) {
11175 gen_shr(tmp2
, tmp2
, tmp
);
11177 gen_helper_shr_cc(tmp2
, cpu_env
, tmp2
, tmp
);
11178 gen_logic_CC(tmp2
);
11181 case 0x4: /* asr */
11182 if (s
->condexec_mask
) {
11183 gen_sar(tmp2
, tmp2
, tmp
);
11185 gen_helper_sar_cc(tmp2
, cpu_env
, tmp2
, tmp
);
11186 gen_logic_CC(tmp2
);
11189 case 0x5: /* adc */
11190 if (s
->condexec_mask
) {
11191 gen_adc(tmp
, tmp2
);
11193 gen_adc_CC(tmp
, tmp
, tmp2
);
11196 case 0x6: /* sbc */
11197 if (s
->condexec_mask
) {
11198 gen_sub_carry(tmp
, tmp
, tmp2
);
11200 gen_sbc_CC(tmp
, tmp
, tmp2
);
11203 case 0x7: /* ror */
11204 if (s
->condexec_mask
) {
11205 tcg_gen_andi_i32(tmp
, tmp
, 0x1f);
11206 tcg_gen_rotr_i32(tmp2
, tmp2
, tmp
);
11208 gen_helper_ror_cc(tmp2
, cpu_env
, tmp2
, tmp
);
11209 gen_logic_CC(tmp2
);
11212 case 0x8: /* tst */
11213 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
11217 case 0x9: /* neg */
11218 if (s
->condexec_mask
)
11219 tcg_gen_neg_i32(tmp
, tmp2
);
11221 gen_sub_CC(tmp
, tmp
, tmp2
);
11223 case 0xa: /* cmp */
11224 gen_sub_CC(tmp
, tmp
, tmp2
);
11227 case 0xb: /* cmn */
11228 gen_add_CC(tmp
, tmp
, tmp2
);
11231 case 0xc: /* orr */
11232 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
11233 if (!s
->condexec_mask
)
11236 case 0xd: /* mul */
11237 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
11238 if (!s
->condexec_mask
)
11241 case 0xe: /* bic */
11242 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
11243 if (!s
->condexec_mask
)
11246 case 0xf: /* mvn */
11247 tcg_gen_not_i32(tmp2
, tmp2
);
11248 if (!s
->condexec_mask
)
11249 gen_logic_CC(tmp2
);
11256 store_reg(s
, rm
, tmp2
);
11258 tcg_temp_free_i32(tmp
);
11260 store_reg(s
, rd
, tmp
);
11261 tcg_temp_free_i32(tmp2
);
11264 tcg_temp_free_i32(tmp
);
11265 tcg_temp_free_i32(tmp2
);
11270 /* load/store register offset. */
11272 rn
= (insn
>> 3) & 7;
11273 rm
= (insn
>> 6) & 7;
11274 op
= (insn
>> 9) & 7;
11275 addr
= load_reg(s
, rn
);
11276 tmp
= load_reg(s
, rm
);
11277 tcg_gen_add_i32(addr
, addr
, tmp
);
11278 tcg_temp_free_i32(tmp
);
11280 if (op
< 3) { /* store */
11281 tmp
= load_reg(s
, rd
);
11283 tmp
= tcg_temp_new_i32();
11288 gen_aa32_st32_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11291 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11294 gen_aa32_st8_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11296 case 3: /* ldrsb */
11297 gen_aa32_ld8s_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11300 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11303 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11306 gen_aa32_ld8u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11308 case 7: /* ldrsh */
11309 gen_aa32_ld16s_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11312 if (op
>= 3) { /* load */
11313 store_reg(s
, rd
, tmp
);
11315 tcg_temp_free_i32(tmp
);
11317 tcg_temp_free_i32(addr
);
11321 /* load/store word immediate offset */
11323 rn
= (insn
>> 3) & 7;
11324 addr
= load_reg(s
, rn
);
11325 val
= (insn
>> 4) & 0x7c;
11326 tcg_gen_addi_i32(addr
, addr
, val
);
11328 if (insn
& (1 << 11)) {
11330 tmp
= tcg_temp_new_i32();
11331 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
11332 store_reg(s
, rd
, tmp
);
11335 tmp
= load_reg(s
, rd
);
11336 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
11337 tcg_temp_free_i32(tmp
);
11339 tcg_temp_free_i32(addr
);
11343 /* load/store byte immediate offset */
11345 rn
= (insn
>> 3) & 7;
11346 addr
= load_reg(s
, rn
);
11347 val
= (insn
>> 6) & 0x1f;
11348 tcg_gen_addi_i32(addr
, addr
, val
);
11350 if (insn
& (1 << 11)) {
11352 tmp
= tcg_temp_new_i32();
11353 gen_aa32_ld8u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11354 store_reg(s
, rd
, tmp
);
11357 tmp
= load_reg(s
, rd
);
11358 gen_aa32_st8_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11359 tcg_temp_free_i32(tmp
);
11361 tcg_temp_free_i32(addr
);
11365 /* load/store halfword immediate offset */
11367 rn
= (insn
>> 3) & 7;
11368 addr
= load_reg(s
, rn
);
11369 val
= (insn
>> 5) & 0x3e;
11370 tcg_gen_addi_i32(addr
, addr
, val
);
11372 if (insn
& (1 << 11)) {
11374 tmp
= tcg_temp_new_i32();
11375 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11376 store_reg(s
, rd
, tmp
);
11379 tmp
= load_reg(s
, rd
);
11380 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11381 tcg_temp_free_i32(tmp
);
11383 tcg_temp_free_i32(addr
);
11387 /* load/store from stack */
11388 rd
= (insn
>> 8) & 7;
11389 addr
= load_reg(s
, 13);
11390 val
= (insn
& 0xff) * 4;
11391 tcg_gen_addi_i32(addr
, addr
, val
);
11393 if (insn
& (1 << 11)) {
11395 tmp
= tcg_temp_new_i32();
11396 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11397 store_reg(s
, rd
, tmp
);
11400 tmp
= load_reg(s
, rd
);
11401 gen_aa32_st32_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
11402 tcg_temp_free_i32(tmp
);
11404 tcg_temp_free_i32(addr
);
11409 * 0b1010_xxxx_xxxx_xxxx
11410 * - Add PC/SP (immediate)
11412 rd
= (insn
>> 8) & 7;
11413 val
= (insn
& 0xff) * 4;
11414 tmp
= add_reg_for_lit(s
, insn
& (1 << 11) ? 13 : 15, val
);
11415 store_reg(s
, rd
, tmp
);
11420 op
= (insn
>> 8) & 0xf;
11424 * 0b1011_0000_xxxx_xxxx
11425 * - ADD (SP plus immediate)
11426 * - SUB (SP minus immediate)
11428 tmp
= load_reg(s
, 13);
11429 val
= (insn
& 0x7f) * 4;
11430 if (insn
& (1 << 7))
11431 val
= -(int32_t)val
;
11432 tcg_gen_addi_i32(tmp
, tmp
, val
);
11433 store_sp_checked(s
, tmp
);
11436 case 2: /* sign/zero extend. */
11439 rm
= (insn
>> 3) & 7;
11440 tmp
= load_reg(s
, rm
);
11441 switch ((insn
>> 6) & 3) {
11442 case 0: gen_sxth(tmp
); break;
11443 case 1: gen_sxtb(tmp
); break;
11444 case 2: gen_uxth(tmp
); break;
11445 case 3: gen_uxtb(tmp
); break;
11447 store_reg(s
, rd
, tmp
);
11449 case 4: case 5: case 0xc: case 0xd:
11451 * 0b1011_x10x_xxxx_xxxx
11454 addr
= load_reg(s
, 13);
11455 if (insn
& (1 << 8))
11459 for (i
= 0; i
< 8; i
++) {
11460 if (insn
& (1 << i
))
11463 if ((insn
& (1 << 11)) == 0) {
11464 tcg_gen_addi_i32(addr
, addr
, -offset
);
11467 if (s
->v8m_stackcheck
) {
11469 * Here 'addr' is the lower of "old SP" and "new SP";
11470 * if this is a pop that starts below the limit and ends
11471 * above it, it is UNKNOWN whether the limit check triggers;
11472 * we choose to trigger.
11474 gen_helper_v8m_stackcheck(cpu_env
, addr
);
11477 for (i
= 0; i
< 8; i
++) {
11478 if (insn
& (1 << i
)) {
11479 if (insn
& (1 << 11)) {
11481 tmp
= tcg_temp_new_i32();
11482 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
11483 store_reg(s
, i
, tmp
);
11486 tmp
= load_reg(s
, i
);
11487 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
11488 tcg_temp_free_i32(tmp
);
11490 /* advance to the next address. */
11491 tcg_gen_addi_i32(addr
, addr
, 4);
11495 if (insn
& (1 << 8)) {
11496 if (insn
& (1 << 11)) {
11498 tmp
= tcg_temp_new_i32();
11499 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
11500 /* don't set the pc until the rest of the instruction
11504 tmp
= load_reg(s
, 14);
11505 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
11506 tcg_temp_free_i32(tmp
);
11508 tcg_gen_addi_i32(addr
, addr
, 4);
11510 if ((insn
& (1 << 11)) == 0) {
11511 tcg_gen_addi_i32(addr
, addr
, -offset
);
11513 /* write back the new stack pointer */
11514 store_reg(s
, 13, addr
);
11515 /* set the new PC value */
11516 if ((insn
& 0x0900) == 0x0900) {
11517 store_reg_from_load(s
, 15, tmp
);
11521 case 1: case 3: case 9: case 11: /* czb */
11523 tmp
= load_reg(s
, rm
);
11524 arm_gen_condlabel(s
);
11525 if (insn
& (1 << 11))
11526 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, s
->condlabel
);
11528 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, s
->condlabel
);
11529 tcg_temp_free_i32(tmp
);
11530 offset
= ((insn
& 0xf8) >> 2) | (insn
& 0x200) >> 3;
11531 gen_jmp(s
, read_pc(s
) + offset
);
11534 case 15: /* IT, nop-hint. */
11535 if ((insn
& 0xf) == 0) {
11536 gen_nop_hint(s
, (insn
>> 4) & 0xf);
11542 * Combinations of firstcond and mask which set up an 0b1111
11543 * condition are UNPREDICTABLE; we take the CONSTRAINED
11544 * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110,
11545 * i.e. both meaning "execute always".
11547 s
->condexec_cond
= (insn
>> 4) & 0xe;
11548 s
->condexec_mask
= insn
& 0x1f;
11549 /* No actual code generated for this insn, just setup state. */
11552 case 0xe: /* bkpt */
11554 int imm8
= extract32(insn
, 0, 8);
11556 gen_exception_bkpt_insn(s
, syn_aa32_bkpt(imm8
, true));
11560 case 0xa: /* rev, and hlt */
11562 int op1
= extract32(insn
, 6, 2);
11566 int imm6
= extract32(insn
, 0, 6);
11572 /* Otherwise this is rev */
11574 rn
= (insn
>> 3) & 0x7;
11576 tmp
= load_reg(s
, rn
);
11578 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
11579 case 1: gen_rev16(tmp
); break;
11580 case 3: gen_revsh(tmp
); break;
11582 g_assert_not_reached();
11584 store_reg(s
, rd
, tmp
);
11589 switch ((insn
>> 5) & 7) {
11593 if (((insn
>> 3) & 1) != !!(s
->be_data
== MO_BE
)) {
11594 gen_helper_setend(cpu_env
);
11595 s
->base
.is_jmp
= DISAS_UPDATE
;
11604 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
11605 tmp
= tcg_const_i32((insn
& (1 << 4)) != 0);
11608 addr
= tcg_const_i32(19);
11609 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
11610 tcg_temp_free_i32(addr
);
11614 addr
= tcg_const_i32(16);
11615 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
11616 tcg_temp_free_i32(addr
);
11618 tcg_temp_free_i32(tmp
);
11621 if (insn
& (1 << 4)) {
11622 shift
= CPSR_A
| CPSR_I
| CPSR_F
;
11626 gen_set_psr_im(s
, ((insn
& 7) << 6), 0, shift
);
11641 /* load/store multiple */
11642 TCGv_i32 loaded_var
= NULL
;
11643 rn
= (insn
>> 8) & 0x7;
11644 addr
= load_reg(s
, rn
);
11645 for (i
= 0; i
< 8; i
++) {
11646 if (insn
& (1 << i
)) {
11647 if (insn
& (1 << 11)) {
11649 tmp
= tcg_temp_new_i32();
11650 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
11654 store_reg(s
, i
, tmp
);
11658 tmp
= load_reg(s
, i
);
11659 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
11660 tcg_temp_free_i32(tmp
);
11662 /* advance to the next address */
11663 tcg_gen_addi_i32(addr
, addr
, 4);
11666 if ((insn
& (1 << rn
)) == 0) {
11667 /* base reg not in list: base register writeback */
11668 store_reg(s
, rn
, addr
);
11670 /* base reg in list: if load, complete it now */
11671 if (insn
& (1 << 11)) {
11672 store_reg(s
, rn
, loaded_var
);
11674 tcg_temp_free_i32(addr
);
11679 /* conditional branch or swi */
11680 cond
= (insn
>> 8) & 0xf;
11686 gen_set_pc_im(s
, s
->base
.pc_next
);
11687 s
->svc_imm
= extract32(insn
, 0, 8);
11688 s
->base
.is_jmp
= DISAS_SWI
;
11691 /* generate a conditional jump to next instruction */
11692 arm_skip_unless(s
, cond
);
11694 /* jump to the offset */
11696 offset
= ((int32_t)insn
<< 24) >> 24;
11697 val
+= offset
<< 1;
11702 if (insn
& (1 << 11)) {
11703 /* thumb_insn_is_16bit() ensures we can't get here for
11704 * a Thumb2 CPU, so this must be a thumb1 split BL/BLX:
11705 * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF)
11707 assert(!arm_dc_feature(s
, ARM_FEATURE_THUMB2
));
11709 offset
= ((insn
& 0x7ff) << 1);
11710 tmp
= load_reg(s
, 14);
11711 tcg_gen_addi_i32(tmp
, tmp
, offset
);
11712 tcg_gen_andi_i32(tmp
, tmp
, 0xfffffffc);
11714 tmp2
= tcg_temp_new_i32();
11715 tcg_gen_movi_i32(tmp2
, s
->base
.pc_next
| 1);
11716 store_reg(s
, 14, tmp2
);
11720 /* unconditional branch */
11722 offset
= ((int32_t)insn
<< 21) >> 21;
11723 val
+= offset
<< 1;
11728 /* thumb_insn_is_16bit() ensures we can't get here for
11729 * a Thumb2 CPU, so this must be a thumb1 split BL/BLX.
11731 assert(!arm_dc_feature(s
, ARM_FEATURE_THUMB2
));
11733 if (insn
& (1 << 11)) {
11734 /* 0b1111_1xxx_xxxx_xxxx : BL suffix */
11735 offset
= ((insn
& 0x7ff) << 1) | 1;
11736 tmp
= load_reg(s
, 14);
11737 tcg_gen_addi_i32(tmp
, tmp
, offset
);
11739 tmp2
= tcg_temp_new_i32();
11740 tcg_gen_movi_i32(tmp2
, s
->base
.pc_next
| 1);
11741 store_reg(s
, 14, tmp2
);
11744 /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
11745 uint32_t uoffset
= ((int32_t)insn
<< 21) >> 9;
11747 tcg_gen_movi_i32(cpu_R
[14], read_pc(s
) + uoffset
);
11754 unallocated_encoding(s
);
11757 static bool insn_crosses_page(CPUARMState
*env
, DisasContext
*s
)
11759 /* Return true if the insn at dc->base.pc_next might cross a page boundary.
11760 * (False positives are OK, false negatives are not.)
11761 * We know this is a Thumb insn, and our caller ensures we are
11762 * only called if dc->base.pc_next is less than 4 bytes from the page
11763 * boundary, so we cross the page if the first 16 bits indicate
11764 * that this is a 32 bit insn.
11766 uint16_t insn
= arm_lduw_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
11768 return !thumb_insn_is_16bit(s
, s
->base
.pc_next
, insn
);
11771 static void arm_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
11773 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11774 CPUARMState
*env
= cs
->env_ptr
;
11775 ARMCPU
*cpu
= env_archcpu(env
);
11776 uint32_t tb_flags
= dc
->base
.tb
->flags
;
11777 uint32_t condexec
, core_mmu_idx
;
11779 dc
->isar
= &cpu
->isar
;
11783 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11784 * there is no secure EL1, so we route exceptions to EL3.
11786 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11787 !arm_el_is_aa64(env
, 3);
11788 dc
->thumb
= FIELD_EX32(tb_flags
, TBFLAG_A32
, THUMB
);
11789 dc
->sctlr_b
= FIELD_EX32(tb_flags
, TBFLAG_A32
, SCTLR_B
);
11790 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
11791 condexec
= FIELD_EX32(tb_flags
, TBFLAG_A32
, CONDEXEC
);
11792 dc
->condexec_mask
= (condexec
& 0xf) << 1;
11793 dc
->condexec_cond
= condexec
>> 4;
11794 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
11795 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
11796 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11797 #if !defined(CONFIG_USER_ONLY)
11798 dc
->user
= (dc
->current_el
== 0);
11800 dc
->ns
= FIELD_EX32(tb_flags
, TBFLAG_A32
, NS
);
11801 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
11802 dc
->vfp_enabled
= FIELD_EX32(tb_flags
, TBFLAG_A32
, VFPEN
);
11803 dc
->vec_len
= FIELD_EX32(tb_flags
, TBFLAG_A32
, VECLEN
);
11804 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
11805 dc
->c15_cpar
= FIELD_EX32(tb_flags
, TBFLAG_A32
, XSCALE_CPAR
);
11806 dc
->vec_stride
= 0;
11808 dc
->vec_stride
= FIELD_EX32(tb_flags
, TBFLAG_A32
, VECSTRIDE
);
11811 dc
->v7m_handler_mode
= FIELD_EX32(tb_flags
, TBFLAG_A32
, HANDLER
);
11812 dc
->v8m_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
11813 regime_is_secure(env
, dc
->mmu_idx
);
11814 dc
->v8m_stackcheck
= FIELD_EX32(tb_flags
, TBFLAG_A32
, STACKCHECK
);
11815 dc
->v8m_fpccr_s_wrong
= FIELD_EX32(tb_flags
, TBFLAG_A32
, FPCCR_S_WRONG
);
11816 dc
->v7m_new_fp_ctxt_needed
=
11817 FIELD_EX32(tb_flags
, TBFLAG_A32
, NEW_FP_CTXT_NEEDED
);
11818 dc
->v7m_lspact
= FIELD_EX32(tb_flags
, TBFLAG_A32
, LSPACT
);
11819 dc
->cp_regs
= cpu
->cp_regs
;
11820 dc
->features
= env
->features
;
11822 /* Single step state. The code-generation logic here is:
11824 * generate code with no special handling for single-stepping (except
11825 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11826 * this happens anyway because those changes are all system register or
11828 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11829 * emit code for one insn
11830 * emit code to clear PSTATE.SS
11831 * emit code to generate software step exception for completed step
11832 * end TB (as usual for having generated an exception)
11833 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11834 * emit code to generate a software step exception
11837 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
11838 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
11839 dc
->is_ldex
= false;
11840 if (!arm_feature(env
, ARM_FEATURE_M
)) {
11841 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
11844 dc
->page_start
= dc
->base
.pc_first
& TARGET_PAGE_MASK
;
11846 /* If architectural single step active, limit to 1. */
11847 if (is_singlestepping(dc
)) {
11848 dc
->base
.max_insns
= 1;
11851 /* ARM is a fixed-length ISA. Bound the number of insns to execute
11852 to those left on the page. */
11854 int bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
11855 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
11858 cpu_V0
= tcg_temp_new_i64();
11859 cpu_V1
= tcg_temp_new_i64();
11860 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
11861 cpu_M0
= tcg_temp_new_i64();
11864 static void arm_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
11866 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11868 /* A note on handling of the condexec (IT) bits:
11870 * We want to avoid the overhead of having to write the updated condexec
11871 * bits back to the CPUARMState for every instruction in an IT block. So:
11872 * (1) if the condexec bits are not already zero then we write
11873 * zero back into the CPUARMState now. This avoids complications trying
11874 * to do it at the end of the block. (For example if we don't do this
11875 * it's hard to identify whether we can safely skip writing condexec
11876 * at the end of the TB, which we definitely want to do for the case
11877 * where a TB doesn't do anything with the IT state at all.)
11878 * (2) if we are going to leave the TB then we call gen_set_condexec()
11879 * which will write the correct value into CPUARMState if zero is wrong.
11880 * This is done both for leaving the TB at the end, and for leaving
11881 * it because of an exception we know will happen, which is done in
11882 * gen_exception_insn(). The latter is necessary because we need to
11883 * leave the TB with the PC/IT state just prior to execution of the
11884 * instruction which caused the exception.
11885 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
11886 * then the CPUARMState will be wrong and we need to reset it.
11887 * This is handled in the same way as restoration of the
11888 * PC in these situations; we save the value of the condexec bits
11889 * for each PC via tcg_gen_insn_start(), and restore_state_to_opc()
11890 * then uses this to restore them after an exception.
11892 * Note that there are no instructions which can read the condexec
11893 * bits, and none which can write non-static values to them, so
11894 * we don't need to care about whether CPUARMState is correct in the
11898 /* Reset the conditional execution bits immediately. This avoids
11899 complications trying to do it at the end of the block. */
11900 if (dc
->condexec_mask
|| dc
->condexec_cond
) {
11901 TCGv_i32 tmp
= tcg_temp_new_i32();
11902 tcg_gen_movi_i32(tmp
, 0);
11903 store_cpu_field(tmp
, condexec_bits
);
11907 static void arm_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
11909 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11911 tcg_gen_insn_start(dc
->base
.pc_next
,
11912 (dc
->condexec_cond
<< 4) | (dc
->condexec_mask
>> 1),
11914 dc
->insn_start
= tcg_last_op();
11917 static bool arm_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
11918 const CPUBreakpoint
*bp
)
11920 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11922 if (bp
->flags
& BP_CPU
) {
11923 gen_set_condexec(dc
);
11924 gen_set_pc_im(dc
, dc
->base
.pc_next
);
11925 gen_helper_check_breakpoints(cpu_env
);
11926 /* End the TB early; it's likely not going to be executed */
11927 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
11929 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
11930 /* The address covered by the breakpoint must be
11931 included in [tb->pc, tb->pc + tb->size) in order
11932 to for it to be properly cleared -- thus we
11933 increment the PC here so that the logic setting
11934 tb->size below does the right thing. */
11935 /* TODO: Advance PC by correct instruction length to
11936 * avoid disassembler error messages */
11937 dc
->base
.pc_next
+= 2;
11938 dc
->base
.is_jmp
= DISAS_NORETURN
;
11944 static bool arm_pre_translate_insn(DisasContext
*dc
)
11946 #ifdef CONFIG_USER_ONLY
11947 /* Intercept jump to the magic kernel page. */
11948 if (dc
->base
.pc_next
>= 0xffff0000) {
11949 /* We always get here via a jump, so know we are not in a
11950 conditional execution block. */
11951 gen_exception_internal(EXCP_KERNEL_TRAP
);
11952 dc
->base
.is_jmp
= DISAS_NORETURN
;
11957 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11958 /* Singlestep state is Active-pending.
11959 * If we're in this state at the start of a TB then either
11960 * a) we just took an exception to an EL which is being debugged
11961 * and this is the first insn in the exception handler
11962 * b) debug exceptions were masked and we just unmasked them
11963 * without changing EL (eg by clearing PSTATE.D)
11964 * In either case we're going to take a swstep exception in the
11965 * "did not step an insn" case, and so the syndrome ISV and EX
11966 * bits should be zero.
11968 assert(dc
->base
.num_insns
== 1);
11969 gen_swstep_exception(dc
, 0, 0);
11970 dc
->base
.is_jmp
= DISAS_NORETURN
;
11977 static void arm_post_translate_insn(DisasContext
*dc
)
11979 if (dc
->condjmp
&& !dc
->base
.is_jmp
) {
11980 gen_set_label(dc
->condlabel
);
11983 translator_loop_temp_check(&dc
->base
);
11986 static void arm_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
11988 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11989 CPUARMState
*env
= cpu
->env_ptr
;
11992 if (arm_pre_translate_insn(dc
)) {
11996 dc
->pc_curr
= dc
->base
.pc_next
;
11997 insn
= arm_ldl_code(env
, dc
->base
.pc_next
, dc
->sctlr_b
);
11999 dc
->base
.pc_next
+= 4;
12000 disas_arm_insn(dc
, insn
);
12002 arm_post_translate_insn(dc
);
12004 /* ARM is a fixed-length ISA. We performed the cross-page check
12005 in init_disas_context by adjusting max_insns. */
12008 static bool thumb_insn_is_unconditional(DisasContext
*s
, uint32_t insn
)
12010 /* Return true if this Thumb insn is always unconditional,
12011 * even inside an IT block. This is true of only a very few
12012 * instructions: BKPT, HLT, and SG.
12014 * A larger class of instructions are UNPREDICTABLE if used
12015 * inside an IT block; we do not need to detect those here, because
12016 * what we do by default (perform the cc check and update the IT
12017 * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE
12018 * choice for those situations.
12020 * insn is either a 16-bit or a 32-bit instruction; the two are
12021 * distinguishable because for the 16-bit case the top 16 bits
12022 * are zeroes, and that isn't a valid 32-bit encoding.
12024 if ((insn
& 0xffffff00) == 0xbe00) {
12029 if ((insn
& 0xffffffc0) == 0xba80 && arm_dc_feature(s
, ARM_FEATURE_V8
) &&
12030 !arm_dc_feature(s
, ARM_FEATURE_M
)) {
12031 /* HLT: v8A only. This is unconditional even when it is going to
12032 * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3.
12033 * For v7 cores this was a plain old undefined encoding and so
12034 * honours its cc check. (We might be using the encoding as
12035 * a semihosting trap, but we don't change the cc check behaviour
12036 * on that account, because a debugger connected to a real v7A
12037 * core and emulating semihosting traps by catching the UNDEF
12038 * exception would also only see cases where the cc check passed.
12039 * No guest code should be trying to do a HLT semihosting trap
12040 * in an IT block anyway.
12045 if (insn
== 0xe97fe97f && arm_dc_feature(s
, ARM_FEATURE_V8
) &&
12046 arm_dc_feature(s
, ARM_FEATURE_M
)) {
12054 static void thumb_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
12056 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
12057 CPUARMState
*env
= cpu
->env_ptr
;
12061 if (arm_pre_translate_insn(dc
)) {
12065 dc
->pc_curr
= dc
->base
.pc_next
;
12066 insn
= arm_lduw_code(env
, dc
->base
.pc_next
, dc
->sctlr_b
);
12067 is_16bit
= thumb_insn_is_16bit(dc
, dc
->base
.pc_next
, insn
);
12068 dc
->base
.pc_next
+= 2;
12070 uint32_t insn2
= arm_lduw_code(env
, dc
->base
.pc_next
, dc
->sctlr_b
);
12072 insn
= insn
<< 16 | insn2
;
12073 dc
->base
.pc_next
+= 2;
12077 if (dc
->condexec_mask
&& !thumb_insn_is_unconditional(dc
, insn
)) {
12078 uint32_t cond
= dc
->condexec_cond
;
12081 * Conditionally skip the insn. Note that both 0xe and 0xf mean
12082 * "always"; 0xf is not "never".
12085 arm_skip_unless(dc
, cond
);
12090 disas_thumb_insn(dc
, insn
);
12092 disas_thumb2_insn(dc
, insn
);
12095 /* Advance the Thumb condexec condition. */
12096 if (dc
->condexec_mask
) {
12097 dc
->condexec_cond
= ((dc
->condexec_cond
& 0xe) |
12098 ((dc
->condexec_mask
>> 4) & 1));
12099 dc
->condexec_mask
= (dc
->condexec_mask
<< 1) & 0x1f;
12100 if (dc
->condexec_mask
== 0) {
12101 dc
->condexec_cond
= 0;
12105 arm_post_translate_insn(dc
);
12107 /* Thumb is a variable-length ISA. Stop translation when the next insn
12108 * will touch a new page. This ensures that prefetch aborts occur at
12111 * We want to stop the TB if the next insn starts in a new page,
12112 * or if it spans between this page and the next. This means that
12113 * if we're looking at the last halfword in the page we need to
12114 * see if it's a 16-bit Thumb insn (which will fit in this TB)
12115 * or a 32-bit Thumb insn (which won't).
12116 * This is to avoid generating a silly TB with a single 16-bit insn
12117 * in it at the end of this page (which would execute correctly
12118 * but isn't very efficient).
12120 if (dc
->base
.is_jmp
== DISAS_NEXT
12121 && (dc
->base
.pc_next
- dc
->page_start
>= TARGET_PAGE_SIZE
12122 || (dc
->base
.pc_next
- dc
->page_start
>= TARGET_PAGE_SIZE
- 3
12123 && insn_crosses_page(env
, dc
)))) {
12124 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
12128 static void arm_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
12130 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
12132 if (tb_cflags(dc
->base
.tb
) & CF_LAST_IO
&& dc
->condjmp
) {
12133 /* FIXME: This can theoretically happen with self-modifying code. */
12134 cpu_abort(cpu
, "IO on conditional branch instruction");
12137 /* At this stage dc->condjmp will only be set when the skipped
12138 instruction was a conditional branch or trap, and the PC has
12139 already been written. */
12140 gen_set_condexec(dc
);
12141 if (dc
->base
.is_jmp
== DISAS_BX_EXCRET
) {
12142 /* Exception return branches need some special case code at the
12143 * end of the TB, which is complex enough that it has to
12144 * handle the single-step vs not and the condition-failed
12145 * insn codepath itself.
12147 gen_bx_excret_final_code(dc
);
12148 } else if (unlikely(is_singlestepping(dc
))) {
12149 /* Unconditional and "condition passed" instruction codepath. */
12150 switch (dc
->base
.is_jmp
) {
12152 gen_ss_advance(dc
);
12153 gen_exception(EXCP_SWI
, syn_aa32_svc(dc
->svc_imm
, dc
->thumb
),
12154 default_exception_el(dc
));
12157 gen_ss_advance(dc
);
12158 gen_exception(EXCP_HVC
, syn_aa32_hvc(dc
->svc_imm
), 2);
12161 gen_ss_advance(dc
);
12162 gen_exception(EXCP_SMC
, syn_aa32_smc(), 3);
12165 case DISAS_TOO_MANY
:
12167 gen_set_pc_im(dc
, dc
->base
.pc_next
);
12170 /* FIXME: Single stepping a WFI insn will not halt the CPU. */
12171 gen_singlestep_exception(dc
);
12173 case DISAS_NORETURN
:
12177 /* While branches must always occur at the end of an IT block,
12178 there are a few other things that can cause us to terminate
12179 the TB in the middle of an IT block:
12180 - Exception generating instructions (bkpt, swi, undefined).
12182 - Hardware watchpoints.
12183 Hardware breakpoints have already been handled and skip this code.
12185 switch(dc
->base
.is_jmp
) {
12187 case DISAS_TOO_MANY
:
12188 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
12194 gen_set_pc_im(dc
, dc
->base
.pc_next
);
12197 /* indicate that the hash table must be used to find the next TB */
12198 tcg_gen_exit_tb(NULL
, 0);
12200 case DISAS_NORETURN
:
12201 /* nothing more to generate */
12205 TCGv_i32 tmp
= tcg_const_i32((dc
->thumb
&&
12206 !(dc
->insn
& (1U << 31))) ? 2 : 4);
12208 gen_helper_wfi(cpu_env
, tmp
);
12209 tcg_temp_free_i32(tmp
);
12210 /* The helper doesn't necessarily throw an exception, but we
12211 * must go back to the main loop to check for interrupts anyway.
12213 tcg_gen_exit_tb(NULL
, 0);
12217 gen_helper_wfe(cpu_env
);
12220 gen_helper_yield(cpu_env
);
12223 gen_exception(EXCP_SWI
, syn_aa32_svc(dc
->svc_imm
, dc
->thumb
),
12224 default_exception_el(dc
));
12227 gen_exception(EXCP_HVC
, syn_aa32_hvc(dc
->svc_imm
), 2);
12230 gen_exception(EXCP_SMC
, syn_aa32_smc(), 3);
12236 /* "Condition failed" instruction codepath for the branch/trap insn */
12237 gen_set_label(dc
->condlabel
);
12238 gen_set_condexec(dc
);
12239 if (unlikely(is_singlestepping(dc
))) {
12240 gen_set_pc_im(dc
, dc
->base
.pc_next
);
12241 gen_singlestep_exception(dc
);
12243 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
12248 static void arm_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
12250 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
12252 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
12253 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
12256 static const TranslatorOps arm_translator_ops
= {
12257 .init_disas_context
= arm_tr_init_disas_context
,
12258 .tb_start
= arm_tr_tb_start
,
12259 .insn_start
= arm_tr_insn_start
,
12260 .breakpoint_check
= arm_tr_breakpoint_check
,
12261 .translate_insn
= arm_tr_translate_insn
,
12262 .tb_stop
= arm_tr_tb_stop
,
12263 .disas_log
= arm_tr_disas_log
,
12266 static const TranslatorOps thumb_translator_ops
= {
12267 .init_disas_context
= arm_tr_init_disas_context
,
12268 .tb_start
= arm_tr_tb_start
,
12269 .insn_start
= arm_tr_insn_start
,
12270 .breakpoint_check
= arm_tr_breakpoint_check
,
12271 .translate_insn
= thumb_tr_translate_insn
,
12272 .tb_stop
= arm_tr_tb_stop
,
12273 .disas_log
= arm_tr_disas_log
,
12276 /* generate intermediate code for basic block 'tb'. */
12277 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
, int max_insns
)
12280 const TranslatorOps
*ops
= &arm_translator_ops
;
12282 if (FIELD_EX32(tb
->flags
, TBFLAG_A32
, THUMB
)) {
12283 ops
= &thumb_translator_ops
;
12285 #ifdef TARGET_AARCH64
12286 if (FIELD_EX32(tb
->flags
, TBFLAG_ANY
, AARCH64_STATE
)) {
12287 ops
= &aarch64_translator_ops
;
12291 translator_loop(ops
, &dc
.base
, cpu
, tb
, max_insns
);
12294 void restore_state_to_opc(CPUARMState
*env
, TranslationBlock
*tb
,
12295 target_ulong
*data
)
12299 env
->condexec_bits
= 0;
12300 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
12302 env
->regs
[15] = data
[0];
12303 env
->condexec_bits
= data
[1];
12304 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;