i.MX: Fix i.MX31 default/reset configuration
[qemu/ar7.git] / hw / net / stellaris_enet.c
blob21a47735d255b0d3b106df08451950e911c3c281
1 /*
2 * Luminary Micro Stellaris Ethernet Controller
4 * Copyright (c) 2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
8 */
9 #include "hw/sysbus.h"
10 #include "net/net.h"
11 #include <zlib.h>
13 //#define DEBUG_STELLARIS_ENET 1
15 #ifdef DEBUG_STELLARIS_ENET
16 #define DPRINTF(fmt, ...) \
17 do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
18 #define BADF(fmt, ...) \
19 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
20 #else
21 #define DPRINTF(fmt, ...) do {} while(0)
22 #define BADF(fmt, ...) \
23 do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
24 #endif
26 #define SE_INT_RX 0x01
27 #define SE_INT_TXER 0x02
28 #define SE_INT_TXEMP 0x04
29 #define SE_INT_FOV 0x08
30 #define SE_INT_RXER 0x10
31 #define SE_INT_MD 0x20
32 #define SE_INT_PHY 0x40
34 #define SE_RCTL_RXEN 0x01
35 #define SE_RCTL_AMUL 0x02
36 #define SE_RCTL_PRMS 0x04
37 #define SE_RCTL_BADCRC 0x08
38 #define SE_RCTL_RSTFIFO 0x10
40 #define SE_TCTL_TXEN 0x01
41 #define SE_TCTL_PADEN 0x02
42 #define SE_TCTL_CRC 0x04
43 #define SE_TCTL_DUPLEX 0x08
45 #define TYPE_STELLARIS_ENET "stellaris_enet"
46 #define STELLARIS_ENET(obj) \
47 OBJECT_CHECK(stellaris_enet_state, (obj), TYPE_STELLARIS_ENET)
49 typedef struct {
50 uint8_t data[2048];
51 uint32_t len;
52 } StellarisEnetRxFrame;
54 typedef struct {
55 SysBusDevice parent_obj;
57 uint32_t ris;
58 uint32_t im;
59 uint32_t rctl;
60 uint32_t tctl;
61 uint32_t thr;
62 uint32_t mctl;
63 uint32_t mdv;
64 uint32_t mtxd;
65 uint32_t mrxd;
66 uint32_t np;
67 uint32_t tx_fifo_len;
68 uint8_t tx_fifo[2048];
69 /* Real hardware has a 2k fifo, which works out to be at most 31 packets.
70 We implement a full 31 packet fifo. */
71 StellarisEnetRxFrame rx[31];
72 uint32_t rx_fifo_offset;
73 uint32_t next_packet;
74 NICState *nic;
75 NICConf conf;
76 qemu_irq irq;
77 MemoryRegion mmio;
78 } stellaris_enet_state;
80 static const VMStateDescription vmstate_rx_frame = {
81 .name = "stellaris_enet/rx_frame",
82 .version_id = 1,
83 .minimum_version_id = 1,
84 .fields = (VMStateField[]) {
85 VMSTATE_UINT8_ARRAY(data, StellarisEnetRxFrame, 2048),
86 VMSTATE_UINT32(len, StellarisEnetRxFrame),
87 VMSTATE_END_OF_LIST()
91 static int stellaris_enet_post_load(void *opaque, int version_id)
93 stellaris_enet_state *s = opaque;
94 int i;
96 /* Sanitize inbound state. Note that next_packet is an index but
97 * np is a size; hence their valid upper bounds differ.
99 if (s->next_packet >= ARRAY_SIZE(s->rx)) {
100 return -1;
103 if (s->np > ARRAY_SIZE(s->rx)) {
104 return -1;
107 for (i = 0; i < ARRAY_SIZE(s->rx); i++) {
108 if (s->rx[i].len > ARRAY_SIZE(s->rx[i].data)) {
109 return -1;
113 if (s->rx_fifo_offset > ARRAY_SIZE(s->rx[0].data) - 4) {
114 return -1;
117 if (s->tx_fifo_len > ARRAY_SIZE(s->tx_fifo)) {
118 return -1;
121 return 0;
124 static const VMStateDescription vmstate_stellaris_enet = {
125 .name = "stellaris_enet",
126 .version_id = 2,
127 .minimum_version_id = 2,
128 .post_load = stellaris_enet_post_load,
129 .fields = (VMStateField[]) {
130 VMSTATE_UINT32(ris, stellaris_enet_state),
131 VMSTATE_UINT32(im, stellaris_enet_state),
132 VMSTATE_UINT32(rctl, stellaris_enet_state),
133 VMSTATE_UINT32(tctl, stellaris_enet_state),
134 VMSTATE_UINT32(thr, stellaris_enet_state),
135 VMSTATE_UINT32(mctl, stellaris_enet_state),
136 VMSTATE_UINT32(mdv, stellaris_enet_state),
137 VMSTATE_UINT32(mtxd, stellaris_enet_state),
138 VMSTATE_UINT32(mrxd, stellaris_enet_state),
139 VMSTATE_UINT32(np, stellaris_enet_state),
140 VMSTATE_UINT32(tx_fifo_len, stellaris_enet_state),
141 VMSTATE_UINT8_ARRAY(tx_fifo, stellaris_enet_state, 2048),
142 VMSTATE_STRUCT_ARRAY(rx, stellaris_enet_state, 31, 1,
143 vmstate_rx_frame, StellarisEnetRxFrame),
144 VMSTATE_UINT32(rx_fifo_offset, stellaris_enet_state),
145 VMSTATE_UINT32(next_packet, stellaris_enet_state),
146 VMSTATE_END_OF_LIST()
150 static void stellaris_enet_update(stellaris_enet_state *s)
152 qemu_set_irq(s->irq, (s->ris & s->im) != 0);
155 /* Return the data length of the packet currently being assembled
156 * in the TX fifo.
158 static inline int stellaris_txpacket_datalen(stellaris_enet_state *s)
160 return s->tx_fifo[0] | (s->tx_fifo[1] << 8);
163 /* Return true if the packet currently in the TX FIFO is complete,
164 * ie the FIFO holds enough bytes for the data length, ethernet header,
165 * payload and optionally CRC.
167 static inline bool stellaris_txpacket_complete(stellaris_enet_state *s)
169 int framelen = stellaris_txpacket_datalen(s);
170 framelen += 16;
171 if (!(s->tctl & SE_TCTL_CRC)) {
172 framelen += 4;
174 /* Cover the corner case of a 2032 byte payload with auto-CRC disabled:
175 * this requires more bytes than will fit in the FIFO. It's not totally
176 * clear how the h/w handles this, but if using threshold-based TX
177 * it will definitely try to transmit something.
179 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo));
180 return s->tx_fifo_len >= framelen;
183 /* Return true if the TX FIFO threshold is enabled and the FIFO
184 * has filled enough to reach it.
186 static inline bool stellaris_tx_thr_reached(stellaris_enet_state *s)
188 return (s->thr < 0x3f &&
189 (s->tx_fifo_len >= 4 * (s->thr * 8 + 1)));
192 /* Send the packet currently in the TX FIFO */
193 static void stellaris_enet_send(stellaris_enet_state *s)
195 int framelen = stellaris_txpacket_datalen(s);
197 /* Ethernet header is in the FIFO but not in the datacount.
198 * We don't implement explicit CRC, so just ignore any
199 * CRC value in the FIFO.
201 framelen += 14;
202 if ((s->tctl & SE_TCTL_PADEN) && framelen < 60) {
203 memset(&s->tx_fifo[framelen + 2], 0, 60 - framelen);
204 framelen = 60;
206 /* This MIN will have no effect unless the FIFO data is corrupt
207 * (eg bad data from an incoming migration); otherwise the check
208 * on the datalen at the start of writing the data into the FIFO
209 * will have caught this. Silently write a corrupt half-packet,
210 * which is what the hardware does in FIFO underrun situations.
212 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo) - 2);
213 qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo + 2, framelen);
214 s->tx_fifo_len = 0;
215 s->ris |= SE_INT_TXEMP;
216 stellaris_enet_update(s);
217 DPRINTF("Done TX\n");
220 /* TODO: Implement MAC address filtering. */
221 static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
223 stellaris_enet_state *s = qemu_get_nic_opaque(nc);
224 int n;
225 uint8_t *p;
226 uint32_t crc;
228 if ((s->rctl & SE_RCTL_RXEN) == 0)
229 return -1;
230 if (s->np >= 31) {
231 return 0;
234 DPRINTF("Received packet len=%zu\n", size);
235 n = s->next_packet + s->np;
236 if (n >= 31)
237 n -= 31;
238 s->np++;
240 s->rx[n].len = size + 6;
241 p = s->rx[n].data;
242 *(p++) = (size + 6);
243 *(p++) = (size + 6) >> 8;
244 memcpy (p, buf, size);
245 p += size;
246 crc = crc32(~0, buf, size);
247 *(p++) = crc;
248 *(p++) = crc >> 8;
249 *(p++) = crc >> 16;
250 *(p++) = crc >> 24;
251 /* Clear the remaining bytes in the last word. */
252 if ((size & 3) != 2) {
253 memset(p, 0, (6 - size) & 3);
256 s->ris |= SE_INT_RX;
257 stellaris_enet_update(s);
259 return size;
262 static int stellaris_enet_can_receive(stellaris_enet_state *s)
264 return (s->np < 31);
267 static uint64_t stellaris_enet_read(void *opaque, hwaddr offset,
268 unsigned size)
270 stellaris_enet_state *s = (stellaris_enet_state *)opaque;
271 uint32_t val;
273 switch (offset) {
274 case 0x00: /* RIS */
275 DPRINTF("IRQ status %02x\n", s->ris);
276 return s->ris;
277 case 0x04: /* IM */
278 return s->im;
279 case 0x08: /* RCTL */
280 return s->rctl;
281 case 0x0c: /* TCTL */
282 return s->tctl;
283 case 0x10: /* DATA */
285 uint8_t *rx_fifo;
287 if (s->np == 0) {
288 BADF("RX underflow\n");
289 return 0;
292 rx_fifo = s->rx[s->next_packet].data + s->rx_fifo_offset;
294 val = rx_fifo[0] | (rx_fifo[1] << 8) | (rx_fifo[2] << 16)
295 | (rx_fifo[3] << 24);
296 s->rx_fifo_offset += 4;
297 if (s->rx_fifo_offset >= s->rx[s->next_packet].len) {
298 s->rx_fifo_offset = 0;
299 s->next_packet++;
300 if (s->next_packet >= 31)
301 s->next_packet = 0;
302 s->np--;
303 DPRINTF("RX done np=%d\n", s->np);
304 if (!s->np && stellaris_enet_can_receive(s)) {
305 qemu_flush_queued_packets(qemu_get_queue(s->nic));
308 return val;
310 case 0x14: /* IA0 */
311 return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
312 | (s->conf.macaddr.a[2] << 16)
313 | ((uint32_t)s->conf.macaddr.a[3] << 24);
314 case 0x18: /* IA1 */
315 return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
316 case 0x1c: /* THR */
317 return s->thr;
318 case 0x20: /* MCTL */
319 return s->mctl;
320 case 0x24: /* MDV */
321 return s->mdv;
322 case 0x28: /* MADD */
323 return 0;
324 case 0x2c: /* MTXD */
325 return s->mtxd;
326 case 0x30: /* MRXD */
327 return s->mrxd;
328 case 0x34: /* NP */
329 return s->np;
330 case 0x38: /* TR */
331 return 0;
332 case 0x3c: /* Undocuented: Timestamp? */
333 return 0;
334 default:
335 hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset);
336 return 0;
340 static void stellaris_enet_write(void *opaque, hwaddr offset,
341 uint64_t value, unsigned size)
343 stellaris_enet_state *s = (stellaris_enet_state *)opaque;
345 switch (offset) {
346 case 0x00: /* IACK */
347 s->ris &= ~value;
348 DPRINTF("IRQ ack %02" PRIx64 "/%02x\n", value, s->ris);
349 stellaris_enet_update(s);
350 /* Clearing TXER also resets the TX fifo. */
351 if (value & SE_INT_TXER) {
352 s->tx_fifo_len = 0;
354 break;
355 case 0x04: /* IM */
356 DPRINTF("IRQ mask %02" PRIx64 "/%02x\n", value, s->ris);
357 s->im = value;
358 stellaris_enet_update(s);
359 break;
360 case 0x08: /* RCTL */
361 s->rctl = value;
362 if (value & SE_RCTL_RSTFIFO) {
363 s->np = 0;
364 s->rx_fifo_offset = 0;
365 stellaris_enet_update(s);
367 break;
368 case 0x0c: /* TCTL */
369 s->tctl = value;
370 break;
371 case 0x10: /* DATA */
372 if (s->tx_fifo_len == 0) {
373 /* The first word is special, it contains the data length */
374 int framelen = value & 0xffff;
375 if (framelen > 2032) {
376 DPRINTF("TX frame too long (%d)\n", framelen);
377 s->ris |= SE_INT_TXER;
378 stellaris_enet_update(s);
379 break;
383 if (s->tx_fifo_len + 4 <= ARRAY_SIZE(s->tx_fifo)) {
384 s->tx_fifo[s->tx_fifo_len++] = value;
385 s->tx_fifo[s->tx_fifo_len++] = value >> 8;
386 s->tx_fifo[s->tx_fifo_len++] = value >> 16;
387 s->tx_fifo[s->tx_fifo_len++] = value >> 24;
390 if (stellaris_tx_thr_reached(s) && stellaris_txpacket_complete(s)) {
391 stellaris_enet_send(s);
393 break;
394 case 0x14: /* IA0 */
395 s->conf.macaddr.a[0] = value;
396 s->conf.macaddr.a[1] = value >> 8;
397 s->conf.macaddr.a[2] = value >> 16;
398 s->conf.macaddr.a[3] = value >> 24;
399 break;
400 case 0x18: /* IA1 */
401 s->conf.macaddr.a[4] = value;
402 s->conf.macaddr.a[5] = value >> 8;
403 break;
404 case 0x1c: /* THR */
405 s->thr = value;
406 break;
407 case 0x20: /* MCTL */
408 s->mctl = value;
409 break;
410 case 0x24: /* MDV */
411 s->mdv = value;
412 break;
413 case 0x28: /* MADD */
414 /* ignored. */
415 break;
416 case 0x2c: /* MTXD */
417 s->mtxd = value & 0xff;
418 break;
419 case 0x38: /* TR */
420 if (value & 1) {
421 stellaris_enet_send(s);
423 break;
424 case 0x30: /* MRXD */
425 case 0x34: /* NP */
426 /* Ignored. */
427 case 0x3c: /* Undocuented: Timestamp? */
428 /* Ignored. */
429 break;
430 default:
431 hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset);
435 static const MemoryRegionOps stellaris_enet_ops = {
436 .read = stellaris_enet_read,
437 .write = stellaris_enet_write,
438 .endianness = DEVICE_NATIVE_ENDIAN,
441 static void stellaris_enet_reset(stellaris_enet_state *s)
443 s->mdv = 0x80;
444 s->rctl = SE_RCTL_BADCRC;
445 s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
446 | SE_INT_TXER | SE_INT_RX;
447 s->thr = 0x3f;
448 s->tx_fifo_len = 0;
451 static NetClientInfo net_stellaris_enet_info = {
452 .type = NET_CLIENT_OPTIONS_KIND_NIC,
453 .size = sizeof(NICState),
454 .receive = stellaris_enet_receive,
457 static int stellaris_enet_init(SysBusDevice *sbd)
459 DeviceState *dev = DEVICE(sbd);
460 stellaris_enet_state *s = STELLARIS_ENET(dev);
462 memory_region_init_io(&s->mmio, OBJECT(s), &stellaris_enet_ops, s,
463 "stellaris_enet", 0x1000);
464 sysbus_init_mmio(sbd, &s->mmio);
465 sysbus_init_irq(sbd, &s->irq);
466 qemu_macaddr_default_if_unset(&s->conf.macaddr);
468 s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf,
469 object_get_typename(OBJECT(dev)), dev->id, s);
470 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
472 stellaris_enet_reset(s);
473 return 0;
476 static Property stellaris_enet_properties[] = {
477 DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf),
478 DEFINE_PROP_END_OF_LIST(),
481 static void stellaris_enet_class_init(ObjectClass *klass, void *data)
483 DeviceClass *dc = DEVICE_CLASS(klass);
484 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
486 k->init = stellaris_enet_init;
487 dc->props = stellaris_enet_properties;
488 dc->vmsd = &vmstate_stellaris_enet;
491 static const TypeInfo stellaris_enet_info = {
492 .name = TYPE_STELLARIS_ENET,
493 .parent = TYPE_SYS_BUS_DEVICE,
494 .instance_size = sizeof(stellaris_enet_state),
495 .class_init = stellaris_enet_class_init,
498 static void stellaris_enet_register_types(void)
500 type_register_static(&stellaris_enet_info);
503 type_init(stellaris_enet_register_types)