hw/net/milkymist-minimac2.c

   1 /*
   2  *  QEMU model of the Milkymist minimac2 block.
   3  *
   4  *  Copyright (c) 2011 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   not available yet
  22  *
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/sysbus.h"
  27 #include "trace.h"
  28 #include "net/net.h"
  29 #include "qemu/error-report.h"
  30
  31 #include <zlib.h>
  32
  33 enum {
  34     R_SETUP = 0,
  35     R_MDIO,
  36     R_STATE0,
  37     R_COUNT0,
  38     R_STATE1,
  39     R_COUNT1,
  40     R_TXCOUNT,
  41     R_MAX
  42 };
  43
  44 enum {
  45     SETUP_PHY_RST = (1<<0),
  46 };
  47
  48 enum {
  49     MDIO_DO  = (1<<0),
  50     MDIO_DI  = (1<<1),
  51     MDIO_OE  = (1<<2),
  52     MDIO_CLK = (1<<3),
  53 };
  54
  55 enum {
  56     STATE_EMPTY   = 0,
  57     STATE_LOADED  = 1,
  58     STATE_PENDING = 2,
  59 };
  60
  61 enum {
  62     MDIO_OP_WRITE = 1,
  63     MDIO_OP_READ  = 2,
  64 };
  65
  66 enum mdio_state {
  67     MDIO_STATE_IDLE,
  68     MDIO_STATE_READING,
  69     MDIO_STATE_WRITING,
  70 };
  71
  72 enum {
  73     R_PHY_ID1  = 2,
  74     R_PHY_ID2  = 3,
  75     R_PHY_MAX  = 32
  76 };
  77
  78 #define MINIMAC2_MTU 1530
  79 #define MINIMAC2_BUFFER_SIZE 2048
  80
  81 struct MilkymistMinimac2MdioState {
  82     int last_clk;
  83     int count;
  84     uint32_t data;
  85     uint16_t data_out;
  86     int state;
  87
  88     uint8_t phy_addr;
  89     uint8_t reg_addr;
  90 };
  91 typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
  92
  93 #define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2"
  94 #define MILKYMIST_MINIMAC2(obj) \
  95     OBJECT_CHECK(MilkymistMinimac2State, (obj), TYPE_MILKYMIST_MINIMAC2)
  96
  97 struct MilkymistMinimac2State {
  98     SysBusDevice parent_obj;
  99
 100     NICState *nic;
 101     NICConf conf;
 102     char *phy_model;
 103     MemoryRegion buffers;
 104     MemoryRegion regs_region;
 105
 106     qemu_irq rx_irq;
 107     qemu_irq tx_irq;
 108
 109     uint32_t regs[R_MAX];
 110
 111     MilkymistMinimac2MdioState mdio;
 112
 113     uint16_t phy_regs[R_PHY_MAX];
 114
 115     uint8_t *rx0_buf;
 116     uint8_t *rx1_buf;
 117     uint8_t *tx_buf;
 118 };
 119 typedef struct MilkymistMinimac2State MilkymistMinimac2State;
 120
 121 static const uint8_t preamble_sfd[] = {
 122         0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
 123 };
 124
 125 static void minimac2_mdio_write_reg(MilkymistMinimac2State *s,
 126         uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
 127 {
 128     trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value);
 129
 130     /* nop */
 131 }
 132
 133 static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
 134         uint8_t phy_addr, uint8_t reg_addr)
 135 {
 136     uint16_t r = s->phy_regs[reg_addr];
 137
 138     trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r);
 139
 140     return r;
 141 }
 142
 143 static void minimac2_update_mdio(MilkymistMinimac2State *s)
 144 {
 145     MilkymistMinimac2MdioState *m = &s->mdio;
 146
 147     /* detect rising clk edge */
 148     if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
 149         /* shift data in */
 150         int bit = ((s->regs[R_MDIO] & MDIO_DO)
 151                    && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
 152         m->data = (m->data << 1) | bit;
 153
 154         /* check for sync */
 155         if (m->data == 0xffffffff) {
 156             m->count = 32;
 157         }
 158
 159         if (m->count == 16) {
 160             uint8_t start = (m->data >> 14) & 0x3;
 161             uint8_t op = (m->data >> 12) & 0x3;
 162             uint8_t ta = (m->data) & 0x3;
 163
 164             if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
 165                 m->state = MDIO_STATE_WRITING;
 166             } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
 167                 m->state = MDIO_STATE_READING;
 168             } else {
 169                 m->state = MDIO_STATE_IDLE;
 170             }
 171
 172             if (m->state != MDIO_STATE_IDLE) {
 173                 m->phy_addr = (m->data >> 7) & 0x1f;
 174                 m->reg_addr = (m->data >> 2) & 0x1f;
 175             }
 176
 177             if (m->state == MDIO_STATE_READING) {
 178                 m->data_out = minimac2_mdio_read_reg(s, m->phy_addr,
 179                         m->reg_addr);
 180             }
 181         }
 182
 183         if (m->count < 16 && m->state == MDIO_STATE_READING) {
 184             int bit = (m->data_out & 0x8000) ? 1 : 0;
 185             m->data_out <<= 1;
 186
 187             if (bit) {
 188                 s->regs[R_MDIO] |= MDIO_DI;
 189             } else {
 190                 s->regs[R_MDIO] &= ~MDIO_DI;
 191             }
 192         }
 193
 194         if (m->count == 0 && m->state) {
 195             if (m->state == MDIO_STATE_WRITING) {
 196                 uint16_t data = m->data & 0xffff;
 197                 minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
 198             }
 199             m->state = MDIO_STATE_IDLE;
 200         }
 201         m->count--;
 202     }
 203
 204     m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
 205 }
 206
 207 static size_t assemble_frame(uint8_t *buf, size_t size,
 208         const uint8_t *payload, size_t payload_size)
 209 {
 210     uint32_t crc;
 211
 212     if (size < payload_size + 12) {
 213         error_report("milkymist_minimac2: received too big ethernet frame");
 214         return 0;
 215     }
 216
 217     /* prepend preamble and sfd */
 218     memcpy(buf, preamble_sfd, 8);
 219
 220     /* now copy the payload */
 221     memcpy(buf + 8, payload, payload_size);
 222
 223     /* pad frame if needed */
 224     if (payload_size < 60) {
 225         memset(buf + payload_size + 8, 0, 60 - payload_size);
 226         payload_size = 60;
 227     }
 228
 229     /* append fcs */
 230     crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
 231     memcpy(buf + payload_size + 8, &crc, 4);
 232
 233     return payload_size + 12;
 234 }
 235
 236 static void minimac2_tx(MilkymistMinimac2State *s)
 237 {
 238     uint32_t txcount = s->regs[R_TXCOUNT];
 239     uint8_t *buf = s->tx_buf;
 240
 241     if (txcount < 64) {
 242         error_report("milkymist_minimac2: ethernet frame too small (%u < %u)",
 243                 txcount, 64);
 244         goto err;
 245     }
 246
 247     if (txcount > MINIMAC2_MTU) {
 248         error_report("milkymist_minimac2: MTU exceeded (%u > %u)",
 249                 txcount, MINIMAC2_MTU);
 250         goto err;
 251     }
 252
 253     if (memcmp(buf, preamble_sfd, 8) != 0) {
 254         error_report("milkymist_minimac2: frame doesn't contain the preamble "
 255                 "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)",
 256                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
 257         goto err;
 258     }
 259
 260     trace_milkymist_minimac2_tx_frame(txcount - 12);
 261
 262     /* send packet, skipping preamble and sfd */
 263     qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12);
 264
 265     s->regs[R_TXCOUNT] = 0;
 266
 267 err:
 268     trace_milkymist_minimac2_pulse_irq_tx();
 269     qemu_irq_pulse(s->tx_irq);
 270 }
 271
 272 static void update_rx_interrupt(MilkymistMinimac2State *s)
 273 {
 274     if (s->regs[R_STATE0] == STATE_PENDING
 275             || s->regs[R_STATE1] == STATE_PENDING) {
 276         trace_milkymist_minimac2_raise_irq_rx();
 277         qemu_irq_raise(s->rx_irq);
 278     } else {
 279         trace_milkymist_minimac2_lower_irq_rx();
 280         qemu_irq_lower(s->rx_irq);
 281     }
 282 }
 283
 284 static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 285 {
 286     MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
 287
 288     uint32_t r_count;
 289     uint32_t r_state;
 290     uint8_t *rx_buf;
 291
 292     size_t frame_size;
 293
 294     trace_milkymist_minimac2_rx_frame(buf, size);
 295
 296     /* choose appropriate slot */
 297     if (s->regs[R_STATE0] == STATE_LOADED) {
 298         r_count = R_COUNT0;
 299         r_state = R_STATE0;
 300         rx_buf = s->rx0_buf;
 301     } else if (s->regs[R_STATE1] == STATE_LOADED) {
 302         r_count = R_COUNT1;
 303         r_state = R_STATE1;
 304         rx_buf = s->rx1_buf;
 305     } else {
 306         return 0;
 307     }
 308
 309     /* assemble frame */
 310     frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size);
 311
 312     if (frame_size == 0) {
 313         return size;
 314     }
 315
 316     trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size);
 317
 318     /* update slot */
 319     s->regs[r_count] = frame_size;
 320     s->regs[r_state] = STATE_PENDING;
 321
 322     update_rx_interrupt(s);
 323
 324     return size;
 325 }
 326
 327 static uint64_t
 328 minimac2_read(void *opaque, hwaddr addr, unsigned size)
 329 {
 330     MilkymistMinimac2State *s = opaque;
 331     uint32_t r = 0;
 332
 333     addr >>= 2;
 334     switch (addr) {
 335     case R_SETUP:
 336     case R_MDIO:
 337     case R_STATE0:
 338     case R_COUNT0:
 339     case R_STATE1:
 340     case R_COUNT1:
 341     case R_TXCOUNT:
 342         r = s->regs[addr];
 343         break;
 344
 345     default:
 346         error_report("milkymist_minimac2: read access to unknown register 0x"
 347                 TARGET_FMT_plx, addr << 2);
 348         break;
 349     }
 350
 351     trace_milkymist_minimac2_memory_read(addr << 2, r);
 352
 353     return r;
 354 }
 355
 356 static int minimac2_can_rx(MilkymistMinimac2State *s)
 357 {
 358     if (s->regs[R_STATE0] == STATE_LOADED) {
 359         return 1;
 360     }
 361     if (s->regs[R_STATE1] == STATE_LOADED) {
 362         return 1;
 363     }
 364
 365     return 0;
 366 }
 367
 368 static void
 369 minimac2_write(void *opaque, hwaddr addr, uint64_t value,
 370                unsigned size)
 371 {
 372     MilkymistMinimac2State *s = opaque;
 373
 374     trace_milkymist_minimac2_memory_write(addr, value);
 375
 376     addr >>= 2;
 377     switch (addr) {
 378     case R_MDIO:
 379     {
 380         /* MDIO_DI is read only */
 381         int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
 382         s->regs[R_MDIO] = value;
 383         if (mdio_di) {
 384             s->regs[R_MDIO] |= mdio_di;
 385         } else {
 386             s->regs[R_MDIO] &= ~mdio_di;
 387         }
 388
 389         minimac2_update_mdio(s);
 390     } break;
 391     case R_TXCOUNT:
 392         s->regs[addr] = value;
 393         if (value > 0) {
 394             minimac2_tx(s);
 395         }
 396         break;
 397     case R_STATE0:
 398     case R_STATE1:
 399         s->regs[addr] = value;
 400         update_rx_interrupt(s);
 401         if (minimac2_can_rx(s)) {
 402             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 403         }
 404         break;
 405     case R_SETUP:
 406     case R_COUNT0:
 407     case R_COUNT1:
 408         s->regs[addr] = value;
 409         break;
 410
 411     default:
 412         error_report("milkymist_minimac2: write access to unknown register 0x"
 413                 TARGET_FMT_plx, addr << 2);
 414         break;
 415     }
 416 }
 417
 418 static const MemoryRegionOps minimac2_ops = {
 419     .read = minimac2_read,
 420     .write = minimac2_write,
 421     .valid = {
 422         .min_access_size = 4,
 423         .max_access_size = 4,
 424     },
 425     .endianness = DEVICE_NATIVE_ENDIAN,
 426 };
 427
 428 static void milkymist_minimac2_reset(DeviceState *d)
 429 {
 430     MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d);
 431     int i;
 432
 433     for (i = 0; i < R_MAX; i++) {
 434         s->regs[i] = 0;
 435     }
 436     for (i = 0; i < R_PHY_MAX; i++) {
 437         s->phy_regs[i] = 0;
 438     }
 439
 440     /* defaults */
 441     s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */
 442     s->phy_regs[R_PHY_ID2] = 0x161a;
 443 }
 444
 445 static NetClientInfo net_milkymist_minimac2_info = {
 446     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 447     .size = sizeof(NICState),
 448     .receive = minimac2_rx,
 449 };
 450
 451 static int milkymist_minimac2_init(SysBusDevice *sbd)
 452 {
 453     DeviceState *dev = DEVICE(sbd);
 454     MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev);
 455     size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
 456
 457     sysbus_init_irq(sbd, &s->rx_irq);
 458     sysbus_init_irq(sbd, &s->tx_irq);
 459
 460     memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s,
 461                           "milkymist-minimac2", R_MAX * 4);
 462     sysbus_init_mmio(sbd, &s->regs_region);
 463
 464     /* register buffers memory */
 465     memory_region_init_ram(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers",
 466                            buffers_size, &error_fatal);
 467     vmstate_register_ram_global(&s->buffers);
 468     s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
 469     s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
 470     s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
 471
 472     sysbus_init_mmio(sbd, &s->buffers);
 473
 474     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 475     s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
 476                           object_get_typename(OBJECT(dev)), dev->id, s);
 477     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 478
 479     return 0;
 480 }
 481
 482 static const VMStateDescription vmstate_milkymist_minimac2_mdio = {
 483     .name = "milkymist-minimac2-mdio",
 484     .version_id = 1,
 485     .minimum_version_id = 1,
 486     .fields = (VMStateField[]) {
 487         VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState),
 488         VMSTATE_INT32(count, MilkymistMinimac2MdioState),
 489         VMSTATE_UINT32(data, MilkymistMinimac2MdioState),
 490         VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState),
 491         VMSTATE_INT32(state, MilkymistMinimac2MdioState),
 492         VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState),
 493         VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState),
 494         VMSTATE_END_OF_LIST()
 495     }
 496 };
 497
 498 static const VMStateDescription vmstate_milkymist_minimac2 = {
 499     .name = "milkymist-minimac2",
 500     .version_id = 1,
 501     .minimum_version_id = 1,
 502     .fields = (VMStateField[]) {
 503         VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX),
 504         VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX),
 505         VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
 506                 vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState),
 507         VMSTATE_END_OF_LIST()
 508     }
 509 };
 510
 511 static Property milkymist_minimac2_properties[] = {
 512     DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf),
 513     DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
 514     DEFINE_PROP_END_OF_LIST(),
 515 };
 516
 517 static void milkymist_minimac2_class_init(ObjectClass *klass, void *data)
 518 {
 519     DeviceClass *dc = DEVICE_CLASS(klass);
 520     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 521
 522     k->init = milkymist_minimac2_init;
 523     dc->reset = milkymist_minimac2_reset;
 524     dc->vmsd = &vmstate_milkymist_minimac2;
 525     dc->props = milkymist_minimac2_properties;
 526 }
 527
 528 static const TypeInfo milkymist_minimac2_info = {
 529     .name          = TYPE_MILKYMIST_MINIMAC2,
 530     .parent        = TYPE_SYS_BUS_DEVICE,
 531     .instance_size = sizeof(MilkymistMinimac2State),
 532     .class_init    = milkymist_minimac2_class_init,
 533 };
 534
 535 static void milkymist_minimac2_register_types(void)
 536 {
 537     type_register_static(&milkymist_minimac2_info);
 538 }
 539
 540 type_init(milkymist_minimac2_register_types)