include/hw/dma/pl080.h

   1 /*
   2  * ARM PrimeCell PL080/PL081 DMA controller
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Copyright (c) 2018 Linaro Limited
   6  * Written by Paul Brook, Peter Maydell
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 or
  10  * (at your option) any later version.
  11  */
  12
  13 /* This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
  14  * The PL080 TRM is:
  15  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf
  16  * and the PL081 TRM is:
  17  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf
  18  *
  19  * QEMU interface:
  20  * + sysbus IRQ 0: DMACINTR combined interrupt line
  21  * + sysbus IRQ 1: DMACINTERR error interrupt request
  22  * + sysbus IRQ 2: DMACINTTC count interrupt request
  23  * + sysbus MMIO region 0: MemoryRegion for the device's registers
  24  * + QOM property "downstream": MemoryRegion defining where DMA
  25  *   bus master transactions are made
  26  */
  27
  28 #ifndef HW_DMA_PL080_H
  29 #define HW_DMA_PL080_H
  30
  31 #include "hw/sysbus.h"
  32
  33 #define PL080_MAX_CHANNELS 8
  34
  35 typedef struct {
  36     uint32_t src;
  37     uint32_t dest;
  38     uint32_t lli;
  39     uint32_t ctrl;
  40     uint32_t conf;
  41 } pl080_channel;
  42
  43 #define TYPE_PL080 "pl080"
  44 #define TYPE_PL081 "pl081"
  45 #define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
  46
  47 typedef struct PL080State {
  48     SysBusDevice parent_obj;
  49
  50     MemoryRegion iomem;
  51     uint8_t tc_int;
  52     uint8_t tc_mask;
  53     uint8_t err_int;
  54     uint8_t err_mask;
  55     uint32_t conf;
  56     uint32_t sync;
  57     uint32_t req_single;
  58     uint32_t req_burst;
  59     pl080_channel chan[PL080_MAX_CHANNELS];
  60     int nchannels;
  61     /* Flag to avoid recursive DMA invocations.  */
  62     int running;
  63     qemu_irq irq;
  64     qemu_irq interr;
  65     qemu_irq inttc;
  66
  67     MemoryRegion *downstream;
  68     AddressSpace downstream_as;
  69 } PL080State;
  70
  71 #endif