hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "pci.h"
  21 #include "qemu-timer.h"
  22 #include "sysemu.h"
  23 #include "i2c.h"
  24 #include "smbus.h"
  25 #include "kvm.h"
  26
  27 //#define DEBUG
  28
  29 /* i82731AB (PIIX4) compatible power management function */
  30 #define PM_FREQ 3579545
  31
  32 #define ACPI_DBG_IO_ADDR  0xb044
  33
  34 typedef struct PIIX4PMState {
  35     PCIDevice dev;
  36     uint16_t pmsts;
  37     uint16_t pmen;
  38     uint16_t pmcntrl;
  39     uint8_t apmc;
  40     uint8_t apms;
  41     QEMUTimer *tmr_timer;
  42     int64_t tmr_overflow_time;
  43     i2c_bus *smbus;
  44     uint8_t smb_stat;
  45     uint8_t smb_ctl;
  46     uint8_t smb_cmd;
  47     uint8_t smb_addr;
  48     uint8_t smb_data0;
  49     uint8_t smb_data1;
  50     uint8_t smb_data[32];
  51     uint8_t smb_index;
  52     qemu_irq irq;
  53 } PIIX4PMState;
  54
  55 #define RSM_STS (1 << 15)
  56 #define PWRBTN_STS (1 << 8)
  57 #define RTC_EN (1 << 10)
  58 #define PWRBTN_EN (1 << 8)
  59 #define GBL_EN (1 << 5)
  60 #define TMROF_EN (1 << 0)
  61
  62 #define SCI_EN (1 << 0)
  63
  64 #define SUS_EN (1 << 13)
  65
  66 #define ACPI_ENABLE 0xf1
  67 #define ACPI_DISABLE 0xf0
  68
  69 #define SMBHSTSTS 0x00
  70 #define SMBHSTCNT 0x02
  71 #define SMBHSTCMD 0x03
  72 #define SMBHSTADD 0x04
  73 #define SMBHSTDAT0 0x05
  74 #define SMBHSTDAT1 0x06
  75 #define SMBBLKDAT 0x07
  76
  77 static PIIX4PMState *pm_state;
  78
  79 static uint32_t get_pmtmr(PIIX4PMState *s)
  80 {
  81     uint32_t d;
  82     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
  83     return d & 0xffffff;
  84 }
  85
  86 static int get_pmsts(PIIX4PMState *s)
  87 {
  88     int64_t d;
  89     int pmsts;
  90     pmsts = s->pmsts;
  91     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
  92     if (d >= s->tmr_overflow_time)
  93         s->pmsts |= TMROF_EN;
  94     return s->pmsts;
  95 }
  96
  97 static void pm_update_sci(PIIX4PMState *s)
  98 {
  99     int sci_level, pmsts;
 100     int64_t expire_time;
 101
 102     pmsts = get_pmsts(s);
 103     sci_level = (((pmsts & s->pmen) &
 104                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 105     qemu_set_irq(s->irq, sci_level);
 106     /* schedule a timer interruption if needed */
 107     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 108         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_FREQ);
 109         qemu_mod_timer(s->tmr_timer, expire_time);
 110     } else {
 111         qemu_del_timer(s->tmr_timer);
 112     }
 113 }
 114
 115 static void pm_tmr_timer(void *opaque)
 116 {
 117     PIIX4PMState *s = opaque;
 118     pm_update_sci(s);
 119 }
 120
 121 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 122 {
 123     PIIX4PMState *s = opaque;
 124     addr &= 0x3f;
 125     switch(addr) {
 126     case 0x00:
 127         {
 128             int64_t d;
 129             int pmsts;
 130             pmsts = get_pmsts(s);
 131             if (pmsts & val & TMROF_EN) {
 132                 /* if TMRSTS is reset, then compute the new overflow time */
 133                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ,
 134                              get_ticks_per_sec());
 135                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 136             }
 137             s->pmsts &= ~val;
 138             pm_update_sci(s);
 139         }
 140         break;
 141     case 0x02:
 142         s->pmen = val;
 143         pm_update_sci(s);
 144         break;
 145     case 0x04:
 146         {
 147             int sus_typ;
 148             s->pmcntrl = val & ~(SUS_EN);
 149             if (val & SUS_EN) {
 150                 /* change suspend type */
 151                 sus_typ = (val >> 10) & 7;
 152                 switch(sus_typ) {
 153                 case 0: /* soft power off */
 154                     qemu_system_shutdown_request();
 155                     break;
 156                 case 1:
 157                     /* RSM_STS should be set on resume. Pretend that resume
 158                        was caused by power button */
 159                     s->pmsts |= (RSM_STS | PWRBTN_STS);
 160                     qemu_system_reset_request();
 161 #if defined(TARGET_I386)
 162                     cmos_set_s3_resume();
 163 #endif
 164                 default:
 165                     break;
 166                 }
 167             }
 168         }
 169         break;
 170     default:
 171         break;
 172     }
 173 #ifdef DEBUG
 174     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 175 #endif
 176 }
 177
 178 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 179 {
 180     PIIX4PMState *s = opaque;
 181     uint32_t val;
 182
 183     addr &= 0x3f;
 184     switch(addr) {
 185     case 0x00:
 186         val = get_pmsts(s);
 187         break;
 188     case 0x02:
 189         val = s->pmen;
 190         break;
 191     case 0x04:
 192         val = s->pmcntrl;
 193         break;
 194     default:
 195         val = 0;
 196         break;
 197     }
 198 #ifdef DEBUG
 199     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 200 #endif
 201     return val;
 202 }
 203
 204 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 205 {
 206     //    PIIX4PMState *s = opaque;
 207     addr &= 0x3f;
 208 #ifdef DEBUG
 209     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 210 #endif
 211 }
 212
 213 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 214 {
 215     PIIX4PMState *s = opaque;
 216     uint32_t val;
 217
 218     addr &= 0x3f;
 219     switch(addr) {
 220     case 0x08:
 221         val = get_pmtmr(s);
 222         break;
 223     default:
 224         val = 0;
 225         break;
 226     }
 227 #ifdef DEBUG
 228     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 229 #endif
 230     return val;
 231 }
 232
 233 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 234 {
 235     PIIX4PMState *s = opaque;
 236     addr &= 1;
 237 #ifdef DEBUG
 238     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 239 #endif
 240     if (addr == 0) {
 241         s->apmc = val;
 242
 243         /* ACPI specs 3.0, 4.7.2.5 */
 244         if (val == ACPI_ENABLE) {
 245             s->pmcntrl |= SCI_EN;
 246         } else if (val == ACPI_DISABLE) {
 247             s->pmcntrl &= ~SCI_EN;
 248         }
 249
 250         if (s->dev.config[0x5b] & (1 << 1)) {
 251             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 252         }
 253     } else {
 254         s->apms = val;
 255     }
 256 }
 257
 258 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 259 {
 260     PIIX4PMState *s = opaque;
 261     uint32_t val;
 262
 263     addr &= 1;
 264     if (addr == 0) {
 265         val = s->apmc;
 266     } else {
 267         val = s->apms;
 268     }
 269 #ifdef DEBUG
 270     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 271 #endif
 272     return val;
 273 }
 274
 275 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 276 {
 277 #if defined(DEBUG)
 278     printf("ACPI: DBG: 0x%08x\n", val);
 279 #endif
 280 }
 281
 282 static void smb_transaction(PIIX4PMState *s)
 283 {
 284     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 285     uint8_t read = s->smb_addr & 0x01;
 286     uint8_t cmd = s->smb_cmd;
 287     uint8_t addr = s->smb_addr >> 1;
 288     i2c_bus *bus = s->smbus;
 289
 290 #ifdef DEBUG
 291     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 292 #endif
 293     switch(prot) {
 294     case 0x0:
 295         smbus_quick_command(bus, addr, read);
 296         break;
 297     case 0x1:
 298         if (read) {
 299             s->smb_data0 = smbus_receive_byte(bus, addr);
 300         } else {
 301             smbus_send_byte(bus, addr, cmd);
 302         }
 303         break;
 304     case 0x2:
 305         if (read) {
 306             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 307         } else {
 308             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 309         }
 310         break;
 311     case 0x3:
 312         if (read) {
 313             uint16_t val;
 314             val = smbus_read_word(bus, addr, cmd);
 315             s->smb_data0 = val;
 316             s->smb_data1 = val >> 8;
 317         } else {
 318             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 319         }
 320         break;
 321     case 0x5:
 322         if (read) {
 323             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 324         } else {
 325             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 326         }
 327         break;
 328     default:
 329         goto error;
 330     }
 331     return;
 332
 333   error:
 334     s->smb_stat |= 0x04;
 335 }
 336
 337 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 338 {
 339     PIIX4PMState *s = opaque;
 340     addr &= 0x3f;
 341 #ifdef DEBUG
 342     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 343 #endif
 344     switch(addr) {
 345     case SMBHSTSTS:
 346         s->smb_stat = 0;
 347         s->smb_index = 0;
 348         break;
 349     case SMBHSTCNT:
 350         s->smb_ctl = val;
 351         if (val & 0x40)
 352             smb_transaction(s);
 353         break;
 354     case SMBHSTCMD:
 355         s->smb_cmd = val;
 356         break;
 357     case SMBHSTADD:
 358         s->smb_addr = val;
 359         break;
 360     case SMBHSTDAT0:
 361         s->smb_data0 = val;
 362         break;
 363     case SMBHSTDAT1:
 364         s->smb_data1 = val;
 365         break;
 366     case SMBBLKDAT:
 367         s->smb_data[s->smb_index++] = val;
 368         if (s->smb_index > 31)
 369             s->smb_index = 0;
 370         break;
 371     default:
 372         break;
 373     }
 374 }
 375
 376 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 377 {
 378     PIIX4PMState *s = opaque;
 379     uint32_t val;
 380
 381     addr &= 0x3f;
 382     switch(addr) {
 383     case SMBHSTSTS:
 384         val = s->smb_stat;
 385         break;
 386     case SMBHSTCNT:
 387         s->smb_index = 0;
 388         val = s->smb_ctl & 0x1f;
 389         break;
 390     case SMBHSTCMD:
 391         val = s->smb_cmd;
 392         break;
 393     case SMBHSTADD:
 394         val = s->smb_addr;
 395         break;
 396     case SMBHSTDAT0:
 397         val = s->smb_data0;
 398         break;
 399     case SMBHSTDAT1:
 400         val = s->smb_data1;
 401         break;
 402     case SMBBLKDAT:
 403         val = s->smb_data[s->smb_index++];
 404         if (s->smb_index > 31)
 405             s->smb_index = 0;
 406         break;
 407     default:
 408         val = 0;
 409         break;
 410     }
 411 #ifdef DEBUG
 412     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 413 #endif
 414     return val;
 415 }
 416
 417 static void pm_io_space_update(PIIX4PMState *s)
 418 {
 419     uint32_t pm_io_base;
 420
 421     if (s->dev.config[0x80] & 1) {
 422         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 423         pm_io_base &= 0xffc0;
 424
 425         /* XXX: need to improve memory and ioport allocation */
 426 #if defined(DEBUG)
 427         printf("PM: mapping to 0x%x\n", pm_io_base);
 428 #endif
 429         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 430         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 431         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 432         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 433     }
 434 }
 435
 436 static void pm_write_config(PCIDevice *d,
 437                             uint32_t address, uint32_t val, int len)
 438 {
 439     pci_default_write_config(d, address, val, len);
 440     if (range_covers_byte(address, len, 0x80))
 441         pm_io_space_update((PIIX4PMState *)d);
 442 }
 443
 444 static int vmstate_acpi_post_load(void *opaque, int version_id)
 445 {
 446     PIIX4PMState *s = opaque;
 447
 448     pm_io_space_update(s);
 449     return 0;
 450 }
 451
 452 static const VMStateDescription vmstate_acpi = {
 453     .name = "piix4_pm",
 454     .version_id = 1,
 455     .minimum_version_id = 1,
 456     .minimum_version_id_old = 1,
 457     .post_load = vmstate_acpi_post_load,
 458     .fields      = (VMStateField []) {
 459         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 460         VMSTATE_UINT16(pmsts, PIIX4PMState),
 461         VMSTATE_UINT16(pmen, PIIX4PMState),
 462         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 463         VMSTATE_UINT8(apmc, PIIX4PMState),
 464         VMSTATE_UINT8(apms, PIIX4PMState),
 465         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 466         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 467         VMSTATE_END_OF_LIST()
 468     }
 469 };
 470
 471 static void piix4_reset(void *opaque)
 472 {
 473     PIIX4PMState *s = opaque;
 474     uint8_t *pci_conf = s->dev.config;
 475
 476     pci_conf[0x58] = 0;
 477     pci_conf[0x59] = 0;
 478     pci_conf[0x5a] = 0;
 479     pci_conf[0x5b] = 0;
 480
 481     if (kvm_enabled()) {
 482         /* Mark SMM as already inited (until KVM supports SMM). */
 483         pci_conf[0x5B] = 0x02;
 484     }
 485 }
 486
 487 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 488 {
 489 #if defined(TARGET_I386)
 490     PIIX4PMState *s = opaque;
 491
 492     if (!s) {
 493         qemu_system_shutdown_request();
 494     } else if (s->pmen & PWRBTN_EN) {
 495         s->pmsts |= PWRBTN_EN;
 496         pm_update_sci(s);
 497     }
 498 #endif
 499 }
 500
 501 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 502                        qemu_irq sci_irq)
 503 {
 504     PIIX4PMState *s;
 505     uint8_t *pci_conf;
 506
 507     s = (PIIX4PMState *)pci_register_device(bus,
 508                                          "PM", sizeof(PIIX4PMState),
 509                                          devfn, NULL, pm_write_config);
 510     pm_state = s;
 511     pci_conf = s->dev.config;
 512     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 513     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 514     pci_conf[0x06] = 0x80;
 515     pci_conf[0x07] = 0x02;
 516     pci_conf[0x08] = 0x03; // revision number
 517     pci_conf[0x09] = 0x00;
 518     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 519     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 520     pci_conf[0x3d] = 0x01; // interrupt pin 1
 521
 522     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 523
 524     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 525     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 526
 527     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 528
 529     if (kvm_enabled()) {
 530         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 531          * support SMM mode. */
 532         pci_conf[0x5B] = 0x02;
 533     }
 534
 535     /* XXX: which specification is used ? The i82731AB has different
 536        mappings */
 537     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 538     pci_conf[0x63] = 0x60;
 539     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 540         (serial_hds[1] != NULL ? 0x90 : 0);
 541
 542     pci_conf[0x90] = smb_io_base | 1;
 543     pci_conf[0x91] = smb_io_base >> 8;
 544     pci_conf[0xd2] = 0x09;
 545     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 546     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 547
 548     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 549
 550     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 551
 552     vmstate_register(0, &vmstate_acpi, s);
 553
 554     s->smbus = i2c_init_bus(NULL, "i2c");
 555     s->irq = sci_irq;
 556     qemu_register_reset(piix4_reset, s);
 557
 558     return s->smbus;
 559 }
 560
 561 #define GPE_BASE 0xafe0
 562 #define PCI_BASE 0xae00
 563 #define PCI_EJ_BASE 0xae08
 564
 565 struct gpe_regs {
 566     uint16_t sts; /* status */
 567     uint16_t en;  /* enabled */
 568 };
 569
 570 struct pci_status {
 571     uint32_t up;
 572     uint32_t down;
 573 };
 574
 575 static struct gpe_regs gpe;
 576 static struct pci_status pci0_status;
 577
 578 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 579 {
 580     if (addr & 1)
 581         return (val >> 8) & 0xff;
 582     return val & 0xff;
 583 }
 584
 585 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 586 {
 587     uint32_t val = 0;
 588     struct gpe_regs *g = opaque;
 589     switch (addr) {
 590         case GPE_BASE:
 591         case GPE_BASE + 1:
 592             val = gpe_read_val(g->sts, addr);
 593             break;
 594         case GPE_BASE + 2:
 595         case GPE_BASE + 3:
 596             val = gpe_read_val(g->en, addr);
 597             break;
 598         default:
 599             break;
 600     }
 601
 602 #if defined(DEBUG)
 603     printf("gpe read %x == %x\n", addr, val);
 604 #endif
 605     return val;
 606 }
 607
 608 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 609 {
 610     if (addr & 1)
 611         *cur = (*cur & 0xff) | (val << 8);
 612     else
 613         *cur = (*cur & 0xff00) | (val & 0xff);
 614 }
 615
 616 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 617 {
 618     uint16_t x1, x0 = val & 0xff;
 619     int shift = (addr & 1) ? 8 : 0;
 620
 621     x1 = (*cur >> shift) & 0xff;
 622
 623     x1 = x1 & ~x0;
 624
 625     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 626 }
 627
 628 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 629 {
 630     struct gpe_regs *g = opaque;
 631     switch (addr) {
 632         case GPE_BASE:
 633         case GPE_BASE + 1:
 634             gpe_reset_val(&g->sts, addr, val);
 635             break;
 636         case GPE_BASE + 2:
 637         case GPE_BASE + 3:
 638             gpe_write_val(&g->en, addr, val);
 639             break;
 640         default:
 641             break;
 642    }
 643
 644 #if defined(DEBUG)
 645     printf("gpe write %x <== %d\n", addr, val);
 646 #endif
 647 }
 648
 649 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 650 {
 651     uint32_t val = 0;
 652     struct pci_status *g = opaque;
 653     switch (addr) {
 654         case PCI_BASE:
 655             val = g->up;
 656             break;
 657         case PCI_BASE + 4:
 658             val = g->down;
 659             break;
 660         default:
 661             break;
 662     }
 663
 664 #if defined(DEBUG)
 665     printf("pcihotplug read %x == %x\n", addr, val);
 666 #endif
 667     return val;
 668 }
 669
 670 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 671 {
 672     struct pci_status *g = opaque;
 673     switch (addr) {
 674         case PCI_BASE:
 675             g->up = val;
 676             break;
 677         case PCI_BASE + 4:
 678             g->down = val;
 679             break;
 680    }
 681
 682 #if defined(DEBUG)
 683     printf("pcihotplug write %x <== %d\n", addr, val);
 684 #endif
 685 }
 686
 687 static uint32_t pciej_read(void *opaque, uint32_t addr)
 688 {
 689 #if defined(DEBUG)
 690     printf("pciej read %x\n", addr);
 691 #endif
 692     return 0;
 693 }
 694
 695 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 696 {
 697     BusState *bus = opaque;
 698     DeviceState *qdev, *next;
 699     PCIDevice *dev;
 700     int slot = ffs(val) - 1;
 701
 702     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 703         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 704         if (PCI_SLOT(dev->devfn) == slot) {
 705             qdev_free(qdev);
 706         }
 707     }
 708
 709
 710 #if defined(DEBUG)
 711     printf("pciej write %x <== %d\n", addr, val);
 712 #endif
 713 }
 714
 715 static int piix4_device_hotplug(PCIDevice *dev, int state);
 716
 717 void piix4_acpi_system_hot_add_init(PCIBus *bus)
 718 {
 719     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 720     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 721
 722     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 723     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 724
 725     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 726     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 727
 728     pci_bus_hotplug(bus, piix4_device_hotplug);
 729 }
 730
 731 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 732 {
 733     g->sts |= 2;
 734     p->up |= (1 << slot);
 735 }
 736
 737 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 738 {
 739     g->sts |= 2;
 740     p->down |= (1 << slot);
 741 }
 742
 743 static int piix4_device_hotplug(PCIDevice *dev, int state)
 744 {
 745     int slot = PCI_SLOT(dev->devfn);
 746
 747     pci0_status.up = 0;
 748     pci0_status.down = 0;
 749     if (state)
 750         enable_device(&pci0_status, &gpe, slot);
 751     else
 752         disable_device(&pci0_status, &gpe, slot);
 753     if (gpe.en & 2) {
 754         qemu_set_irq(pm_state->irq, 1);
 755         qemu_set_irq(pm_state->irq, 0);
 756     }
 757     return 0;
 758 }
 759
 760 struct acpi_table_header
 761 {
 762     char signature [4];    /* ACPI signature (4 ASCII characters) */
 763     uint32_t length;          /* Length of table, in bytes, including header */
 764     uint8_t revision;         /* ACPI Specification minor version # */
 765     uint8_t checksum;         /* To make sum of entire table == 0 */
 766     char oem_id [6];       /* OEM identification */
 767     char oem_table_id [8]; /* OEM table identification */
 768     uint32_t oem_revision;    /* OEM revision number */
 769     char asl_compiler_id [4]; /* ASL compiler vendor ID */
 770     uint32_t asl_compiler_revision; /* ASL compiler revision number */
 771 } __attribute__((packed));
 772
 773 char *acpi_tables;
 774 size_t acpi_tables_len;
 775
 776 static int acpi_checksum(const uint8_t *data, int len)
 777 {
 778     int sum, i;
 779     sum = 0;
 780     for(i = 0; i < len; i++)
 781         sum += data[i];
 782     return (-sum) & 0xff;
 783 }
 784
 785 int acpi_table_add(const char *t)
 786 {
 787     static const char *dfl_id = "QEMUQEMU";
 788     char buf[1024], *p, *f;
 789     struct acpi_table_header acpi_hdr;
 790     unsigned long val;
 791     size_t off;
 792
 793     memset(&acpi_hdr, 0, sizeof(acpi_hdr));
 794
 795     if (get_param_value(buf, sizeof(buf), "sig", t)) {
 796         strncpy(acpi_hdr.signature, buf, 4);
 797     } else {
 798         strncpy(acpi_hdr.signature, dfl_id, 4);
 799     }
 800     if (get_param_value(buf, sizeof(buf), "rev", t)) {
 801         val = strtoul(buf, &p, 10);
 802         if (val > 255 || *p != '\0')
 803             goto out;
 804     } else {
 805         val = 1;
 806     }
 807     acpi_hdr.revision = (int8_t)val;
 808
 809     if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
 810         strncpy(acpi_hdr.oem_id, buf, 6);
 811     } else {
 812         strncpy(acpi_hdr.oem_id, dfl_id, 6);
 813     }
 814
 815     if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
 816         strncpy(acpi_hdr.oem_table_id, buf, 8);
 817     } else {
 818         strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
 819     }
 820
 821     if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
 822         val = strtol(buf, &p, 10);
 823         if(*p != '\0')
 824             goto out;
 825     } else {
 826         val = 1;
 827     }
 828     acpi_hdr.oem_revision = cpu_to_le32(val);
 829
 830     if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
 831         strncpy(acpi_hdr.asl_compiler_id, buf, 4);
 832     } else {
 833         strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
 834     }
 835
 836     if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
 837         val = strtol(buf, &p, 10);
 838         if(*p != '\0')
 839             goto out;
 840     } else {
 841         val = 1;
 842     }
 843     acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
 844
 845     if (!get_param_value(buf, sizeof(buf), "data", t)) {
 846          buf[0] = '\0';
 847     }
 848
 849     acpi_hdr.length = sizeof(acpi_hdr);
 850
 851     f = buf;
 852     while (buf[0]) {
 853         struct stat s;
 854         char *n = strchr(f, ':');
 855         if (n)
 856             *n = '\0';
 857         if(stat(f, &s) < 0) {
 858             fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
 859             goto out;
 860         }
 861         acpi_hdr.length += s.st_size;
 862         if (!n)
 863             break;
 864         *n = ':';
 865         f = n + 1;
 866     }
 867
 868     if (!acpi_tables) {
 869         acpi_tables_len = sizeof(uint16_t);
 870         acpi_tables = qemu_mallocz(acpi_tables_len);
 871     }
 872     p = acpi_tables + acpi_tables_len;
 873     acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
 874     acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len);
 875
 876     acpi_hdr.length = cpu_to_le32(acpi_hdr.length);
 877     *(uint16_t*)p = acpi_hdr.length;
 878     p += sizeof(uint16_t);
 879     memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
 880     off = sizeof(acpi_hdr);
 881
 882     f = buf;
 883     while (buf[0]) {
 884         struct stat s;
 885         int fd;
 886         char *n = strchr(f, ':');
 887         if (n)
 888             *n = '\0';
 889         fd = open(f, O_RDONLY);
 890
 891         if(fd < 0)
 892             goto out;
 893         if(fstat(fd, &s) < 0) {
 894             close(fd);
 895             goto out;
 896         }
 897
 898         do {
 899             int r;
 900             r = read(fd, p + off, s.st_size);
 901             if (r > 0) {
 902                 off += r;
 903                 s.st_size -= r;
 904             } else if ((r < 0 && errno != EINTR) || r == 0) {
 905                 close(fd);
 906                 goto out;
 907             }
 908         } while(s.st_size);
 909
 910         close(fd);
 911         if (!n)
 912             break;
 913         f = n + 1;
 914     }
 915
 916     ((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
 917     /* increase number of tables */
 918     (*(uint16_t*)acpi_tables) =
 919             cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
 920     return 0;
 921 out:
 922     if (acpi_tables) {
 923         qemu_free(acpi_tables);
 924         acpi_tables = NULL;
 925     }
 926     return -1;
 927 }