target/mips/cp0_helper.c

   1 /*
   2  *  Helpers for emulation of CP0-related MIPS instructions.
   3  *
   4  *  Copyright (C) 2004-2005  Jocelyn Mayer
   5  *  Copyright (C) 2020  Wave Computing, Inc.
   6  *  Copyright (C) 2020  Aleksandar Markovic <amarkovic@wavecomp.com>
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  *
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu/main-loop.h"
  25 #include "cpu.h"
  26 #include "internal.h"
  27 #include "qemu/host-utils.h"
  28 #include "exec/helper-proto.h"
  29 #include "exec/exec-all.h"
  30 #include "exec/cpu_ldst.h"
  31 #include "exec/memop.h"
  32 #include "sysemu/kvm.h"
  33
  34
  35 #ifndef CONFIG_USER_ONLY
  36 /* SMP helpers.  */
  37 static bool mips_vpe_is_wfi(MIPSCPU *c)
  38 {
  39     CPUState *cpu = CPU(c);
  40     CPUMIPSState *env = &c->env;
  41
  42     /*
  43      * If the VPE is halted but otherwise active, it means it's waiting for
  44      * an interrupt.\
  45      */
  46     return cpu->halted && mips_vpe_active(env);
  47 }
  48
  49 static bool mips_vp_is_wfi(MIPSCPU *c)
  50 {
  51     CPUState *cpu = CPU(c);
  52     CPUMIPSState *env = &c->env;
  53
  54     return cpu->halted && mips_vp_active(env);
  55 }
  56
  57 static inline void mips_vpe_wake(MIPSCPU *c)
  58 {
  59     /*
  60      * Don't set ->halted = 0 directly, let it be done via cpu_has_work
  61      * because there might be other conditions that state that c should
  62      * be sleeping.
  63      */
  64     qemu_mutex_lock_iothread();
  65     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
  66     qemu_mutex_unlock_iothread();
  67 }
  68
  69 static inline void mips_vpe_sleep(MIPSCPU *cpu)
  70 {
  71     CPUState *cs = CPU(cpu);
  72
  73     /*
  74      * The VPE was shut off, really go to bed.
  75      * Reset any old _WAKE requests.
  76      */
  77     cs->halted = 1;
  78     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
  79 }
  80
  81 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
  82 {
  83     CPUMIPSState *c = &cpu->env;
  84
  85     /* FIXME: TC reschedule.  */
  86     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
  87         mips_vpe_wake(cpu);
  88     }
  89 }
  90
  91 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
  92 {
  93     CPUMIPSState *c = &cpu->env;
  94
  95     /* FIXME: TC reschedule.  */
  96     if (!mips_vpe_active(c)) {
  97         mips_vpe_sleep(cpu);
  98     }
  99 }
 100
 101 /**
 102  * mips_cpu_map_tc:
 103  * @env: CPU from which mapping is performed.
 104  * @tc: Should point to an int with the value of the global TC index.
 105  *
 106  * This function will transform @tc into a local index within the
 107  * returned #CPUMIPSState.
 108  */
 109
 110 /*
 111  * FIXME: This code assumes that all VPEs have the same number of TCs,
 112  *        which depends on runtime setup. Can probably be fixed by
 113  *        walking the list of CPUMIPSStates.
 114  */
 115 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 116 {
 117     MIPSCPU *cpu;
 118     CPUState *cs;
 119     CPUState *other_cs;
 120     int vpe_idx;
 121     int tc_idx = *tc;
 122
 123     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 124         /* Not allowed to address other CPUs.  */
 125         *tc = env->current_tc;
 126         return env;
 127     }
 128
 129     cs = env_cpu(env);
 130     vpe_idx = tc_idx / cs->nr_threads;
 131     *tc = tc_idx % cs->nr_threads;
 132     other_cs = qemu_get_cpu(vpe_idx);
 133     if (other_cs == NULL) {
 134         return env;
 135     }
 136     cpu = MIPS_CPU(other_cs);
 137     return &cpu->env;
 138 }
 139
 140 /*
 141  * The per VPE CP0_Status register shares some fields with the per TC
 142  * CP0_TCStatus registers. These fields are wired to the same registers,
 143  * so changes to either of them should be reflected on both registers.
 144  *
 145  * Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 146  *
 147  * These helper call synchronizes the regs for a given cpu.
 148  */
 149
 150 /*
 151  * Called for updates to CP0_Status.  Defined in "cpu.h" for gdbstub.c.
 152  * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
 153  *                                   int tc);
 154  */
 155
 156 /* Called for updates to CP0_TCStatus.  */
 157 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 158                              target_ulong v)
 159 {
 160     uint32_t status;
 161     uint32_t tcu, tmx, tasid, tksu;
 162     uint32_t mask = ((1U << CP0St_CU3)
 163                        | (1 << CP0St_CU2)
 164                        | (1 << CP0St_CU1)
 165                        | (1 << CP0St_CU0)
 166                        | (1 << CP0St_MX)
 167                        | (3 << CP0St_KSU));
 168
 169     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 170     tmx = (v >> CP0TCSt_TMX) & 0x1;
 171     tasid = v & cpu->CP0_EntryHi_ASID_mask;
 172     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 173
 174     status = tcu << CP0St_CU0;
 175     status |= tmx << CP0St_MX;
 176     status |= tksu << CP0St_KSU;
 177
 178     cpu->CP0_Status &= ~mask;
 179     cpu->CP0_Status |= status;
 180
 181     /* Sync the TASID with EntryHi.  */
 182     cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
 183     cpu->CP0_EntryHi |= tasid;
 184
 185     compute_hflags(cpu);
 186 }
 187
 188 /* Called for updates to CP0_EntryHi.  */
 189 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 190 {
 191     int32_t *tcst;
 192     uint32_t asid, v = cpu->CP0_EntryHi;
 193
 194     asid = v & cpu->CP0_EntryHi_ASID_mask;
 195
 196     if (tc == cpu->current_tc) {
 197         tcst = &cpu->active_tc.CP0_TCStatus;
 198     } else {
 199         tcst = &cpu->tcs[tc].CP0_TCStatus;
 200     }
 201
 202     *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
 203     *tcst |= asid;
 204 }
 205
 206 /* CP0 helpers */
 207 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 208 {
 209     return env->mvp->CP0_MVPControl;
 210 }
 211
 212 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 213 {
 214     return env->mvp->CP0_MVPConf0;
 215 }
 216
 217 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 218 {
 219     return env->mvp->CP0_MVPConf1;
 220 }
 221
 222 target_ulong helper_mfc0_random(CPUMIPSState *env)
 223 {
 224     return (int32_t)cpu_mips_get_random(env);
 225 }
 226
 227 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 228 {
 229     return env->active_tc.CP0_TCStatus;
 230 }
 231
 232 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 233 {
 234     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 235     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 236
 237     if (other_tc == other->current_tc) {
 238         return other->active_tc.CP0_TCStatus;
 239     } else {
 240         return other->tcs[other_tc].CP0_TCStatus;
 241     }
 242 }
 243
 244 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 245 {
 246     return env->active_tc.CP0_TCBind;
 247 }
 248
 249 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 250 {
 251     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 252     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 253
 254     if (other_tc == other->current_tc) {
 255         return other->active_tc.CP0_TCBind;
 256     } else {
 257         return other->tcs[other_tc].CP0_TCBind;
 258     }
 259 }
 260
 261 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 262 {
 263     return env->active_tc.PC;
 264 }
 265
 266 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 267 {
 268     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 269     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 270
 271     if (other_tc == other->current_tc) {
 272         return other->active_tc.PC;
 273     } else {
 274         return other->tcs[other_tc].PC;
 275     }
 276 }
 277
 278 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 279 {
 280     return env->active_tc.CP0_TCHalt;
 281 }
 282
 283 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 284 {
 285     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 286     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 287
 288     if (other_tc == other->current_tc) {
 289         return other->active_tc.CP0_TCHalt;
 290     } else {
 291         return other->tcs[other_tc].CP0_TCHalt;
 292     }
 293 }
 294
 295 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 296 {
 297     return env->active_tc.CP0_TCContext;
 298 }
 299
 300 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 301 {
 302     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 303     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 304
 305     if (other_tc == other->current_tc) {
 306         return other->active_tc.CP0_TCContext;
 307     } else {
 308         return other->tcs[other_tc].CP0_TCContext;
 309     }
 310 }
 311
 312 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 313 {
 314     return env->active_tc.CP0_TCSchedule;
 315 }
 316
 317 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 318 {
 319     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 320     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 321
 322     if (other_tc == other->current_tc) {
 323         return other->active_tc.CP0_TCSchedule;
 324     } else {
 325         return other->tcs[other_tc].CP0_TCSchedule;
 326     }
 327 }
 328
 329 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 330 {
 331     return env->active_tc.CP0_TCScheFBack;
 332 }
 333
 334 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 335 {
 336     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 337     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 338
 339     if (other_tc == other->current_tc) {
 340         return other->active_tc.CP0_TCScheFBack;
 341     } else {
 342         return other->tcs[other_tc].CP0_TCScheFBack;
 343     }
 344 }
 345
 346 target_ulong helper_mfc0_count(CPUMIPSState *env)
 347 {
 348     return (int32_t)cpu_mips_get_count(env);
 349 }
 350
 351 target_ulong helper_mfc0_saar(CPUMIPSState *env)
 352 {
 353     if ((env->CP0_SAARI & 0x3f) < 2) {
 354         return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
 355     }
 356     return 0;
 357 }
 358
 359 target_ulong helper_mfhc0_saar(CPUMIPSState *env)
 360 {
 361     if ((env->CP0_SAARI & 0x3f) < 2) {
 362         return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
 363     }
 364     return 0;
 365 }
 366
 367 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 368 {
 369     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 370     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 371
 372     return other->CP0_EntryHi;
 373 }
 374
 375 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 376 {
 377     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 378     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 379
 380     return other->CP0_Cause;
 381 }
 382
 383 target_ulong helper_mftc0_status(CPUMIPSState *env)
 384 {
 385     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 386     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 387
 388     return other->CP0_Status;
 389 }
 390
 391 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 392 {
 393     return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift);
 394 }
 395
 396 target_ulong helper_mfc0_maar(CPUMIPSState *env)
 397 {
 398     return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
 399 }
 400
 401 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
 402 {
 403     return env->CP0_MAAR[env->CP0_MAARI] >> 32;
 404 }
 405
 406 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 407 {
 408     return (int32_t)env->CP0_WatchLo[sel];
 409 }
 410
 411 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 412 {
 413     return (int32_t) env->CP0_WatchHi[sel];
 414 }
 415
 416 target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel)
 417 {
 418     return env->CP0_WatchHi[sel] >> 32;
 419 }
 420
 421 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 422 {
 423     target_ulong t0 = env->CP0_Debug;
 424     if (env->hflags & MIPS_HFLAG_DM) {
 425         t0 |= 1 << CP0DB_DM;
 426     }
 427
 428     return t0;
 429 }
 430
 431 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 432 {
 433     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 434     int32_t tcstatus;
 435     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 436
 437     if (other_tc == other->current_tc) {
 438         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 439     } else {
 440         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 441     }
 442
 443     /* XXX: Might be wrong, check with EJTAG spec. */
 444     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 445             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 446 }
 447
 448 #if defined(TARGET_MIPS64)
 449 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 450 {
 451     return env->active_tc.PC;
 452 }
 453
 454 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 455 {
 456     return env->active_tc.CP0_TCHalt;
 457 }
 458
 459 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 460 {
 461     return env->active_tc.CP0_TCContext;
 462 }
 463
 464 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 465 {
 466     return env->active_tc.CP0_TCSchedule;
 467 }
 468
 469 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 470 {
 471     return env->active_tc.CP0_TCScheFBack;
 472 }
 473
 474 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 475 {
 476     return env->CP0_LLAddr >> env->CP0_LLAddr_shift;
 477 }
 478
 479 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
 480 {
 481     return env->CP0_MAAR[env->CP0_MAARI];
 482 }
 483
 484 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 485 {
 486     return env->CP0_WatchLo[sel];
 487 }
 488
 489 target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 490 {
 491     return env->CP0_WatchHi[sel];
 492 }
 493
 494 target_ulong helper_dmfc0_saar(CPUMIPSState *env)
 495 {
 496     if ((env->CP0_SAARI & 0x3f) < 2) {
 497         return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
 498     }
 499     return 0;
 500 }
 501 #endif /* TARGET_MIPS64 */
 502
 503 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 504 {
 505     uint32_t index_p = env->CP0_Index & 0x80000000;
 506     uint32_t tlb_index = arg1 & 0x7fffffff;
 507     if (tlb_index < env->tlb->nb_tlb) {
 508         if (env->insn_flags & ISA_MIPS32R6) {
 509             index_p |= arg1 & 0x80000000;
 510         }
 511         env->CP0_Index = index_p | tlb_index;
 512     }
 513 }
 514
 515 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 516 {
 517     uint32_t mask = 0;
 518     uint32_t newval;
 519
 520     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
 521         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 522                 (1 << CP0MVPCo_EVP);
 523     }
 524     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
 525         mask |= (1 << CP0MVPCo_STLB);
 526     }
 527     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 528
 529     /* TODO: Enable/disable shared TLB, enable/disable VPEs. */
 530
 531     env->mvp->CP0_MVPControl = newval;
 532 }
 533
 534 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 535 {
 536     uint32_t mask;
 537     uint32_t newval;
 538
 539     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 540            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 541     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 542
 543     /*
 544      * Yield scheduler intercept not implemented.
 545      * Gating storage scheduler intercept not implemented.
 546      */
 547
 548     /* TODO: Enable/disable TCs. */
 549
 550     env->CP0_VPEControl = newval;
 551 }
 552
 553 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 554 {
 555     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 556     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 557     uint32_t mask;
 558     uint32_t newval;
 559
 560     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 561            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 562     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
 563
 564     /* TODO: Enable/disable TCs.  */
 565
 566     other->CP0_VPEControl = newval;
 567 }
 568
 569 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
 570 {
 571     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 572     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 573     /* FIXME: Mask away return zero on read bits.  */
 574     return other->CP0_VPEControl;
 575 }
 576
 577 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
 578 {
 579     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 580     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 581
 582     return other->CP0_VPEConf0;
 583 }
 584
 585 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
 586 {
 587     uint32_t mask = 0;
 588     uint32_t newval;
 589
 590     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
 591         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) {
 592             mask |= (0xff << CP0VPEC0_XTC);
 593         }
 594         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 595     }
 596     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
 597
 598     /* TODO: TC exclusive handling due to ERL/EXL. */
 599
 600     env->CP0_VPEConf0 = newval;
 601 }
 602
 603 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
 604 {
 605     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 606     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 607     uint32_t mask = 0;
 608     uint32_t newval;
 609
 610     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 611     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
 612
 613     /* TODO: TC exclusive handling due to ERL/EXL.  */
 614     other->CP0_VPEConf0 = newval;
 615 }
 616
 617 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
 618 {
 619     uint32_t mask = 0;
 620     uint32_t newval;
 621
 622     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 623         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
 624                 (0xff << CP0VPEC1_NCP1);
 625     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
 626
 627     /* UDI not implemented. */
 628     /* CP2 not implemented. */
 629
 630     /* TODO: Handle FPU (CP1) binding. */
 631
 632     env->CP0_VPEConf1 = newval;
 633 }
 634
 635 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
 636 {
 637     /* Yield qualifier inputs not implemented. */
 638     env->CP0_YQMask = 0x00000000;
 639 }
 640
 641 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
 642 {
 643     env->CP0_VPEOpt = arg1 & 0x0000ffff;
 644 }
 645
 646 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
 647
 648 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
 649 {
 650     /* 1k pages not implemented */
 651     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
 652     env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
 653                         | (rxi << (CP0EnLo_XI - 30));
 654 }
 655
 656 #if defined(TARGET_MIPS64)
 657 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
 658
 659 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
 660 {
 661     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
 662     env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
 663 }
 664 #endif
 665
 666 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
 667 {
 668     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
 669     uint32_t newval;
 670
 671     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
 672
 673     env->active_tc.CP0_TCStatus = newval;
 674     sync_c0_tcstatus(env, env->current_tc, newval);
 675 }
 676
 677 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
 678 {
 679     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 680     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 681
 682     if (other_tc == other->current_tc) {
 683         other->active_tc.CP0_TCStatus = arg1;
 684     } else {
 685         other->tcs[other_tc].CP0_TCStatus = arg1;
 686     }
 687     sync_c0_tcstatus(other, other_tc, arg1);
 688 }
 689
 690 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
 691 {
 692     uint32_t mask = (1 << CP0TCBd_TBE);
 693     uint32_t newval;
 694
 695     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
 696         mask |= (1 << CP0TCBd_CurVPE);
 697     }
 698     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
 699     env->active_tc.CP0_TCBind = newval;
 700 }
 701
 702 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
 703 {
 704     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 705     uint32_t mask = (1 << CP0TCBd_TBE);
 706     uint32_t newval;
 707     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 708
 709     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
 710         mask |= (1 << CP0TCBd_CurVPE);
 711     }
 712     if (other_tc == other->current_tc) {
 713         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
 714         other->active_tc.CP0_TCBind = newval;
 715     } else {
 716         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
 717         other->tcs[other_tc].CP0_TCBind = newval;
 718     }
 719 }
 720
 721 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
 722 {
 723     env->active_tc.PC = arg1;
 724     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
 725     env->CP0_LLAddr = 0;
 726     env->lladdr = 0;
 727     /* MIPS16 not implemented. */
 728 }
 729
 730 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
 731 {
 732     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 733     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 734
 735     if (other_tc == other->current_tc) {
 736         other->active_tc.PC = arg1;
 737         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
 738         other->CP0_LLAddr = 0;
 739         other->lladdr = 0;
 740         /* MIPS16 not implemented. */
 741     } else {
 742         other->tcs[other_tc].PC = arg1;
 743         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
 744         other->CP0_LLAddr = 0;
 745         other->lladdr = 0;
 746         /* MIPS16 not implemented. */
 747     }
 748 }
 749
 750 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
 751 {
 752     MIPSCPU *cpu = env_archcpu(env);
 753
 754     env->active_tc.CP0_TCHalt = arg1 & 0x1;
 755
 756     /* TODO: Halt TC / Restart (if allocated+active) TC. */
 757     if (env->active_tc.CP0_TCHalt & 1) {
 758         mips_tc_sleep(cpu, env->current_tc);
 759     } else {
 760         mips_tc_wake(cpu, env->current_tc);
 761     }
 762 }
 763
 764 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
 765 {
 766     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 767     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 768     MIPSCPU *other_cpu = env_archcpu(other);
 769
 770     /* TODO: Halt TC / Restart (if allocated+active) TC. */
 771
 772     if (other_tc == other->current_tc) {
 773         other->active_tc.CP0_TCHalt = arg1;
 774     } else {
 775         other->tcs[other_tc].CP0_TCHalt = arg1;
 776     }
 777
 778     if (arg1 & 1) {
 779         mips_tc_sleep(other_cpu, other_tc);
 780     } else {
 781         mips_tc_wake(other_cpu, other_tc);
 782     }
 783 }
 784
 785 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
 786 {
 787     env->active_tc.CP0_TCContext = arg1;
 788 }
 789
 790 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
 791 {
 792     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 793     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 794
 795     if (other_tc == other->current_tc) {
 796         other->active_tc.CP0_TCContext = arg1;
 797     } else {
 798         other->tcs[other_tc].CP0_TCContext = arg1;
 799     }
 800 }
 801
 802 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
 803 {
 804     env->active_tc.CP0_TCSchedule = arg1;
 805 }
 806
 807 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
 808 {
 809     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 810     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 811
 812     if (other_tc == other->current_tc) {
 813         other->active_tc.CP0_TCSchedule = arg1;
 814     } else {
 815         other->tcs[other_tc].CP0_TCSchedule = arg1;
 816     }
 817 }
 818
 819 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
 820 {
 821     env->active_tc.CP0_TCScheFBack = arg1;
 822 }
 823
 824 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
 825 {
 826     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 827     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 828
 829     if (other_tc == other->current_tc) {
 830         other->active_tc.CP0_TCScheFBack = arg1;
 831     } else {
 832         other->tcs[other_tc].CP0_TCScheFBack = arg1;
 833     }
 834 }
 835
 836 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
 837 {
 838     /* 1k pages not implemented */
 839     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
 840     env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
 841                         | (rxi << (CP0EnLo_XI - 30));
 842 }
 843
 844 #if defined(TARGET_MIPS64)
 845 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
 846 {
 847     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
 848     env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
 849 }
 850 #endif
 851
 852 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
 853 {
 854     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
 855 }
 856
 857 void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1)
 858 {
 859     int32_t old;
 860     old = env->CP0_MemoryMapID;
 861     env->CP0_MemoryMapID = (int32_t) arg1;
 862     /* If the MemoryMapID changes, flush qemu's TLB.  */
 863     if (old != env->CP0_MemoryMapID) {
 864         cpu_mips_tlb_flush(env);
 865     }
 866 }
 867
 868 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
 869 {
 870     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
 871     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
 872         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
 873          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
 874          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
 875         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
 876     }
 877 }
 878
 879 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
 880 {
 881     update_pagemask(env, arg1, &env->CP0_PageMask);
 882 }
 883
 884 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
 885 {
 886     /* SmartMIPS not implemented */
 887     /* 1k pages not implemented */
 888     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
 889                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
 890     compute_hflags(env);
 891     restore_pamask(env);
 892 }
 893
 894 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
 895 {
 896     CPUState *cs = env_cpu(env);
 897
 898     env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
 899     tlb_flush(cs);
 900 }
 901
 902 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
 903 {
 904     CPUState *cs = env_cpu(env);
 905
 906     env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
 907     tlb_flush(cs);
 908 }
 909
 910 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
 911 {
 912     CPUState *cs = env_cpu(env);
 913
 914     env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
 915     tlb_flush(cs);
 916 }
 917
 918 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
 919 {
 920 #if defined(TARGET_MIPS64)
 921     uint64_t mask = 0x3F3FFFFFFFULL;
 922     uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
 923     uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
 924
 925     if ((env->insn_flags & ISA_MIPS32R6)) {
 926         if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
 927             mask &= ~(0x3FULL << CP0PF_BDI);
 928         }
 929         if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
 930             mask &= ~(0x3FULL << CP0PF_GDI);
 931         }
 932         if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
 933             mask &= ~(0x3FULL << CP0PF_UDI);
 934         }
 935         if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
 936             mask &= ~(0x3FULL << CP0PF_MDI);
 937         }
 938         if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
 939             mask &= ~(0x3FULL << CP0PF_PTI);
 940         }
 941     }
 942     env->CP0_PWField = arg1 & mask;
 943
 944     if ((new_ptei >= 32) ||
 945             ((env->insn_flags & ISA_MIPS32R6) &&
 946                     (new_ptei == 0 || new_ptei == 1))) {
 947         env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
 948                 (old_ptei << CP0PF_PTEI);
 949     }
 950 #else
 951     uint32_t mask = 0x3FFFFFFF;
 952     uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
 953     uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
 954
 955     if ((env->insn_flags & ISA_MIPS32R6)) {
 956         if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
 957             mask &= ~(0x3F << CP0PF_GDW);
 958         }
 959         if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
 960             mask &= ~(0x3F << CP0PF_UDW);
 961         }
 962         if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
 963             mask &= ~(0x3F << CP0PF_MDW);
 964         }
 965         if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
 966             mask &= ~(0x3F << CP0PF_PTW);
 967         }
 968     }
 969     env->CP0_PWField = arg1 & mask;
 970
 971     if ((new_ptew >= 32) ||
 972             ((env->insn_flags & ISA_MIPS32R6) &&
 973                     (new_ptew == 0 || new_ptew == 1))) {
 974         env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
 975                 (old_ptew << CP0PF_PTEW);
 976     }
 977 #endif
 978 }
 979
 980 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
 981 {
 982 #if defined(TARGET_MIPS64)
 983     env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
 984 #else
 985     env->CP0_PWSize = arg1 & 0x3FFFFFFF;
 986 #endif
 987 }
 988
 989 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
 990 {
 991     if (env->insn_flags & ISA_MIPS32R6) {
 992         if (arg1 < env->tlb->nb_tlb) {
 993             env->CP0_Wired = arg1;
 994         }
 995     } else {
 996         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
 997     }
 998 }
 999
1000 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1001 {
1002 #if defined(TARGET_MIPS64)
1003     /* PWEn = 0. Hardware page table walking is not implemented. */
1004     env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
1005 #else
1006     env->CP0_PWCtl = (arg1 & 0x800000FF);
1007 #endif
1008 }
1009
1010 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1011 {
1012     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1013 }
1014
1015 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1016 {
1017     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1018 }
1019
1020 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1021 {
1022     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1023 }
1024
1025 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1026 {
1027     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1028 }
1029
1030 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1031 {
1032     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1033 }
1034
1035 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1036 {
1037     uint32_t mask = 0x0000000F;
1038
1039     if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1040         (env->insn_flags & ISA_MIPS32R6)) {
1041         mask |= (1 << 4);
1042     }
1043     if (env->insn_flags & ISA_MIPS32R6) {
1044         mask |= (1 << 5);
1045     }
1046     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1047         mask |= (1 << 29);
1048
1049         if (arg1 & (1 << 29)) {
1050             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1051         } else {
1052             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1053         }
1054     }
1055
1056     env->CP0_HWREna = arg1 & mask;
1057 }
1058
1059 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1060 {
1061     cpu_mips_store_count(env, arg1);
1062 }
1063
1064 void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
1065 {
1066     uint32_t target = arg1 & 0x3f;
1067     if (target <= 1) {
1068         env->CP0_SAARI = target;
1069     }
1070 }
1071
1072 void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
1073 {
1074     uint32_t target = env->CP0_SAARI & 0x3f;
1075     if (target < 2) {
1076         env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
1077         switch (target) {
1078         case 0:
1079             if (env->itu) {
1080                 itc_reconfigure(env->itu);
1081             }
1082             break;
1083         }
1084     }
1085 }
1086
1087 void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
1088 {
1089     uint32_t target = env->CP0_SAARI & 0x3f;
1090     if (target < 2) {
1091         env->CP0_SAAR[target] =
1092             (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
1093             (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
1094         switch (target) {
1095         case 0:
1096             if (env->itu) {
1097                 itc_reconfigure(env->itu);
1098             }
1099             break;
1100         }
1101     }
1102 }
1103
1104 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1105 {
1106     target_ulong old, val, mask;
1107     mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1108     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1109         mask |= 1 << CP0EnHi_EHINV;
1110     }
1111
1112     /* 1k pages not implemented */
1113 #if defined(TARGET_MIPS64)
1114     if (env->insn_flags & ISA_MIPS32R6) {
1115         int entryhi_r = extract64(arg1, 62, 2);
1116         int config0_at = extract32(env->CP0_Config0, 13, 2);
1117         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1118         if ((entryhi_r == 2) ||
1119             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1120             /* skip EntryHi.R field if new value is reserved */
1121             mask &= ~(0x3ull << 62);
1122         }
1123     }
1124     mask &= env->SEGMask;
1125 #endif
1126     old = env->CP0_EntryHi;
1127     val = (arg1 & mask) | (old & ~mask);
1128     env->CP0_EntryHi = val;
1129     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1130         sync_c0_entryhi(env, env->current_tc);
1131     }
1132     /* If the ASID changes, flush qemu's TLB.  */
1133     if ((old & env->CP0_EntryHi_ASID_mask) !=
1134         (val & env->CP0_EntryHi_ASID_mask)) {
1135         tlb_flush(env_cpu(env));
1136     }
1137 }
1138
1139 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1140 {
1141     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1142     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1143
1144     other->CP0_EntryHi = arg1;
1145     sync_c0_entryhi(other, other_tc);
1146 }
1147
1148 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1149 {
1150     cpu_mips_store_compare(env, arg1);
1151 }
1152
1153 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1154 {
1155     uint32_t val, old;
1156
1157     old = env->CP0_Status;
1158     cpu_mips_store_status(env, arg1);
1159     val = env->CP0_Status;
1160
1161     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1162         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1163                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1164                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1165                 env->CP0_Cause);
1166         switch (cpu_mmu_index(env, false)) {
1167         case 3:
1168             qemu_log(", ERL\n");
1169             break;
1170         case MIPS_HFLAG_UM:
1171             qemu_log(", UM\n");
1172             break;
1173         case MIPS_HFLAG_SM:
1174             qemu_log(", SM\n");
1175             break;
1176         case MIPS_HFLAG_KM:
1177             qemu_log("\n");
1178             break;
1179         default:
1180             cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
1181             break;
1182         }
1183     }
1184 }
1185
1186 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1187 {
1188     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1189     uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1190     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1191
1192     other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1193     sync_c0_status(env, other, other_tc);
1194 }
1195
1196 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1197 {
1198     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1199 }
1200
1201 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1202 {
1203     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1204     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1205 }
1206
1207 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1208 {
1209     cpu_mips_store_cause(env, arg1);
1210 }
1211
1212 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1213 {
1214     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1215     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1216
1217     cpu_mips_store_cause(other, arg1);
1218 }
1219
1220 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1221 {
1222     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1223     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1224
1225     return other->CP0_EPC;
1226 }
1227
1228 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1229 {
1230     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1231     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1232
1233     return other->CP0_EBase;
1234 }
1235
1236 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1237 {
1238     target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1239     if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1240         mask |= ~0x3FFFFFFF;
1241     }
1242     env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1243 }
1244
1245 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1246 {
1247     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1248     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1249     target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1250     if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1251         mask |= ~0x3FFFFFFF;
1252     }
1253     other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1254 }
1255
1256 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1257 {
1258     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1259     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1260
1261     switch (idx) {
1262     case 0: return other->CP0_Config0;
1263     case 1: return other->CP0_Config1;
1264     case 2: return other->CP0_Config2;
1265     case 3: return other->CP0_Config3;
1266     /* 4 and 5 are reserved.  */
1267     case 6: return other->CP0_Config6;
1268     case 7: return other->CP0_Config7;
1269     default:
1270         break;
1271     }
1272     return 0;
1273 }
1274
1275 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1276 {
1277     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1278 }
1279
1280 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1281 {
1282     /* tertiary/secondary caches not implemented */
1283     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1284 }
1285
1286 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1287 {
1288     if (env->insn_flags & ASE_MICROMIPS) {
1289         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1290                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
1291     }
1292 }
1293
1294 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1295 {
1296     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1297                        (arg1 & env->CP0_Config4_rw_bitmask);
1298 }
1299
1300 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1301 {
1302     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1303                        (arg1 & env->CP0_Config5_rw_bitmask);
1304     env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
1305             0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
1306     compute_hflags(env);
1307 }
1308
1309 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1310 {
1311     target_long mask = env->CP0_LLAddr_rw_bitmask;
1312     arg1 = arg1 << env->CP0_LLAddr_shift;
1313     env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask);
1314 }
1315
1316 #define MTC0_MAAR_MASK(env) \
1317         ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1318
1319 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1320 {
1321     env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1322 }
1323
1324 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1325 {
1326     env->CP0_MAAR[env->CP0_MAARI] =
1327         (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1328         (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1329 }
1330
1331 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1332 {
1333     int index = arg1 & 0x3f;
1334     if (index == 0x3f) {
1335         /*
1336          * Software may write all ones to INDEX to determine the
1337          *  maximum value supported.
1338          */
1339         env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1340     } else if (index < MIPS_MAAR_MAX) {
1341         env->CP0_MAARI = index;
1342     }
1343     /*
1344      * Other than the all ones, if the value written is not supported,
1345      * then INDEX is unchanged from its previous value.
1346      */
1347 }
1348
1349 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1350 {
1351     /*
1352      * Watch exceptions for instructions, data loads, data stores
1353      * not implemented.
1354      */
1355     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1356 }
1357
1358 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1359 {
1360     uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1361     if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
1362         mask |= 0xFFFFFFFF00000000ULL; /* MMID */
1363     }
1364     env->CP0_WatchHi[sel] = arg1 & mask;
1365     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1366 }
1367
1368 void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1369 {
1370     env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) |
1371                             (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL);
1372 }
1373
1374 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1375 {
1376     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1377     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1378 }
1379
1380 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1381 {
1382     env->CP0_Framemask = arg1; /* XXX */
1383 }
1384
1385 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1386 {
1387     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1388     if (arg1 & (1 << CP0DB_DM)) {
1389         env->hflags |= MIPS_HFLAG_DM;
1390     } else {
1391         env->hflags &= ~MIPS_HFLAG_DM;
1392     }
1393 }
1394
1395 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1396 {
1397     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1398     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1399     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1400
1401     /* XXX: Might be wrong, check with EJTAG spec. */
1402     if (other_tc == other->current_tc) {
1403         other->active_tc.CP0_Debug_tcstatus = val;
1404     } else {
1405         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1406     }
1407     other->CP0_Debug = (other->CP0_Debug &
1408                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1409                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1410 }
1411
1412 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1413 {
1414     env->CP0_Performance0 = arg1 & 0x000007ff;
1415 }
1416
1417 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1418 {
1419     int32_t wst = arg1 & (1 << CP0EC_WST);
1420     int32_t spr = arg1 & (1 << CP0EC_SPR);
1421     int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1422
1423     env->CP0_ErrCtl = wst | spr | itc;
1424
1425     if (itc && !wst && !spr) {
1426         env->hflags |= MIPS_HFLAG_ITC_CACHE;
1427     } else {
1428         env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1429     }
1430 }
1431
1432 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1433 {
1434     if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1435         /*
1436          * If CACHE instruction is configured for ITC tags then make all
1437          * CP0.TagLo bits writable. The actual write to ITC Configuration
1438          * Tag will take care of the read-only bits.
1439          */
1440         env->CP0_TagLo = arg1;
1441     } else {
1442         env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1443     }
1444 }
1445
1446 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1447 {
1448     env->CP0_DataLo = arg1; /* XXX */
1449 }
1450
1451 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1452 {
1453     env->CP0_TagHi = arg1; /* XXX */
1454 }
1455
1456 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1457 {
1458     env->CP0_DataHi = arg1; /* XXX */
1459 }
1460
1461 /* MIPS MT functions */
1462 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1463 {
1464     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1465     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1466
1467     if (other_tc == other->current_tc) {
1468         return other->active_tc.gpr[sel];
1469     } else {
1470         return other->tcs[other_tc].gpr[sel];
1471     }
1472 }
1473
1474 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1475 {
1476     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1477     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1478
1479     if (other_tc == other->current_tc) {
1480         return other->active_tc.LO[sel];
1481     } else {
1482         return other->tcs[other_tc].LO[sel];
1483     }
1484 }
1485
1486 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1487 {
1488     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1489     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1490
1491     if (other_tc == other->current_tc) {
1492         return other->active_tc.HI[sel];
1493     } else {
1494         return other->tcs[other_tc].HI[sel];
1495     }
1496 }
1497
1498 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1499 {
1500     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1501     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1502
1503     if (other_tc == other->current_tc) {
1504         return other->active_tc.ACX[sel];
1505     } else {
1506         return other->tcs[other_tc].ACX[sel];
1507     }
1508 }
1509
1510 target_ulong helper_mftdsp(CPUMIPSState *env)
1511 {
1512     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1513     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1514
1515     if (other_tc == other->current_tc) {
1516         return other->active_tc.DSPControl;
1517     } else {
1518         return other->tcs[other_tc].DSPControl;
1519     }
1520 }
1521
1522 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1523 {
1524     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1525     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1526
1527     if (other_tc == other->current_tc) {
1528         other->active_tc.gpr[sel] = arg1;
1529     } else {
1530         other->tcs[other_tc].gpr[sel] = arg1;
1531     }
1532 }
1533
1534 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1535 {
1536     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1537     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1538
1539     if (other_tc == other->current_tc) {
1540         other->active_tc.LO[sel] = arg1;
1541     } else {
1542         other->tcs[other_tc].LO[sel] = arg1;
1543     }
1544 }
1545
1546 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1547 {
1548     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1549     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1550
1551     if (other_tc == other->current_tc) {
1552         other->active_tc.HI[sel] = arg1;
1553     } else {
1554         other->tcs[other_tc].HI[sel] = arg1;
1555     }
1556 }
1557
1558 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1559 {
1560     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1561     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1562
1563     if (other_tc == other->current_tc) {
1564         other->active_tc.ACX[sel] = arg1;
1565     } else {
1566         other->tcs[other_tc].ACX[sel] = arg1;
1567     }
1568 }
1569
1570 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1571 {
1572     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1573     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1574
1575     if (other_tc == other->current_tc) {
1576         other->active_tc.DSPControl = arg1;
1577     } else {
1578         other->tcs[other_tc].DSPControl = arg1;
1579     }
1580 }
1581
1582 /* MIPS MT functions */
1583 target_ulong helper_dmt(void)
1584 {
1585     /* TODO */
1586     return 0;
1587 }
1588
1589 target_ulong helper_emt(void)
1590 {
1591     /* TODO */
1592     return 0;
1593 }
1594
1595 target_ulong helper_dvpe(CPUMIPSState *env)
1596 {
1597     CPUState *other_cs = first_cpu;
1598     target_ulong prev = env->mvp->CP0_MVPControl;
1599
1600     CPU_FOREACH(other_cs) {
1601         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1602         /* Turn off all VPEs except the one executing the dvpe.  */
1603         if (&other_cpu->env != env) {
1604             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1605             mips_vpe_sleep(other_cpu);
1606         }
1607     }
1608     return prev;
1609 }
1610
1611 target_ulong helper_evpe(CPUMIPSState *env)
1612 {
1613     CPUState *other_cs = first_cpu;
1614     target_ulong prev = env->mvp->CP0_MVPControl;
1615
1616     CPU_FOREACH(other_cs) {
1617         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1618
1619         if (&other_cpu->env != env
1620             /* If the VPE is WFI, don't disturb its sleep.  */
1621             && !mips_vpe_is_wfi(other_cpu)) {
1622             /* Enable the VPE.  */
1623             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1624             mips_vpe_wake(other_cpu); /* And wake it up.  */
1625         }
1626     }
1627     return prev;
1628 }
1629 #endif /* !CONFIG_USER_ONLY */
1630
1631 /* R6 Multi-threading */
1632 #ifndef CONFIG_USER_ONLY
1633 target_ulong helper_dvp(CPUMIPSState *env)
1634 {
1635     CPUState *other_cs = first_cpu;
1636     target_ulong prev = env->CP0_VPControl;
1637
1638     if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1639         CPU_FOREACH(other_cs) {
1640             MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1641             /* Turn off all VPs except the one executing the dvp. */
1642             if (&other_cpu->env != env) {
1643                 mips_vpe_sleep(other_cpu);
1644             }
1645         }
1646         env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1647     }
1648     return prev;
1649 }
1650
1651 target_ulong helper_evp(CPUMIPSState *env)
1652 {
1653     CPUState *other_cs = first_cpu;
1654     target_ulong prev = env->CP0_VPControl;
1655
1656     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1657         CPU_FOREACH(other_cs) {
1658             MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1659             if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1660                 /*
1661                  * If the VP is WFI, don't disturb its sleep.
1662                  * Otherwise, wake it up.
1663                  */
1664                 mips_vpe_wake(other_cpu);
1665             }
1666         }
1667         env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1668     }
1669     return prev;
1670 }
1671 #endif /* !CONFIG_USER_ONLY */